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[34.125.73.210]) by smtp.gmail.com with UTF8SMTPSA id 98e67ed59e1d1-2d84449fc02sm2152712a91.0.2024.08.28.10.17.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 28 Aug 2024 10:17:28 -0700 (PDT) From: Stephen Boyd To: Konrad Dybcio , Bjorn Andersson , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, patches@lists.linux.dev, linux-clk@vger.kernel.org, Neil Armstrong , Amit Pundir , Taniya Das Subject: [PATCH v3 2/2] clk: qcom: gcc-sm8550: Don't use shared clk_ops for QUPs Date: Wed, 28 Aug 2024 10:17:08 -0700 Message-ID: <20240828171722.1251587-3-swboyd@chromium.org> X-Mailer: git-send-email 2.46.0.295.g3b9ea8a38a-goog In-Reply-To: <20240828171722.1251587-1-swboyd@chromium.org> References: <20240828171722.1251587-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The QUPs aren't shared in a way that requires parking the RCG at an always on parent in case some other entity turns on the clk. The hardware is capable of setting a new frequency itself with the DFS mode, so parking is unnecessary. Furthermore, there aren't any GDSCs for these devices, so there isn't a possibility of the GDSC turning on the clks for housekeeping purposes. This wasn't a problem to mark these clks shared until we started parking shared RCGs at clk registration time in commit 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration"). Parking at init is actually harmful to the UART when earlycon is used. If the device is pumping out data while the frequency changes you'll see garbage on the serial console until the driver can probe and actually set a proper frequency. Revert the QUP part of commit 929c75d57566 ("clk: qcom: gcc-sm8550: Mark RCGs shared where applicable") so that the QUPs don't get parked during clk registration and break UART operations. Fixes: 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration") Fixes: 929c75d57566 ("clk: qcom: gcc-sm8550: Mark RCGs shared where applica= ble") Cc: Konrad Dybcio Cc: Bjorn Andersson Cc: Taniya Das Cc: Neil Armstrong Reported-by: Amit Pundir Closes: https://lore.kernel.org/CAMi1Hd1KQBE4kKUdAn8E5FV+BiKzuv+8FoyWQrrTHP= DoYTuhgA@mail.gmail.com Tested-by: Amit Pundir Signed-off-by: Stephen Boyd --- drivers/clk/qcom/gcc-sm8550.c | 52 +++++++++++++++++------------------ 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c index 7944ddb4b47d..0244a05866b8 100644 --- a/drivers/clk/qcom/gcc-sm8550.c +++ b/drivers/clk/qcom/gcc-sm8550.c @@ -536,7 +536,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s0_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -551,7 +551,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s1_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -566,7 +566,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s2_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -581,7 +581,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s3_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -596,7 +596,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s4_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -611,7 +611,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s5_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -626,7 +626,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s6_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -641,7 +641,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s7_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -656,7 +656,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s8_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -671,7 +671,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s9_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -700,7 +700,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src =3D { @@ -717,7 +717,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src =3D { @@ -750,7 +750,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src =3D { @@ -767,7 +767,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src =3D { @@ -784,7 +784,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src =3D { @@ -801,7 +801,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src =3D { @@ -818,7 +818,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src =3D { @@ -835,7 +835,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src =3D { @@ -852,7 +852,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src =3D { @@ -869,7 +869,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src =3D { @@ -886,7 +886,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src =3D { @@ -903,7 +903,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src =3D { @@ -920,7 +920,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src =3D { @@ -937,7 +937,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src =3D { @@ -975,7 +975,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_= init =3D { .parent_data =3D gcc_parent_data_8, .num_parents =3D ARRAY_SIZE(gcc_parent_data_8), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src =3D { @@ -992,7 +992,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src =3D { --=20 https://chromeos.dev