From nobody Thu Dec 18 15:26:05 2025 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A2701A4AA4 for ; Wed, 28 Aug 2024 17:17:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724865449; cv=none; b=ilqIfXm+9jSOhxNISyAqSMvQMY64hNErOb1NIiNBNsuu9C2tl9FeK7I1Fa8U4v88VrtLFVwKgeJGxMgbQglsVckJ6T5kTsNef32dbOjGkccHGXJoLikC4xxSrV8nfcqD7QumVBNr7DF+JVfyPq4zZknZsqDfnccg+A6lC91ORss= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724865449; c=relaxed/simple; bh=bwSfvGk4ew41Pt/E/xxobSD02oCnd1HApU3EHn2TPXE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Bmz9plxzfJZw3izgk1Q1H/1bn7T4Iz+UIDxWjQs6wNmyVP/12y7WNOxDQo/jfF8qtkRfpBA1kYhV6nBZkHcVtD+Yv6gqPxCbjNrLVVal3dDnO8INd9LKlZC6IpGmtaJg9XEYFAxk4sKbSh+Lo5wqH0sZBN1Gji8p6UUzTzxkRRQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=cxKNMulr; arc=none smtp.client-ip=209.85.214.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="cxKNMulr" Received: by mail-pl1-f173.google.com with SMTP id d9443c01a7336-2020ac89cabso65988935ad.1 for ; Wed, 28 Aug 2024 10:17:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1724865447; x=1725470247; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=obx3p45lH094wmMafo9xf2AcgFRs0OVi52Qu0+34Bqo=; b=cxKNMulruytZG+HLC7rGGJ6ShymYnMN9dmqeyFljiemLc6HqLXoQbg07dUjKN9ItWf LGFcC5bD65Mqe6KXwTS6ninfbHap+eapmR08PZ9VJt+p2QkkzgIzHta7ibp/lHFy2ILw 7UZe68bOJJ63VnDbhyc4b2pwYMAj129nztfQg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724865447; x=1725470247; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=obx3p45lH094wmMafo9xf2AcgFRs0OVi52Qu0+34Bqo=; b=Xh4kh7tc4VviauFXU+dDMoBFpy1Tv92jE1DdIBi2SFPM0e9MDDCcosM/YA/2l6BgAp /M7uYD/aNx01h3U04xu3uGYykySk6m5xs+2Ayc7RDSgEBkX3oxq/cguiCnOlhY0a1nWl v6HHgAnopIedSC1WIeUnYcr5Teb3emr06y2txIZ2lX8smaOjGg7vLpilbSF7eUfBOFqO /app0SX7PE6QrJI2iR/8sK3pfErDPqvpGGzQIczvwATlFCrNFsgtIqSnZAcOaoXo6RON +9q0IHHy+va2eF8s3hbAiQKoxPW4OUQaEPSMPB/am8jdipCwv8jvemc0eGEQDO+BoACv oKWg== X-Gm-Message-State: AOJu0Yw9lspcKOqBu9+CgvQragVjQT/DWg5fzC+nkVQwzyztt9jZuy+W Z4qUWalbU9GBaS2sfSeCaSUKpWHMnKUopEAAf7JrUCtkrvXectft3HE4amEA1w== X-Google-Smtp-Source: AGHT+IFo3yNR44JAQjq7tPpX6XRV0bUKv+iJl4hPJ7g/ZEOViXftZwzGkPdFX7wZrnrsNHYoVWKkMw== X-Received: by 2002:a17:903:2a85:b0:1fd:9a23:90cc with SMTP id d9443c01a7336-2050c34c67dmr2292795ad.26.1724865447375; Wed, 28 Aug 2024 10:17:27 -0700 (PDT) Received: from localhost (210.73.125.34.bc.googleusercontent.com. [34.125.73.210]) by smtp.gmail.com with UTF8SMTPSA id d9443c01a7336-20385ae81afsm101148885ad.252.2024.08.28.10.17.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 28 Aug 2024 10:17:26 -0700 (PDT) From: Stephen Boyd To: Konrad Dybcio , Bjorn Andersson , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, patches@lists.linux.dev, linux-clk@vger.kernel.org, Neil Armstrong , Amit Pundir , Taniya Das Subject: [PATCH v3 1/2] clk: qcom: dispcc-sc7180: Only park display clks at init Date: Wed, 28 Aug 2024 10:17:07 -0700 Message-ID: <20240828171722.1251587-2-swboyd@chromium.org> X-Mailer: git-send-email 2.46.0.295.g3b9ea8a38a-goog In-Reply-To: <20240828171722.1251587-1-swboyd@chromium.org> References: <20240828171722.1251587-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Amit Pundir reports that audio and USB-C host mode stops working on sm8550 after commit 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration"). That's because the gcc_usb30_prim_master_clk_src clk is registered and clk_rcg2_shared_init() parks it on XO. Running USB at a slower speed than the link supports is effectively under-clocking the USB link and probably confusing the downstream USB devices. We didn't need to change all the shared RCGs to park on XO at registration time in commit commit 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration"). Instead, we only needed to park the few display related clks on sc7180 to fix the issue. Fix sm8550 (and likely other qcom SoCs) by skipping the parking part of clk_rcg2_shared_init(). Make that the default init clk_op for shared RCGs, but keep the part where we cache the config register as that's still necessary to figure out the true parent of the clk is. Introduce another set of clk_ops 'clk_rcg2_shared_init_park' that does what clk_rcg2_shared_init() was doing and use that for the display clks on sc7180. This fixes the sm8550 problem and limits the "park upon registration" logic to the display clks that need it. Fixes: 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration") Cc: Konrad Dybcio Cc: Bjorn Andersson Cc: Taniya Das Cc: Neil Armstrong Reported-by: Amit Pundir Closes: https://lore.kernel.org/CAMi1Hd1KQBE4kKUdAn8E5FV+BiKzuv+8FoyWQrrTHP= DoYTuhgA@mail.gmail.com Signed-off-by: Stephen Boyd Tested-by: Johan Hovold --- drivers/clk/qcom/clk-rcg.h | 1 + drivers/clk/qcom/clk-rcg2.c | 36 +++++++++++++++++++++++++++++--- drivers/clk/qcom/dispcc-sc7180.c | 8 +++---- 3 files changed, 38 insertions(+), 7 deletions(-) diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index d7414361e432..5f479a29d969 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -198,6 +198,7 @@ extern const struct clk_ops clk_byte2_ops; extern const struct clk_ops clk_pixel_ops; extern const struct clk_ops clk_gfx3d_ops; extern const struct clk_ops clk_rcg2_shared_ops; +extern const struct clk_ops clk_rcg2_shared_init_park_ops; extern const struct clk_ops clk_dp_ops; =20 struct clk_rcg_dfs_data { diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 30b19bd39d08..5f0b729d7115 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -1305,6 +1305,31 @@ clk_rcg2_shared_recalc_rate(struct clk_hw *hw, unsig= ned long parent_rate) } =20 static int clk_rcg2_shared_init(struct clk_hw *hw) +{ + struct clk_rcg2 *rcg =3D to_clk_rcg2(hw); + + /* + * Cache the cfg so that the parent is properly mapped at registration. + */ + regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &rcg->parked_cfg); + + return 0; +} + +const struct clk_ops clk_rcg2_shared_ops =3D { + .init =3D clk_rcg2_shared_init, + .enable =3D clk_rcg2_shared_enable, + .disable =3D clk_rcg2_shared_disable, + .get_parent =3D clk_rcg2_shared_get_parent, + .set_parent =3D clk_rcg2_shared_set_parent, + .recalc_rate =3D clk_rcg2_shared_recalc_rate, + .determine_rate =3D clk_rcg2_determine_rate, + .set_rate =3D clk_rcg2_shared_set_rate, + .set_rate_and_parent =3D clk_rcg2_shared_set_rate_and_parent, +}; +EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops); + +static int clk_rcg2_shared_init_park(struct clk_hw *hw) { /* * This does a few things: @@ -1335,8 +1360,13 @@ static int clk_rcg2_shared_init(struct clk_hw *hw) return 0; } =20 -const struct clk_ops clk_rcg2_shared_ops =3D { - .init =3D clk_rcg2_shared_init, +/* + * Like clk_rcg2_shared_ops but also park the clk at init to avoid the par= ent + * from being shutdown, getting the clk stuck when it is turned on + * automatically by the GDSC. + */ +const struct clk_ops clk_rcg2_shared_init_park_ops =3D { + .init =3D clk_rcg2_shared_init_park, .enable =3D clk_rcg2_shared_enable, .disable =3D clk_rcg2_shared_disable, .get_parent =3D clk_rcg2_shared_get_parent, @@ -1346,7 +1376,7 @@ const struct clk_ops clk_rcg2_shared_ops =3D { .set_rate =3D clk_rcg2_shared_set_rate, .set_rate_and_parent =3D clk_rcg2_shared_set_rate_and_parent, }; -EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops); +EXPORT_SYMBOL_GPL(clk_rcg2_shared_init_park_ops); =20 /* Common APIs to be used for DFS based RCGR */ static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l, diff --git a/drivers/clk/qcom/dispcc-sc7180.c b/drivers/clk/qcom/dispcc-sc7= 180.c index 4710247be530..068af819f23e 100644 --- a/drivers/clk/qcom/dispcc-sc7180.c +++ b/drivers/clk/qcom/dispcc-sc7180.c @@ -154,7 +154,7 @@ static struct clk_rcg2 disp_cc_mdss_ahb_clk_src =3D { .parent_data =3D disp_cc_parent_data_4, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_4), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_shared_init_park_ops, }, }; =20 @@ -263,7 +263,7 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src =3D { .name =3D "disp_cc_mdss_mdp_clk_src", .parent_data =3D disp_cc_parent_data_3, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_shared_init_park_ops, }, }; =20 @@ -291,7 +291,7 @@ static struct clk_rcg2 disp_cc_mdss_rot_clk_src =3D { .name =3D "disp_cc_mdss_rot_clk_src", .parent_data =3D disp_cc_parent_data_3, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_shared_init_park_ops, }, }; =20 @@ -305,7 +305,7 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src =3D { .name =3D "disp_cc_mdss_vsync_clk_src", .parent_data =3D disp_cc_parent_data_0, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_shared_init_park_ops, }, }; =20 --=20 https://chromeos.dev From nobody Thu Dec 18 15:26:05 2025 Received: from mail-pg1-f182.google.com (mail-pg1-f182.google.com [209.85.215.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06F021A707A for ; Wed, 28 Aug 2024 17:17:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724865451; cv=none; b=nebyXVKkg2i9rfMNtvq5n82PS2UM3098Segrq8mLqjtOIIiNrCnPbIXyrh4qgctecqqJ/1yf/LLRdA3qHp3LDOLbnIzM4LFL0xJOgRo1+1GaGfMPRyDA3+0k75vDqW1iDVa11SiP4WlpWWrsPStl5DF8g7Myg0QqRkt+g09qjRc= ARC-Message-Signature: i=1; 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[34.125.73.210]) by smtp.gmail.com with UTF8SMTPSA id 98e67ed59e1d1-2d84449fc02sm2152712a91.0.2024.08.28.10.17.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 28 Aug 2024 10:17:28 -0700 (PDT) From: Stephen Boyd To: Konrad Dybcio , Bjorn Andersson , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, patches@lists.linux.dev, linux-clk@vger.kernel.org, Neil Armstrong , Amit Pundir , Taniya Das Subject: [PATCH v3 2/2] clk: qcom: gcc-sm8550: Don't use shared clk_ops for QUPs Date: Wed, 28 Aug 2024 10:17:08 -0700 Message-ID: <20240828171722.1251587-3-swboyd@chromium.org> X-Mailer: git-send-email 2.46.0.295.g3b9ea8a38a-goog In-Reply-To: <20240828171722.1251587-1-swboyd@chromium.org> References: <20240828171722.1251587-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The QUPs aren't shared in a way that requires parking the RCG at an always on parent in case some other entity turns on the clk. The hardware is capable of setting a new frequency itself with the DFS mode, so parking is unnecessary. Furthermore, there aren't any GDSCs for these devices, so there isn't a possibility of the GDSC turning on the clks for housekeeping purposes. This wasn't a problem to mark these clks shared until we started parking shared RCGs at clk registration time in commit 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration"). Parking at init is actually harmful to the UART when earlycon is used. If the device is pumping out data while the frequency changes you'll see garbage on the serial console until the driver can probe and actually set a proper frequency. Revert the QUP part of commit 929c75d57566 ("clk: qcom: gcc-sm8550: Mark RCGs shared where applicable") so that the QUPs don't get parked during clk registration and break UART operations. Fixes: 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration") Fixes: 929c75d57566 ("clk: qcom: gcc-sm8550: Mark RCGs shared where applica= ble") Cc: Konrad Dybcio Cc: Bjorn Andersson Cc: Taniya Das Cc: Neil Armstrong Reported-by: Amit Pundir Closes: https://lore.kernel.org/CAMi1Hd1KQBE4kKUdAn8E5FV+BiKzuv+8FoyWQrrTHP= DoYTuhgA@mail.gmail.com Tested-by: Amit Pundir Signed-off-by: Stephen Boyd --- drivers/clk/qcom/gcc-sm8550.c | 52 +++++++++++++++++------------------ 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c index 7944ddb4b47d..0244a05866b8 100644 --- a/drivers/clk/qcom/gcc-sm8550.c +++ b/drivers/clk/qcom/gcc-sm8550.c @@ -536,7 +536,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s0_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -551,7 +551,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s1_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -566,7 +566,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s2_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -581,7 +581,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s3_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -596,7 +596,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s4_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -611,7 +611,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s5_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -626,7 +626,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s6_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -641,7 +641,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s7_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -656,7 +656,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s8_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -671,7 +671,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s9_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -700,7 +700,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src =3D { @@ -717,7 +717,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src =3D { @@ -750,7 +750,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src =3D { @@ -767,7 +767,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src =3D { @@ -784,7 +784,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src =3D { @@ -801,7 +801,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src =3D { @@ -818,7 +818,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src =3D { @@ -835,7 +835,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src =3D { @@ -852,7 +852,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src =3D { @@ -869,7 +869,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src =3D { @@ -886,7 +886,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src =3D { @@ -903,7 +903,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src =3D { @@ -920,7 +920,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src =3D { @@ -937,7 +937,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src =3D { @@ -975,7 +975,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_= init =3D { .parent_data =3D gcc_parent_data_8, .num_parents =3D ARRAY_SIZE(gcc_parent_data_8), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src =3D { @@ -992,7 +992,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src =3D { --=20 https://chromeos.dev