From nobody Fri Dec 19 08:54:44 2025 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11260177982; Wed, 28 Aug 2024 14:37:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724855860; cv=none; b=BZMjFpKoINASbpfY8UJI80Dxlofng44iqvzpfdEajO8RByZCNMDiDINSJHqvrHJOIIhxedU2RUx0YLPTPP9sX0NZplw14Eq/WAFzXIWWIDm+T8P0qiZiIE/XUXikEE1PydaMA/E+o+0XAYjZOf8YJWG2ArZuckulbYV6pXsHEps= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724855860; c=relaxed/simple; bh=j1ZdAt9Z10RbBRdUdOnJFsCAuSZUM7cdJHp5gtvnHHg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=KTCXP5gzZSWQ7IlJBmWYAk10fRBDVBC021ryPwoezkDk6USIWviKZGXCdQ4pCOBv3ahEZb/Fz2tWAwMnFF0g++GeEyn5m2ZjjOHLsX3bCqokvebZdkJj906HtBj/Xx3ZwvvVah/E9MjUFOZ+TjyNUFM9M1VEXVrDfjGiNurbC0s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=gZG3z47R; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="gZG3z47R" Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 47SDc7d2019018; Wed, 28 Aug 2024 16:37:14 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= uEF0ao6f0gyrAH6MbtQ5SiSNrPGghcolYp9r1uQWemY=; b=gZG3z47RRUr+BsNa qIuLJu5LhpQOKu8pmqwvg8swt3XB6F38jZtVpxTaekcO0AqlrvfTZF2IlTXSa6R6 AiaYJ3KkLRLI0zu6gvOXBnRU1Ba1x1YDWz/YIAJjfhQmwa1jMHakaDxFUw0SqkHA Wkcf+VLWKfXtapAzrV220Tw+G+0FGCZ1S8x44+ZfJWJmK2R6/ZYqeFBURsQO4HIF DJaE+md2UwcjCqBNTjNBYNN+lu5G9sjybOyWfUis6m96cslfz4CWu/+GAbidSEaz liGE4TdJl4cy6dgVtswFtsABe/htG6bOE1h1cqkbFHq/U3BUuPXzhUDqDIpRpDHb t9fkmQ== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 41a4xyrb4s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 28 Aug 2024 16:37:13 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id CEE1A40049; Wed, 28 Aug 2024 16:37:09 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id C3F9B26F22C; Wed, 28 Aug 2024 16:36:21 +0200 (CEST) Received: from localhost (10.129.178.212) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Wed, 28 Aug 2024 16:36:21 +0200 From: Christian Bruel To: , , , , , , , CC: , , , , , , Christian Bruel Subject: [PATCH v4 1/5] dt-bindings: phy: Add STM32MP25 COMBOPHY bindings Date: Wed, 28 Aug 2024 16:34:48 +0200 Message-ID: <20240828143452.1407532-2-christian.bruel@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240828143452.1407532-1-christian.bruel@foss.st.com> References: <20240828143452.1407532-1-christian.bruel@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-28_05,2024-08-27_01,2024-05-17_01 Content-Type: text/plain; charset="utf-8" Document the bindings for STM32 COMBOPHY interface, used to support the PCIe and USB3 stm32mp25 drivers. Following entries can be used to tune caracterisation parameters - st,output-micro-ohms and st,output-vswing-microvolt bindings entries to tune the impedance and voltage swing using discrete simulation results - st,rx-equalizer register to set the internal rx equalizer filter value. Signed-off-by: Christian Bruel --- .../bindings/phy/st,stm32mp25-combophy.yaml | 128 ++++++++++++++++++ 1 file changed, 128 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/st,stm32mp25-comb= ophy.yaml diff --git a/Documentation/devicetree/bindings/phy/st,stm32mp25-combophy.ya= ml b/Documentation/devicetree/bindings/phy/st,stm32mp25-combophy.yaml new file mode 100644 index 000000000000..8d4a40b94507 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/st,stm32mp25-combophy.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/st,stm32mp25-combophy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32MP25 USB3/PCIe COMBOPHY + +maintainers: + - Christian Bruel + +description: + Single lane PHY shared (exclusive) between the USB3 and PCIe controllers. + Supports 5Gbit/s for USB3 and PCIe gen2 or 2.5Gbit/s for PCIe gen1. + +properties: + compatible: + const: st,stm32mp25-combophy + + reg: + maxItems: 1 + + "#phy-cells": + const: 1 + + clocks: + minItems: 2 + items: + - description: apb Bus clock mandatory to access registers. + - description: ker Internal RCC reference clock for USB3 or PCIe + - description: pad Optional on board clock input for PCIe only. Typi= cally an + external 100Mhz oscillator wired on dedicated CLKIN p= ad. Used as reference + clock input instead of the ker + + clock-names: + minItems: 2 + items: + - const: apb + - const: ker + - const: pad + + resets: + maxItems: 1 + + reset-names: + const: phy + + power-domains: + maxItems: 1 + + wakeup-source: true + + interrupts: + maxItems: 1 + description: interrupt used for wakeup + + access-controllers: + minItems: 1 + maxItems: 2 + + st,syscfg: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to the SYSCON entry required for configuring PCIe + or USB3. + + st,ssc-on: + type: boolean + description: + A boolean property whose presence indicates that the SSC for common = clock + needs to be set. + + st,rx-equalizer: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + default: 2 + description: + A 3 bit value to tune the RX fixed equalizer setting for optimal eye= compliance + + st,output-micro-ohms: + minimum: 3999000 + maximum: 6090000 + default: 4968000 + description: + A value property to tune the Single Ended Output Impedance, simulati= ons results + at 25C for a VDDP=3D0.8V. The hardware accepts discrete values in th= is range. + + st,output-vswing-microvolt: + minimum: 442000 + maximum: 803000 + default: 803000 + description: + A value property in microvolt to tune the Single Ended Output Voltag= e Swing to change the + Vlo, Vhi for a VDDP =3D 0.8V. The hardware accepts discrete values i= n this range. + +required: + - "#phy-cells" + - compatible + - clocks + - clock-names + - reg + - resets + - reset-names + - st,syscfg + +additionalProperties: false + +examples: + - | + #include + #include + #include + + combophy: phy@480c0000 { + compatible =3D "st,stm32mp25-combophy"; + reg =3D <0x480c0000 0x1000>; + #phy-cells =3D <1>; + clocks =3D <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>; + clock-names =3D "apb", "ker"; + resets =3D <&rcc USB3PCIEPHY_R>; + reset-names =3D "phy"; + st,syscfg =3D <&syscfg>; + access-controllers =3D <&rifsc 67>; + power-domains =3D <&CLUSTER_PD>; + wakeup-source; + interrupts-extended =3D <&exti1 45 IRQ_TYPE_EDGE_FALLING>; + }; +... --=20 2.34.1