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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240828-dts-qcom-label-v1-4-b27b72130247@linaro.org> References: <20240828-dts-qcom-label-v1-0-b27b72130247@linaro.org> In-Reply-To: <20240828-dts-qcom-label-v1-0-b27b72130247@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=12936; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=iTiyki3nb7d+M6yJoDKpNpaMfTLhGQH10mtoP7umNHI=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBmzs8VVJ1m7qFJ8Cpcmhs/DnoXquVxuK+dcx1B0 ddRYkhvSdOJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZs7PFQAKCRDBN2bmhouD 16XqD/981PKakraoip7gdgLQ5TEWf9KaZ+CkypMxhy+zFWyvzIsPGI4UuYPF8uhMeMEu3Xar5fb ZHiIL+6oIFjt6+9fN+5tKf4xFiIbyHFY/eNSjoSyKKAp65sVfoK40cz/VGdZeZjDg541GjOUs4L 6aST6nw7Sx6EQQthdioEdVwUJ/QvRO070ZCokjkHsY77x7YZcep7nHGYxdsDLL0eVF+2VrelwNk Jyp6pkGf78ijW4kzEpM5bMREIP/NphsFwMvulnthwTGwVFiZ4jBJ/wz9PQWwpy4KM4usmDukL11 wBMv5UbktmJgcKigCd9IBqpf8Kj1l/VUX7RNk41gMPP0AaQPgUpvSQ1pYZKFF/FeSknCdmZq9MN bbBrmTyGnaMJDkzRSN0EUc4bKPXJMrXWDKZqcmtIxRDLYISIRAQ8alA/mngfQ4Wg2sjHyTFoNz/ uvCwdUNZz9LaZc6/S+A84NuPXqMkhJzhs4UeiPOaZft1AV8PZacqWZmts3RsnuUXBFMxt6tjymT /b4uViiG/x/l1OKcksW2pQbSbCCJpegAg8GGeGZ9siBpncZnH9vhUUnnTsLIxxKqtjY3zSeEyiq A8WG/kegaxOsTnAdlYHR/ZOnNFMnZXUlxOoCQbWCkywpk9fhgD+gGTcalQx2fBytJ6yzQMq8cwC xLc1R01yeGIlcvA== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski --- .../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 16 +-- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 140 ++++++++++-------= ---- 2 files changed, 78 insertions(+), 78 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/a= rch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 6a28cab97189..83208b10f994 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -346,18 +346,18 @@ skin-temp-crit { cooling-maps { map0 { trip =3D <&skin_temp_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; =20 map1 { trip =3D <&skin_temp_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 80a57aa22839..7138466f2439 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -44,7 +44,7 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a78c"; reg =3D <0x0 0x0>; @@ -52,14 +52,14 @@ CPU0: cpu@0 { enable-method =3D "psci"; capacity-dmips-mhz =3D <981>; dynamic-power-coefficient =3D <549>; - next-level-cache =3D <&L2_0>; - power-domains =3D <&CPU_PD0>; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_= SHARED>; #cooling-cells =3D <2>; - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -72,7 +72,7 @@ L3_0: l3-cache { }; }; =20 - CPU1: cpu@100 { + cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "arm,cortex-a78c"; reg =3D <0x0 0x100>; @@ -80,14 +80,14 @@ CPU1: cpu@100 { enable-method =3D "psci"; capacity-dmips-mhz =3D <981>; dynamic-power-coefficient =3D <549>; - next-level-cache =3D <&L2_100>; - power-domains =3D <&CPU_PD1>; + next-level-cache =3D <&l2_100>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_= SHARED>; #cooling-cells =3D <2>; - L2_100: l2-cache { + l2_100: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -95,7 +95,7 @@ L2_100: l2-cache { }; }; =20 - CPU2: cpu@200 { + cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "arm,cortex-a78c"; reg =3D <0x0 0x200>; @@ -103,14 +103,14 @@ CPU2: cpu@200 { enable-method =3D "psci"; capacity-dmips-mhz =3D <981>; dynamic-power-coefficient =3D <549>; - next-level-cache =3D <&L2_200>; - power-domains =3D <&CPU_PD2>; + next-level-cache =3D <&l2_200>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_= SHARED>; #cooling-cells =3D <2>; - L2_200: l2-cache { + l2_200: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -118,7 +118,7 @@ L2_200: l2-cache { }; }; =20 - CPU3: cpu@300 { + cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "arm,cortex-a78c"; reg =3D <0x0 0x300>; @@ -126,14 +126,14 @@ CPU3: cpu@300 { enable-method =3D "psci"; capacity-dmips-mhz =3D <981>; dynamic-power-coefficient =3D <549>; - next-level-cache =3D <&L2_300>; - power-domains =3D <&CPU_PD3>; + next-level-cache =3D <&l2_300>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_= SHARED>; #cooling-cells =3D <2>; - L2_300: l2-cache { + l2_300: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -141,7 +141,7 @@ L2_300: l2-cache { }; }; =20 - CPU4: cpu@400 { + cpu4: cpu@400 { device_type =3D "cpu"; compatible =3D "arm,cortex-x1c"; reg =3D <0x0 0x400>; @@ -149,14 +149,14 @@ CPU4: cpu@400 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <590>; - next-level-cache =3D <&L2_400>; - power-domains =3D <&CPU_PD4>; + next-level-cache =3D <&l2_400>; + power-domains =3D <&cpu_pd4>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_= SHARED>; #cooling-cells =3D <2>; - L2_400: l2-cache { + l2_400: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -164,7 +164,7 @@ L2_400: l2-cache { }; }; =20 - CPU5: cpu@500 { + cpu5: cpu@500 { device_type =3D "cpu"; compatible =3D "arm,cortex-x1c"; reg =3D <0x0 0x500>; @@ -172,14 +172,14 @@ CPU5: cpu@500 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <590>; - next-level-cache =3D <&L2_500>; - power-domains =3D <&CPU_PD5>; + next-level-cache =3D <&l2_500>; + power-domains =3D <&cpu_pd5>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_= SHARED>; #cooling-cells =3D <2>; - L2_500: l2-cache { + l2_500: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -187,7 +187,7 @@ L2_500: l2-cache { }; }; =20 - CPU6: cpu@600 { + cpu6: cpu@600 { device_type =3D "cpu"; compatible =3D "arm,cortex-x1c"; reg =3D <0x0 0x600>; @@ -195,14 +195,14 @@ CPU6: cpu@600 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <590>; - next-level-cache =3D <&L2_600>; - power-domains =3D <&CPU_PD6>; + next-level-cache =3D <&l2_600>; + power-domains =3D <&cpu_pd6>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_= SHARED>; #cooling-cells =3D <2>; - L2_600: l2-cache { + l2_600: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -210,7 +210,7 @@ L2_600: l2-cache { }; }; =20 - CPU7: cpu@700 { + cpu7: cpu@700 { device_type =3D "cpu"; compatible =3D "arm,cortex-x1c"; reg =3D <0x0 0x700>; @@ -218,14 +218,14 @@ CPU7: cpu@700 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <590>; - next-level-cache =3D <&L2_700>; - power-domains =3D <&CPU_PD7>; + next-level-cache =3D <&l2_700>; + power-domains =3D <&cpu_pd7>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_= SHARED>; #cooling-cells =3D <2>; - L2_700: l2-cache { + l2_700: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -236,35 +236,35 @@ L2_700: l2-cache { cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; =20 core4 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core5 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core6 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core7 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; @@ -272,7 +272,7 @@ core7 { idle-states { entry-method =3D "psci"; =20 - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + LITTLE_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "little-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -282,7 +282,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + BIG_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "big-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -294,7 +294,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { }; =20 domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { + cluster_sleep_0: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x4100c344>; entry-latency-us =3D <3263>; @@ -593,57 +593,57 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&LITTLE_cpu_sleep_0>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&LITTLE_cpu_sleep_0>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&LITTLE_cpu_sleep_0>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&LITTLE_cpu_sleep_0>; }; =20 - CPU_PD4: power-domain-cpu4 { + cpu_pd4: power-domain-cpu4 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&BIG_cpu_sleep_0>; }; =20 - CPU_PD5: power-domain-cpu5 { + cpu_pd5: power-domain-cpu5 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&BIG_cpu_sleep_0>; }; =20 - CPU_PD6: power-domain-cpu6 { + cpu_pd6: power-domain-cpu6 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&BIG_cpu_sleep_0>; }; =20 - CPU_PD7: power-domain-cpu7 { + cpu_pd7: power-domain-cpu7 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&BIG_cpu_sleep_0>; }; =20 - CLUSTER_PD: power-domain-cpu-cluster0 { + cluster_pd: power-domain-cpu-cluster0 { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_SLEEP_0>; + domain-idle-states =3D <&cluster_sleep_0>; }; }; =20 @@ -5111,7 +5111,7 @@ apps_rsc: rsc@18200000 { qcom,tcs-config =3D , , , ; label =3D "apps_rsc"; - power-domains =3D <&CLUSTER_PD>; + power-domains =3D <&cluster_pd>; =20 apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; --=20 2.43.0