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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240828-dts-qcom-label-v1-3-b27b72130247@linaro.org> References: <20240828-dts-qcom-label-v1-0-b27b72130247@linaro.org> In-Reply-To: <20240828-dts-qcom-label-v1-0-b27b72130247@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=34642; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=9xFo0eqJACDBytuCX1V3rePCU01EF0FRKpoOtpC7OFY=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBmzs8UMELBjqcHqp4mkarCQ9R8xKMZfKolkGJD9 E/aI3x/okaJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZs7PFAAKCRDBN2bmhouD 14vCD/9JPA4PgC8tWuaqW4Dc8P+fliZAefUvmoL2PjX7O0ocebn4L963ZiRi7P3/0L53wYTSCjv q5o0z6WmTyibB+ICexaFt7cUss3lSfxPI/8adSx+YuYVONk+qWMucmAhy2RkZVmdGI2nwHVHZtY n2PbXhDjlN/MKCZivHlNROTCm9IyhMzQ+tLbvlhNIGJZ2bIL0BMeJUxARlawH+Uj/va3wx4yspY H2J4Y18bjIHwMAu9ahUWmGrYfknK3fy7Td9DxOBGQ8jpMGZNkB9IfhPV27v01ij/xYVTcyIkVCL 0RZxL36nKRaxbe6A51Wn4Nv2Q9VOup0/S+EHNiz/tkRIyGs1D2WZf1T8Vl89gRTIpLoUBWaKLBQ LyfW6RSIyi9pPhanG9S1h9h8Bmmx0E6g323/uVdxaShA8pjCqZdfArh4FvZMCjVuAzv1IVvk4dP 1yAK7R59xdL34l/G90NKACHSHcR6nqy+0bhCJV5e//wEBb4fhWhtScgncW2nR2yVX7ubd7R/VNH dF/N00qac+BtzfApjhZB7tt5zZBdqppzf01QGrVaNk/q2AbkJDjShzdt+IjwPpm+E2QDeB0KR5u jzg/PvODSO5IICXkNDqqbYUfF4beSY1bfM5UlvLuCHzFIG1rIErkenEcRa+oO59OJvfD64ZGCfM nuAmDUkg1cN0VzA== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sc7180-firmware-tfa.dtsi | 84 ++--- .../arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 8 +- .../boot/dts/qcom/sc7180-trogdor-homestar.dtsi | 8 +- .../boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi | 8 +- arch/arm64/boot/dts/qcom/sc7180.dtsi | 344 ++++++++++-------= ---- arch/arm64/boot/dts/qcom/sm7125.dtsi | 16 +- 6 files changed, 234 insertions(+), 234 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-firmware-tfa.dtsi b/arch/arm64= /boot/dts/qcom/sc7180-firmware-tfa.dtsi index ee35a454dbf6..f362b6b436ce 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-firmware-tfa.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-firmware-tfa.dtsi @@ -6,82 +6,82 @@ * by Qualcomm firmware. */ =20 -&CPU0 { +&cpu0 { /delete-property/ power-domains; /delete-property/ power-domain-names; =20 - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&LITTLE_cpu_sleep_0 + &LITTLE_cpu_sleep_1 + &cluster_sleep_0>; }; =20 -&CPU1 { +&cpu1 { /delete-property/ power-domains; /delete-property/ power-domain-names; =20 - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&LITTLE_cpu_sleep_0 + &LITTLE_cpu_sleep_1 + &cluster_sleep_0>; }; =20 -&CPU2 { +&cpu2 { /delete-property/ power-domains; /delete-property/ power-domain-names; =20 - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&LITTLE_cpu_sleep_0 + &LITTLE_cpu_sleep_1 + &cluster_sleep_0>; }; =20 -&CPU3 { +&cpu3 { /delete-property/ power-domains; /delete-property/ power-domain-names; =20 - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&LITTLE_cpu_sleep_0 + &LITTLE_cpu_sleep_1 + &cluster_sleep_0>; }; =20 -&CPU4 { +&cpu4 { /delete-property/ power-domains; /delete-property/ power-domain-names; =20 - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&LITTLE_cpu_sleep_0 + &LITTLE_cpu_sleep_1 + &cluster_sleep_0>; }; =20 -&CPU5 { +&cpu5 { /delete-property/ power-domains; /delete-property/ power-domain-names; =20 - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&LITTLE_cpu_sleep_0 + &LITTLE_cpu_sleep_1 + &cluster_sleep_0>; }; =20 -&CPU6 { +&cpu6 { /delete-property/ power-domains; /delete-property/ power-domain-names; =20 - cpu-idle-states =3D <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&BIG_cpu_sleep_0 + &BIG_cpu_sleep_1 + &cluster_sleep_0>; }; =20 -&CPU7 { +&cpu7 { /delete-property/ power-domains; /delete-property/ power-domain-names; =20 - cpu-idle-states =3D <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&BIG_cpu_sleep_0 + &BIG_cpu_sleep_1 + &cluster_sleep_0>; }; =20 /delete-node/ &domain_idle_states; =20 &idle_states { - CLUSTER_SLEEP_0: cluster-sleep-0 { + cluster_sleep_0: cluster-sleep-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "cluster-power-down"; arm,psci-suspend-param =3D <0x40003444>; @@ -92,15 +92,15 @@ CLUSTER_SLEEP_0: cluster-sleep-0 { }; }; =20 -/delete-node/ &CPU_PD0; -/delete-node/ &CPU_PD1; -/delete-node/ &CPU_PD2; -/delete-node/ &CPU_PD3; -/delete-node/ &CPU_PD4; -/delete-node/ &CPU_PD5; -/delete-node/ &CPU_PD6; -/delete-node/ &CPU_PD7; -/delete-node/ &CLUSTER_PD; +/delete-node/ &cpu_pd0; +/delete-node/ &cpu_pd1; +/delete-node/ &cpu_pd2; +/delete-node/ &cpu_pd3; +/delete-node/ &cpu_pd4; +/delete-node/ &cpu_pd5; +/delete-node/ &cpu_pd6; +/delete-node/ &cpu_pd7; +/delete-node/ &cluster_pd; =20 &apps_rsc { /delete-property/ power-domains; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm= 64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index 3c124bbe2f4c..25b17b0425f2 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -53,14 +53,14 @@ skin-temp-crit { cooling-maps { map0 { trip =3D <&skin_temp_alert0>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; =20 map1 { trip =3D <&skin_temp_alert1>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/a= rm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi index b2df22faafe8..f57976906d63 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi @@ -71,14 +71,14 @@ skin-temp-crit { cooling-maps { map0 { trip =3D <&skin_temp_alert0>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; =20 map1 { trip =3D <&skin_temp_alert1>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi b/arc= h/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi index af89d80426ab..d4925be3b1fc 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi @@ -78,14 +78,14 @@ skin-temp-crit { cooling-maps { map0 { trip =3D <&skin_temp_alert0>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; =20 map1 { trip =3D <&skin_temp_alert1>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qco= m/sc7180.dtsi index b5ebf8980325..4a080fc77e6e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -77,23 +77,23 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "qcom,kryo468"; reg =3D <0x0 0x0>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; capacity-dmips-mhz =3D <415>; dynamic-power-coefficient =3D <137>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; qcom,freq-domain =3D <&cpufreq_hw 0>; - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -106,23 +106,23 @@ L3_0: l3-cache { }; }; =20 - CPU1: cpu@100 { + cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "qcom,kryo468"; reg =3D <0x0 0x100>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD1>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; capacity-dmips-mhz =3D <415>; dynamic-power-coefficient =3D <137>; - next-level-cache =3D <&L2_100>; + next-level-cache =3D <&l2_100>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; qcom,freq-domain =3D <&cpufreq_hw 0>; - L2_100: l2-cache { + l2_100: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -130,23 +130,23 @@ L2_100: l2-cache { }; }; =20 - CPU2: cpu@200 { + cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "qcom,kryo468"; reg =3D <0x0 0x200>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD2>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; capacity-dmips-mhz =3D <415>; dynamic-power-coefficient =3D <137>; - next-level-cache =3D <&L2_200>; + next-level-cache =3D <&l2_200>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; qcom,freq-domain =3D <&cpufreq_hw 0>; - L2_200: l2-cache { + l2_200: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -154,23 +154,23 @@ L2_200: l2-cache { }; }; =20 - CPU3: cpu@300 { + cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "qcom,kryo468"; reg =3D <0x0 0x300>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD3>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; capacity-dmips-mhz =3D <415>; dynamic-power-coefficient =3D <137>; - next-level-cache =3D <&L2_300>; + next-level-cache =3D <&l2_300>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; qcom,freq-domain =3D <&cpufreq_hw 0>; - L2_300: l2-cache { + l2_300: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -178,23 +178,23 @@ L2_300: l2-cache { }; }; =20 - CPU4: cpu@400 { + cpu4: cpu@400 { device_type =3D "cpu"; compatible =3D "qcom,kryo468"; reg =3D <0x0 0x400>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD4>; + power-domains =3D <&cpu_pd4>; power-domain-names =3D "psci"; capacity-dmips-mhz =3D <415>; dynamic-power-coefficient =3D <137>; - next-level-cache =3D <&L2_400>; + next-level-cache =3D <&l2_400>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; qcom,freq-domain =3D <&cpufreq_hw 0>; - L2_400: l2-cache { + l2_400: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -202,23 +202,23 @@ L2_400: l2-cache { }; }; =20 - CPU5: cpu@500 { + cpu5: cpu@500 { device_type =3D "cpu"; compatible =3D "qcom,kryo468"; reg =3D <0x0 0x500>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD5>; + power-domains =3D <&cpu_pd5>; power-domain-names =3D "psci"; capacity-dmips-mhz =3D <415>; dynamic-power-coefficient =3D <137>; - next-level-cache =3D <&L2_500>; + next-level-cache =3D <&l2_500>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; qcom,freq-domain =3D <&cpufreq_hw 0>; - L2_500: l2-cache { + l2_500: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -226,23 +226,23 @@ L2_500: l2-cache { }; }; =20 - CPU6: cpu@600 { + cpu6: cpu@600 { device_type =3D "cpu"; compatible =3D "qcom,kryo468"; reg =3D <0x0 0x600>; clocks =3D <&cpufreq_hw 1>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD6>; + power-domains =3D <&cpu_pd6>; power-domain-names =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <480>; - next-level-cache =3D <&L2_600>; + next-level-cache =3D <&l2_600>; operating-points-v2 =3D <&cpu6_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; qcom,freq-domain =3D <&cpufreq_hw 1>; - L2_600: l2-cache { + l2_600: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -250,23 +250,23 @@ L2_600: l2-cache { }; }; =20 - CPU7: cpu@700 { + cpu7: cpu@700 { device_type =3D "cpu"; compatible =3D "qcom,kryo468"; reg =3D <0x0 0x700>; clocks =3D <&cpufreq_hw 1>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD7>; + power-domains =3D <&cpu_pd7>; power-domain-names =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <480>; - next-level-cache =3D <&L2_700>; + next-level-cache =3D <&l2_700>; operating-points-v2 =3D <&cpu6_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; qcom,freq-domain =3D <&cpufreq_hw 1>; - L2_700: l2-cache { + l2_700: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -277,35 +277,35 @@ L2_700: l2-cache { cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; =20 core4 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core5 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core6 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core7 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; @@ -313,7 +313,7 @@ core7 { idle_states: idle-states { entry-method =3D "psci"; =20 - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + LITTLE_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "little-power-down"; arm,psci-suspend-param =3D <0x40000003>; @@ -323,7 +323,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { local-timer-stop; }; =20 - LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { + LITTLE_cpu_sleep_1: cpu-sleep-0-1 { compatible =3D "arm,idle-state"; idle-state-name =3D "little-rail-power-down"; arm,psci-suspend-param =3D <0x40000004>; @@ -333,7 +333,7 @@ LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + BIG_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "big-power-down"; arm,psci-suspend-param =3D <0x40000003>; @@ -343,7 +343,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_1: cpu-sleep-1-1 { + BIG_cpu_sleep_1: cpu-sleep-1-1 { compatible =3D "arm,idle-state"; idle-state-name =3D "big-rail-power-down"; arm,psci-suspend-param =3D <0x40000004>; @@ -355,7 +355,7 @@ BIG_CPU_SLEEP_1: cpu-sleep-1-1 { }; =20 domain_idle_states: domain-idle-states { - CLUSTER_SLEEP_PC: cluster-sleep-0 { + cluster_sleep_PC: cluster-sleep-0 { compatible =3D "domain-idle-state"; idle-state-name =3D "cluster-l3-power-collapse"; arm,psci-suspend-param =3D <0x41000044>; @@ -364,7 +364,7 @@ CLUSTER_SLEEP_PC: cluster-sleep-0 { min-residency-us =3D <6118>; }; =20 - CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { + cluster_sleep_CX_RET: cluster-sleep-1 { compatible =3D "domain-idle-state"; idle-state-name =3D "cluster-cx-retention"; arm,psci-suspend-param =3D <0x41001244>; @@ -373,7 +373,7 @@ CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { min-residency-us =3D <8467>; }; =20 - CLUSTER_AOSS_SLEEP: cluster-sleep-2 { + cluster_aoss_sleep: cluster-sleep-2 { compatible =3D "domain-idle-state"; idle-state-name =3D "cluster-power-down"; arm,psci-suspend-param =3D <0x4100b244>; @@ -583,59 +583,59 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: cpu0 { + cpu_pd0: cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&LITTLE_cpu_sleep_0 &LITTLE_cpu_sleep_1>; }; =20 - CPU_PD1: cpu1 { + cpu_pd1: cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&LITTLE_cpu_sleep_0 &LITTLE_cpu_sleep_1>; }; =20 - CPU_PD2: cpu2 { + cpu_pd2: cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&LITTLE_cpu_sleep_0 &LITTLE_cpu_sleep_1>; }; =20 - CPU_PD3: cpu3 { + cpu_pd3: cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&LITTLE_cpu_sleep_0 &LITTLE_cpu_sleep_1>; }; =20 - CPU_PD4: cpu4 { + cpu_pd4: cpu4 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&LITTLE_cpu_sleep_0 &LITTLE_cpu_sleep_1>; }; =20 - CPU_PD5: cpu5 { + cpu_pd5: cpu5 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&LITTLE_cpu_sleep_0 &LITTLE_cpu_sleep_1>; }; =20 - CPU_PD6: cpu6 { + cpu_pd6: cpu6 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&BIG_cpu_sleep_0 &BIG_cpu_sleep_1>; }; =20 - CPU_PD7: cpu7 { + cpu_pd7: cpu7 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&BIG_cpu_sleep_0 &BIG_cpu_sleep_1>; }; =20 - CLUSTER_PD: cpu-cluster0 { + cluster_pd: cpu-cluster0 { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_SLEEP_PC - &CLUSTER_SLEEP_CX_RET - &CLUSTER_AOSS_SLEEP>; + domain-idle-states =3D <&cluster_sleep_PC + &cluster_sleep_CX_RET + &cluster_aoss_sleep>; }; }; =20 @@ -2546,7 +2546,7 @@ etm@7040000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07040000 0 0x1000>; =20 - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -2566,7 +2566,7 @@ etm@7140000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07140000 0 0x1000>; =20 - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -2586,7 +2586,7 @@ etm@7240000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07240000 0 0x1000>; =20 - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -2606,7 +2606,7 @@ etm@7340000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07340000 0 0x1000>; =20 - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -2626,7 +2626,7 @@ etm@7440000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07440000 0 0x1000>; =20 - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -2646,7 +2646,7 @@ etm@7540000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07540000 0 0x1000>; =20 - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -2666,7 +2666,7 @@ etm@7640000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07640000 0 0x1000>; =20 - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -2686,7 +2686,7 @@ etm@7740000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07740000 0 0x1000>; =20 - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3734,7 +3734,7 @@ apps_rsc: rsc@18200000 { , , ; - power-domains =3D <&CLUSTER_PD>; + power-domains =3D <&cluster_pd>; =20 rpmhcc: clock-controller { compatible =3D "qcom,sc7180-rpmh-clk"; @@ -4063,21 +4063,21 @@ cpu0_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu0_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu0_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4111,21 +4111,21 @@ cpu1_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu1_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu1_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4159,21 +4159,21 @@ cpu2_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu2_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu2_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4207,21 +4207,21 @@ cpu3_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu3_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu3_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4255,21 +4255,21 @@ cpu4_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu4_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu4_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4303,21 +4303,21 @@ cpu5_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu5_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu5_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4351,13 +4351,13 @@ cpu6_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu6_alert0>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu6_alert1>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4391,13 +4391,13 @@ cpu7_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu7_alert0>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu7_alert1>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4431,13 +4431,13 @@ cpu8_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu8_alert0>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu8_alert1>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4471,13 +4471,13 @@ cpu9_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu9_alert0>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu9_alert1>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm7125.dtsi b/arch/arm64/boot/dts/qco= m/sm7125.dtsi index 12dd72859a43..a53145a610a3 100644 --- a/arch/arm64/boot/dts/qcom/sm7125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm7125.dtsi @@ -6,11 +6,11 @@ #include "sc7180.dtsi" =20 /* SM7125 uses Kryo 465 instead of Kryo 468 */ -&CPU0 { compatible =3D "qcom,kryo465"; }; -&CPU1 { compatible =3D "qcom,kryo465"; }; -&CPU2 { compatible =3D "qcom,kryo465"; }; -&CPU3 { compatible =3D "qcom,kryo465"; }; -&CPU4 { compatible =3D "qcom,kryo465"; }; -&CPU5 { compatible =3D "qcom,kryo465"; }; -&CPU6 { compatible =3D "qcom,kryo465"; }; -&CPU7 { compatible =3D "qcom,kryo465"; }; +&cpu0 { compatible =3D "qcom,kryo465"; }; +&cpu1 { compatible =3D "qcom,kryo465"; }; +&cpu2 { compatible =3D "qcom,kryo465"; }; +&cpu3 { compatible =3D "qcom,kryo465"; }; +&cpu4 { compatible =3D "qcom,kryo465"; }; +&cpu5 { compatible =3D "qcom,kryo465"; }; +&cpu6 { compatible =3D "qcom,kryo465"; }; +&cpu7 { compatible =3D "qcom,kryo465"; }; --=20 2.43.0