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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240828-dts-qcom-label-v1-13-b27b72130247@linaro.org> References: <20240828-dts-qcom-label-v1-0-b27b72130247@linaro.org> In-Reply-To: <20240828-dts-qcom-label-v1-0-b27b72130247@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=10774; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=pHMfjW7Be5Bb6vXPXSXyPM3vsfQI/WhQfh6/a0UVoxk=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBmzs8d8TYVgepqrq8xY7Rjvx8iMafZNpRx8eybU m4JO+u4qlSJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZs7PHQAKCRDBN2bmhouD 173TD/43RZKdfeyuIRXJtPJ7y2+oIHpRgssMwEMknpgv8VVtyDcf/zvlK7X9ZCxttdX1dhU3PDQ UJmFtLuaiVccFLRPVei2f7dsMgtvhF3uI708ICdXQSD8SCqfKVZcKMUnaJTeoTMp1cF8f0nujLL xP5aZDhRHKrf9LvGK06q1Sl+urMOtdbjbF4VMjTWYPyhdDiQJDv0YR9V0/CxwIhk2b/DOPz0lQN IYhafzX50x20vu8VKuaLWMQP3VN+hYHl/09XyA2B099cQyGLbmI/CKt/6xRTFsMshYPvwHTbH19 OzdmVLipG1osVgDvnrPCt9Wcnv6K5R1eg2cmWDYhYdQ8nbkrBOY+0iIMAKvYywC90cghlA+R1c/ oBSHoDlC4qmoiR53W00kJI3WYvrWb8x0qyztUxxIPckRXuJGVzLT5Cu15e8EacK1JiU/ZbzJwW0 tf0GcvppT2jkHmTwTWZ0Nnyh7CRCYBUYeFlj2Jhg14pIQIuWBSn6Bj+IY8/22/gZBvgXqzhICZ1 mSaC2Ui1RIVZ+wn084m3CYfSk7Rls10mNc5Sl+hQnEdk6WST0VmoP+Wz+eGFfFC8UEchBUQ8XQG vGj49ctYAG5+fDgobHEEc0nL8e81KoIJFdFXfn5DEGcc3g9EqlavSUBMHmQMaaKWq2vgRtqEL3W 2Lrk+0b5bCYk+ow== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 142 +++++++++++++++++--------------= ---- 1 file changed, 71 insertions(+), 71 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index 01ac3769ffa6..1af936467a14 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -68,18 +68,18 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a520"; reg =3D <0 0>; =20 clocks =3D <&cpufreq_hw 0>; =20 - power-domains =3D <&CPU_PD0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; =20 enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; =20 @@ -87,7 +87,7 @@ CPU0: cpu@0 { =20 #cooling-cells =3D <2>; =20 - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -101,18 +101,18 @@ L3_0: l3-cache { }; }; =20 - CPU1: cpu@100 { + cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "arm,cortex-a520"; reg =3D <0 0x100>; =20 clocks =3D <&cpufreq_hw 0>; =20 - power-domains =3D <&CPU_PD1>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; =20 enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; =20 @@ -121,18 +121,18 @@ CPU1: cpu@100 { #cooling-cells =3D <2>; }; =20 - CPU2: cpu@200 { + cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "arm,cortex-a720"; reg =3D <0 0x200>; =20 clocks =3D <&cpufreq_hw 3>; =20 - power-domains =3D <&CPU_PD2>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; =20 enable-method =3D "psci"; - next-level-cache =3D <&L2_200>; + next-level-cache =3D <&l2_200>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <238>; =20 @@ -140,7 +140,7 @@ CPU2: cpu@200 { =20 #cooling-cells =3D <2>; =20 - L2_200: l2-cache { + l2_200: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -148,18 +148,18 @@ L2_200: l2-cache { }; }; =20 - CPU3: cpu@300 { + cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "arm,cortex-a720"; reg =3D <0 0x300>; =20 clocks =3D <&cpufreq_hw 3>; =20 - power-domains =3D <&CPU_PD3>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; =20 enable-method =3D "psci"; - next-level-cache =3D <&L2_200>; + next-level-cache =3D <&l2_200>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <238>; =20 @@ -168,18 +168,18 @@ CPU3: cpu@300 { #cooling-cells =3D <2>; }; =20 - CPU4: cpu@400 { + cpu4: cpu@400 { device_type =3D "cpu"; compatible =3D "arm,cortex-a720"; reg =3D <0 0x400>; =20 clocks =3D <&cpufreq_hw 3>; =20 - power-domains =3D <&CPU_PD4>; + power-domains =3D <&cpu_pd4>; power-domain-names =3D "psci"; =20 enable-method =3D "psci"; - next-level-cache =3D <&L2_400>; + next-level-cache =3D <&l2_400>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <238>; =20 @@ -187,7 +187,7 @@ CPU4: cpu@400 { =20 #cooling-cells =3D <2>; =20 - L2_400: l2-cache { + l2_400: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -195,18 +195,18 @@ L2_400: l2-cache { }; }; =20 - CPU5: cpu@500 { + cpu5: cpu@500 { device_type =3D "cpu"; compatible =3D "arm,cortex-a720"; reg =3D <0 0x500>; =20 clocks =3D <&cpufreq_hw 1>; =20 - power-domains =3D <&CPU_PD5>; + power-domains =3D <&cpu_pd5>; power-domain-names =3D "psci"; =20 enable-method =3D "psci"; - next-level-cache =3D <&L2_500>; + next-level-cache =3D <&l2_500>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <238>; =20 @@ -214,7 +214,7 @@ CPU5: cpu@500 { =20 #cooling-cells =3D <2>; =20 - L2_500: l2-cache { + l2_500: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -222,18 +222,18 @@ L2_500: l2-cache { }; }; =20 - CPU6: cpu@600 { + cpu6: cpu@600 { device_type =3D "cpu"; compatible =3D "arm,cortex-a720"; reg =3D <0 0x600>; =20 clocks =3D <&cpufreq_hw 1>; =20 - power-domains =3D <&CPU_PD6>; + power-domains =3D <&cpu_pd6>; power-domain-names =3D "psci"; =20 enable-method =3D "psci"; - next-level-cache =3D <&L2_600>; + next-level-cache =3D <&l2_600>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <238>; =20 @@ -241,7 +241,7 @@ CPU6: cpu@600 { =20 #cooling-cells =3D <2>; =20 - L2_600: l2-cache { + l2_600: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -249,18 +249,18 @@ L2_600: l2-cache { }; }; =20 - CPU7: cpu@700 { + cpu7: cpu@700 { device_type =3D "cpu"; compatible =3D "arm,cortex-x4"; reg =3D <0 0x700>; =20 clocks =3D <&cpufreq_hw 2>; =20 - power-domains =3D <&CPU_PD7>; + power-domains =3D <&cpu_pd7>; power-domain-names =3D "psci"; =20 enable-method =3D "psci"; - next-level-cache =3D <&L2_700>; + next-level-cache =3D <&l2_700>; capacity-dmips-mhz =3D <1894>; dynamic-power-coefficient =3D <588>; =20 @@ -268,7 +268,7 @@ CPU7: cpu@700 { =20 #cooling-cells =3D <2>; =20 - L2_700: l2-cache { + l2_700: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -279,35 +279,35 @@ L2_700: l2-cache { cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; =20 core4 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core5 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core6 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core7 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; @@ -315,7 +315,7 @@ core7 { idle-states { entry-method =3D "psci"; =20 - SILVER_CPU_SLEEP_0: cpu-sleep-0-0 { + SILVER_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "silver-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -325,7 +325,7 @@ SILVER_CPU_SLEEP_0: cpu-sleep-0-0 { local-timer-stop; }; =20 - GOLD_CPU_SLEEP_0: cpu-sleep-1-0 { + GOLD_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "gold-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -335,7 +335,7 @@ GOLD_CPU_SLEEP_0: cpu-sleep-1-0 { local-timer-stop; }; =20 - GOLD_PLUS_CPU_SLEEP_0: cpu-sleep-2-0 { + GOLD_PLUS_cpu_sleep_0: cpu-sleep-2-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "gold-plus-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -347,7 +347,7 @@ GOLD_PLUS_CPU_SLEEP_0: cpu-sleep-2-0 { }; =20 domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { + cluster_sleep_0: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41000044>; entry-latency-us =3D <750>; @@ -355,7 +355,7 @@ CLUSTER_SLEEP_0: cluster-sleep-0 { min-residency-us =3D <9144>; }; =20 - CLUSTER_SLEEP_1: cluster-sleep-1 { + cluster_sleep_1: cluster-sleep-1 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x4100c344>; entry-latency-us =3D <2800>; @@ -411,58 +411,58 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&SILVER_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&SILVER_cpu_sleep_0>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&SILVER_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&SILVER_cpu_sleep_0>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&SILVER_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&SILVER_cpu_sleep_0>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&GOLD_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&GOLD_cpu_sleep_0>; }; =20 - CPU_PD4: power-domain-cpu4 { + cpu_pd4: power-domain-cpu4 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&GOLD_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&GOLD_cpu_sleep_0>; }; =20 - CPU_PD5: power-domain-cpu5 { + cpu_pd5: power-domain-cpu5 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&GOLD_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&GOLD_cpu_sleep_0>; }; =20 - CPU_PD6: power-domain-cpu6 { + cpu_pd6: power-domain-cpu6 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&GOLD_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&GOLD_cpu_sleep_0>; }; =20 - CPU_PD7: power-domain-cpu7 { + cpu_pd7: power-domain-cpu7 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&GOLD_PLUS_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&GOLD_PLUS_cpu_sleep_0>; }; =20 - CLUSTER_PD: power-domain-cluster { + cluster_pd: power-domain-cluster { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_SLEEP_0>, - <&CLUSTER_SLEEP_1>; + domain-idle-states =3D <&cluster_sleep_0>, + <&cluster_sleep_1>; }; }; =20 @@ -5083,7 +5083,7 @@ apps_rsc: rsc@17a00000 { , ; =20 - power-domains =3D <&CLUSTER_PD>; + power-domains =3D <&cluster_pd>; =20 qcom,tcs-offset =3D <0xd00>; qcom,drv-id =3D <2>; --=20 2.43.0