From nobody Fri Dec 19 10:42:17 2025 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4175172BDE; Wed, 28 Aug 2024 11:15:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724843737; cv=none; b=h93OUxS3xDIz2pe/L3oFhKuRBmFWoCmeWVw6EnZxojNP4YOamDhfPZC8NlLbRaegTDhO1VPIKSX4vkjNCKObXk4jLAmFdHFs9Fmh6D8EvbEvt5FRn5RdN0Oz6IrMYHq82sXTnE1RQqyZdUER8AEb38h2RYnrTya1gjxVCLN4cOY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724843737; c=relaxed/simple; bh=ctB09K24SqurJXr/ft7jZw9+UyPyGGy5oMXc/OeTwQI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=olZ6VU0iuUk0swxZ5PpqvkVA12zOkTWT8rB2MHVd5LqLE8TMeAWjYjTI3UArgLBocA0MI0TWKRQD5KRY3MII8/+5wXVh9vJT22qi/wGZPMuMKcmj3Np5qUxGp6uvyNum0tkZw76Uf0VLncq8T3181SLyxRfpK7B///1wqQJB8qs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=KDWI9zu9; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="KDWI9zu9" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 47SBFEd7061201; Wed, 28 Aug 2024 06:15:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1724843715; bh=8gtxeFvNGfixNaQDUEiJ8QxpXzP8Fi+ODc2rKVMoRio=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=KDWI9zu9XG9uRFc3VMjVvT01O2oCWWHqWGc9WPV5TVgpRJoC5U23j6lJksTYkAqUE IpOjgvZ0HFJXwZ40lQv9k853GMee+nUNtkvT/5jalB6g+vway6sAoSSPvtuiqi+ME8 EaIWsIObW2mHGEWsa26ePrgPaDnypvwCt3TTGTxo= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 47SBFES5048632 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Aug 2024 06:15:14 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 28 Aug 2024 06:15:14 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 28 Aug 2024 06:15:14 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 47SBF109122618; Wed, 28 Aug 2024 06:15:10 -0500 From: Manorit Chawdhry Date: Wed, 28 Aug 2024 16:45:00 +0530 Subject: [PATCH v5 2/5] arm64: dts: ti: Refactor J784s4-evm to a common file Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240828-b4-upstream-j742s2-v5-2-9aaa02a0faee@ti.com> References: <20240828-b4-upstream-j742s2-v5-0-9aaa02a0faee@ti.com> In-Reply-To: <20240828-b4-upstream-j742s2-v5-0-9aaa02a0faee@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Udit Kumar , Neha Malcom Francis , Aniket Limaye , Beleswar Padhi , Manorit Chawdhry X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1724843701; l=77397; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=ctB09K24SqurJXr/ft7jZw9+UyPyGGy5oMXc/OeTwQI=; b=NDXbBMH4AKtQ+3cKJBK2DuZEI5GerQN/NUmJY3QYGLiDxItVnidaWKQiRJSQqredfly9cfiWq SAHnafOgUdIB8yfbqnm3umjih9NHWiy6BsEcEznvrciwB+yxIEwUr67 X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Refactor J784s4-evm to a common file which uses the superset device to allow reuse in j742s2-evm which uses the subset part. Signed-off-by: Manorit Chawdhry Reviewed-by: Beleswar Padhi --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 1427 +---------------= --- .../boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 1437 ++++++++++++++++= ++++ 2 files changed, 1440 insertions(+), 1424 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts= /ti/k3-j784s4-evm.dts index ea27519d7b89..a84bde08f85e 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -10,176 +10,23 @@ #include #include #include "k3-j784s4.dtsi" +#include "k3-j784s4-j742s2-evm-common.dtsi" =20 / { compatible =3D "ti,j784s4-evm", "ti,j784s4"; model =3D "Texas Instruments J784S4 EVM"; =20 - chosen { - stdout-path =3D "serial2:115200n8"; - }; - - aliases { - serial0 =3D &wkup_uart0; - serial1 =3D &mcu_uart0; - serial2 =3D &main_uart8; - mmc0 =3D &main_sdhci0; - mmc1 =3D &main_sdhci1; - i2c0 =3D &wkup_i2c0; - i2c3 =3D &main_i2c0; - ethernet0 =3D &mcu_cpsw_port1; - ethernet1 =3D &main_cpsw1_port1; - }; - memory@80000000 { - device_type =3D "memory"; - bootph-all; /* 32G RAM */ reg =3D <0x00000000 0x80000000 0x00000000 0x80000000>, <0x00000008 0x80000000 0x00000007 0x80000000>; + device_type =3D "memory"; + bootph-all; }; =20 reserved_memory: reserved-memory { #address-cells =3D <2>; #size-cells =3D <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg =3D <0x00 0x9e800000 0x00 0x01800000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa0000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa0100000 0x00 0xf00000>; - no-map; - }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - main_r5fss2_core0_memory_region: r5f-memory@a6100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - main_r5fss2_core1_memory_region: r5f-memory@a7100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: c71-dma-memory@a8000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa8000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: c71-memory@a8100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa8100000 0x00 0xf00000>; - no-map; - }; - - c71_1_dma_memory_region: c71-dma-memory@a9000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa9000000 0x00 0x100000>; - no-map; - }; - - c71_1_memory_region: c71-memory@a9100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa9100000 0x00 0xf00000>; - no-map; - }; - - c71_2_dma_memory_region: c71-dma-memory@aa000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xaa000000 0x00 0x100000>; - no-map; - }; - - c71_2_memory_region: c71-memory@aa100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xaa100000 0x00 0xf00000>; - no-map; - }; =20 c71_3_dma_memory_region: c71-dma-memory@ab000000 { compatible =3D "shared-dma-pool"; @@ -193,1286 +40,18 @@ c71_3_memory_region: c71-memory@ab100000 { no-map; }; }; - - evm_12v0: regulator-evm12v0 { - /* main supply */ - compatible =3D "regulator-fixed"; - regulator-name =3D "evm_12v0"; - regulator-min-microvolt =3D <12000000>; - regulator-max-microvolt =3D <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_3v3: regulator-vsys3v3 { - /* Output of LM5140 */ - compatible =3D "regulator-fixed"; - regulator-name =3D "vsys_3v3"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - vin-supply =3D <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_5v0: regulator-vsys5v0 { - /* Output of LM5140 */ - compatible =3D "regulator-fixed"; - regulator-name =3D "vsys_5v0"; - regulator-min-microvolt =3D <5000000>; - regulator-max-microvolt =3D <5000000>; - vin-supply =3D <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_mmc1: regulator-sd { - /* Output of TPS22918 */ - compatible =3D "regulator-fixed"; - regulator-name =3D "vdd_mmc1"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - regulator-boot-on; - enable-active-high; - vin-supply =3D <&vsys_3v3>; - gpio =3D <&exp2 2 GPIO_ACTIVE_HIGH>; - }; - - vdd_sd_dv: regulator-TLV71033 { - /* Output of TLV71033 */ - compatible =3D "regulator-gpio"; - regulator-name =3D "tlv71033"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&vdd_sd_dv_pins_default>; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <3300000>; - regulator-boot-on; - vin-supply =3D <&vsys_5v0>; - gpios =3D <&main_gpio0 8 GPIO_ACTIVE_HIGH>; - states =3D <1800000 0x0>, - <3300000 0x1>; - }; - - dp0_pwr_3v3: regulator-dp0-prw { - compatible =3D "regulator-fixed"; - regulator-name =3D "dp0-pwr"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - gpio =3D <&exp4 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - dp0: connector-dp0 { - compatible =3D "dp-connector"; - label =3D "DP0"; - type =3D "full-size"; - dp-pwr-supply =3D <&dp0_pwr_3v3>; - - port { - dp0_connector_in: endpoint { - remote-endpoint =3D <&dp0_out>; - }; - }; - }; - - transceiver0: can-phy0 { - compatible =3D "ti,tcan1042"; - #phy-cells =3D <0>; - max-bitrate =3D <5000000>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&mcu_mcan0_gpio_pins_default>; - standby-gpios =3D <&wkup_gpio0 69 GPIO_ACTIVE_HIGH>; - }; - - transceiver1: can-phy1 { - compatible =3D "ti,tcan1042"; - #phy-cells =3D <0>; - max-bitrate =3D <5000000>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&mcu_mcan1_gpio_pins_default>; - standby-gpios =3D <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; - }; - - transceiver2: can-phy2 { - /* standby pin has been grounded by default */ - compatible =3D "ti,tcan1042"; - #phy-cells =3D <0>; - max-bitrate =3D <5000000>; - }; - - transceiver3: can-phy3 { - compatible =3D "ti,tcan1042"; - #phy-cells =3D <0>; - max-bitrate =3D <5000000>; - standby-gpios =3D <&exp2 7 GPIO_ACTIVE_HIGH>; - mux-states =3D <&mux1 1>; - }; - - mux1: mux-controller { - compatible =3D "gpio-mux"; - #mux-state-cells =3D <1>; - mux-gpios =3D <&exp2 14 GPIO_ACTIVE_HIGH>; - idle-state =3D <1>; - }; - - codec_audio: sound { - compatible =3D "ti,j7200-cpb-audio"; - model =3D "j784s4-cpb"; - - ti,cpb-mcasp =3D <&mcasp0>; - ti,cpb-codec =3D <&pcm3168a_1>; - - clocks =3D <&k3_clks 265 0>, <&k3_clks 265 1>, - <&k3_clks 157 34>, <&k3_clks 157 63>; - clock-names =3D "cpb-mcasp-auxclk", "cpb-mcasp-auxclk-48000", - "cpb-codec-scki", "cpb-codec-scki-48000"; - }; -}; - -&wkup_gpio0 { - status =3D "okay"; -}; - -&main_pmx0 { - bootph-all; - main_cpsw2g_default_pins: main-cpsw2g-default-pins { - pinctrl-single,pins =3D < - J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */ - J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */ - J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */ - J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */ - J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */ - J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL = */ - J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */ - J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */ - J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */ - J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */ - J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */ - J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL = */ - >; - }; - - main_cpsw2g_mdio_default_pins: main-cpsw2g-mdio-default-pins { - pinctrl-single,pins =3D < - J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */ - J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */ - >; - }; - - main_uart8_pins_default: main-uart8-default-pins { - bootph-all; - pinctrl-single,pins =3D < - J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ - J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ - J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ - J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ - >; - }; - - main_i2c0_pins_default: main-i2c0-default-pins { - pinctrl-single,pins =3D < - J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ - J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ - >; - }; - - main_i2c5_pins_default: main-i2c5-default-pins { - pinctrl-single,pins =3D < - J784S4_IOPAD(0x01c, PIN_INPUT, 8) /* (AG34) MCAN15_TX.I2C5_SCL */ - J784S4_IOPAD(0x018, PIN_INPUT, 8) /* (AK36) MCAN14_RX.I2C5_SDA */ - >; - }; - - main_mmc1_pins_default: main-mmc1-default-pins { - bootph-all; - pinctrl-single,pins =3D < - J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ - J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ - J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */ - J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */ - J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */ - J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */ - J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */ - J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */ - >; - }; - - vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { - pinctrl-single,pins =3D < - J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ - >; - }; - - dp0_pins_default: dp0-default-pins { - pinctrl-single,pins =3D < - J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */ - >; - }; - - main_i2c4_pins_default: main-i2c4-default-pins { - pinctrl-single,pins =3D < - J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */ - J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */ - >; - }; - - main_mcan4_pins_default: main-mcan4-default-pins { - pinctrl-single,pins =3D < - J784S4_IOPAD(0x088, PIN_INPUT, 0) /* (AF36) MCAN4_RX */ - J784S4_IOPAD(0x084, PIN_OUTPUT, 0) /* (AG38) MCAN4_TX */ - >; - }; - - main_mcan16_pins_default: main-mcan16-default-pins { - pinctrl-single,pins =3D < - J784S4_IOPAD(0x028, PIN_INPUT, 0) /* (AE33) MCAN16_RX */ - J784S4_IOPAD(0x024, PIN_OUTPUT, 0) /* (AH34) MCAN16_TX */ - >; - }; - - main_usbss0_pins_default: main-usbss0-default-pins { - bootph-all; - pinctrl-single,pins =3D < - J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */ - >; - }; - - main_i2c3_pins_default: main-i2c3-default-pins { - pinctrl-single,pins =3D < - J784S4_IOPAD(0x064, PIN_INPUT, 13) /* (AF38) MCAN0_TX.I2C3_SCL */ - J784S4_IOPAD(0x060, PIN_INPUT, 13) /* (AE36) MCASP2_AXR1.I2C3_SDA */ - >; - }; - - main_mcasp0_pins_default: main-mcasp0-default-pins { - pinctrl-single,pins =3D < - J784S4_IOPAD(0x038, PIN_OUTPUT_PULLDOWN, 1) /* (AK35) MCASP0_ACLKX */ - J784S4_IOPAD(0x03c, PIN_OUTPUT_PULLDOWN, 1) /* (AK38) MCASP0_AFSX */ - J784S4_IOPAD(0x07c, PIN_OUTPUT_PULLDOWN, 1) /* (AJ38) MCASP0_AXR3 */ - J784S4_IOPAD(0x080, PIN_INPUT_PULLDOWN, 1) /* (AK34) MCASP0_AXR4 */ - >; - }; - - audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins { - pinctrl-single,pins =3D < - J784S4_IOPAD(0x078, PIN_OUTPUT, 1) /* (AH37) MCAN2_RX.AUDIO_EXT_REFCLK1= */ - >; - }; -}; - -&wkup_pmx2 { - bootph-all; - wkup_uart0_pins_default: wkup-uart0-default-pins { - bootph-all; - pinctrl-single,pins =3D < - J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ - J784S4_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (K34) WKUP_UART0_TXD */ - >; - }; - - wkup_i2c0_pins_default: wkup-i2c0-default-pins { - bootph-all; - pinctrl-single,pins =3D < - J784S4_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ - J784S4_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ - >; - }; - - mcu_uart0_pins_default: mcu-uart0-default-pins { - bootph-all; - pinctrl-single,pins =3D < - J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0= _CTSn */ - J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART= 0_RTSn */ - J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0= _RXD */ - J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART= 0_TXD */ - >; - }; - - mcu_cpsw_pins_default: mcu-cpsw-default-pins { - pinctrl-single,pins =3D < - J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ - J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ - J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ - J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ - J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ - J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ - J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ - J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ - J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ - J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ - J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ - J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ - >; - }; - - mcu_mdio_pins_default: mcu-mdio-default-pins { - pinctrl-single,pins =3D < - J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ - J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ - >; - }; - - mcu_adc0_pins_default: mcu-adc0-default-pins { - pinctrl-single,pins =3D < - J784S4_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ - J784S4_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ - J784S4_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */ - J784S4_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */ - J784S4_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */ - J784S4_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */ - J784S4_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */ - J784S4_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */ - >; - }; - - mcu_adc1_pins_default: mcu-adc1-default-pins { - pinctrl-single,pins =3D < - J784S4_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ - J784S4_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ - J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */ - J784S4_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */ - J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */ - J784S4_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */ - J784S4_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */ - J784S4_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ - >; - }; - - mcu_mcan0_pins_default: mcu-mcan0-default-pins { - pinctrl-single,pins =3D < - J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */ - J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */ - >; - }; - - mcu_mcan1_pins_default: mcu-mcan1-default-pins { - pinctrl-single,pins =3D < - J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (H35) WKUP_GPIO0_4.MCU_MCAN1= _TX */ - J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_= RX */ - >; - }; - - mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { - pinctrl-single,pins =3D < - J784S4_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (J38) MCU_SPI0_D1.WKUP_GPIO0_= 69 */ - >; - }; - - mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { - pinctrl-single,pins =3D < - J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */ - >; - }; -}; - -&wkup_pmx1 { - status =3D "okay"; - - pmic_irq_pins_default: pmic-irq-default-pins { - pinctrl-single,pins =3D < - /* (G33) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */ - J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7) - >; - }; -}; - -&wkup_pmx0 { - bootph-all; - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { - bootph-all; - pinctrl-single,pins =3D < - J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ - J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ - J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ - J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ - J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ - J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ - J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ - J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ - J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ - J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ - J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ - >; - }; -}; - -&wkup_pmx1 { - bootph-all; - mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins { - bootph-all; - pinctrl-single,pins =3D < - J784S4_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_ECC_FAIL */ - J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */ - >; - }; - - mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { - bootph-all; - pinctrl-single,pins =3D < - J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ - J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ - J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ - J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ - J784S4_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ - J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ - J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ - J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ - >; - }; -}; - -&wkup_uart0 { - /* Firmware usage */ - status =3D "reserved"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&wkup_uart0_pins_default>; -}; - -&wkup_i2c0 { - bootph-all; - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&wkup_i2c0_pins_default>; - clock-frequency =3D <400000>; - - eeprom@50 { - /* CAV24C256WE-GT3 */ - compatible =3D "atmel,24c256"; - reg =3D <0x50>; - }; - - tps659413: pmic@48 { - compatible =3D "ti,tps6594-q1"; - reg =3D <0x48>; - system-power-controller; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pmic_irq_pins_default>; - interrupt-parent =3D <&wkup_gpio0>; - interrupts =3D <39 IRQ_TYPE_EDGE_FALLING>; - gpio-controller; - #gpio-cells =3D <2>; - ti,primary-pmic; - buck12-supply =3D <&vsys_3v3>; - buck3-supply =3D <&vsys_3v3>; - buck4-supply =3D <&vsys_3v3>; - buck5-supply =3D <&vsys_3v3>; - ldo1-supply =3D <&vsys_3v3>; - ldo2-supply =3D <&vsys_3v3>; - ldo3-supply =3D <&vsys_3v3>; - ldo4-supply =3D <&vsys_3v3>; - - regulators { - bucka12: buck12 { - regulator-name =3D "vdd_ddr_1v1"; - regulator-min-microvolt =3D <1100000>; - regulator-max-microvolt =3D <1100000>; - regulator-boot-on; - regulator-always-on; - }; - - bucka3: buck3 { - regulator-name =3D "vdd_ram_0v85"; - regulator-min-microvolt =3D <850000>; - regulator-max-microvolt =3D <850000>; - regulator-boot-on; - regulator-always-on; - }; - - bucka4: buck4 { - regulator-name =3D "vdd_io_1v8"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - bucka5: buck5 { - regulator-name =3D "vdd_mcu_0v85"; - regulator-min-microvolt =3D <850000>; - regulator-max-microvolt =3D <850000>; - regulator-boot-on; - regulator-always-on; - }; - - ldoa1: ldo1 { - regulator-name =3D "vdd_mcuio_1v8"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldoa2: ldo2 { - regulator-name =3D "vdd_mcuio_3v3"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldoa3: ldo3 { - regulator-name =3D "vds_dll_0v8"; - regulator-min-microvolt =3D <800000>; - regulator-max-microvolt =3D <800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldoa4: ldo4 { - regulator-name =3D "vda_mcu_1v8"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - tps62873a: regulator@40 { - compatible =3D "ti,tps62873"; - reg =3D <0x40>; - bootph-pre-ram; - regulator-name =3D "VDD_CPU_AVS"; - regulator-min-microvolt =3D <750000>; - regulator-max-microvolt =3D <1330000>; - regulator-boot-on; - regulator-always-on; - }; - - tps62873b: regulator@43 { - compatible =3D "ti,tps62873"; - reg =3D <0x43>; - regulator-name =3D "VDD_CORE_0V8"; - regulator-min-microvolt =3D <760000>; - regulator-max-microvolt =3D <840000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&mcu_uart0 { - bootph-all; - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&mcu_uart0_pins_default>; -}; - -&main_uart8 { - bootph-all; - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&main_uart8_pins_default>; -}; - -&ufs_wrapper { - status =3D "okay"; -}; - -&fss { - bootph-all; - status =3D "okay"; -}; - -&ospi0 { - bootph-all; - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_def= ault>; - - flash@0 { - bootph-all; - compatible =3D "jedec,spi-nor"; - reg =3D <0x0>; - spi-tx-bus-width =3D <8>; - spi-rx-bus-width =3D <8>; - spi-max-frequency =3D <25000000>; - cdns,tshsl-ns =3D <60>; - cdns,tsd2d-ns =3D <60>; - cdns,tchsh-ns =3D <60>; - cdns,tslch-ns =3D <60>; - cdns,read-delay =3D <4>; - - partitions { - compatible =3D "fixed-partitions"; - #address-cells =3D <1>; - #size-cells =3D <1>; - - partition@0 { - label =3D "ospi.tiboot3"; - reg =3D <0x0 0x80000>; - }; - - partition@80000 { - label =3D "ospi.tispl"; - reg =3D <0x80000 0x200000>; - }; - - partition@280000 { - label =3D "ospi.u-boot"; - reg =3D <0x280000 0x400000>; - }; - - partition@680000 { - label =3D "ospi.env"; - reg =3D <0x680000 0x40000>; - }; - - partition@6c0000 { - label =3D "ospi.env.backup"; - reg =3D <0x6c0000 0x40000>; - }; - - partition@800000 { - label =3D "ospi.rootfs"; - reg =3D <0x800000 0x37c0000>; - }; - - partition@3fc0000 { - bootph-all; - label =3D "ospi.phypattern"; - reg =3D <0x3fc0000 0x40000>; - }; - }; - }; -}; - -&ospi1 { - bootph-all; - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&mcu_fss0_ospi1_pins_default>; - - flash@0 { - bootph-all; - compatible =3D "jedec,spi-nor"; - reg =3D <0x0>; - spi-tx-bus-width =3D <1>; - spi-rx-bus-width =3D <4>; - spi-max-frequency =3D <40000000>; - cdns,tshsl-ns =3D <60>; - cdns,tsd2d-ns =3D <60>; - cdns,tchsh-ns =3D <60>; - cdns,tslch-ns =3D <60>; - cdns,read-delay =3D <2>; - - partitions { - compatible =3D "fixed-partitions"; - #address-cells =3D <1>; - #size-cells =3D <1>; - - partition@0 { - label =3D "qspi.tiboot3"; - reg =3D <0x0 0x80000>; - }; - - partition@80000 { - label =3D "qspi.tispl"; - reg =3D <0x80000 0x200000>; - }; - - partition@280000 { - label =3D "qspi.u-boot"; - reg =3D <0x280000 0x400000>; - }; - - partition@680000 { - label =3D "qspi.env"; - reg =3D <0x680000 0x40000>; - }; - - partition@6c0000 { - label =3D "qspi.env.backup"; - reg =3D <0x6c0000 0x40000>; - }; - - partition@800000 { - label =3D "qspi.rootfs"; - reg =3D <0x800000 0x37c0000>; - }; - - partition@3fc0000 { - bootph-all; - label =3D "qspi.phypattern"; - reg =3D <0x3fc0000 0x40000>; - }; - }; - - }; -}; - -&main_i2c0 { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&main_i2c0_pins_default>; - - clock-frequency =3D <400000>; - - exp1: gpio@20 { - compatible =3D "ti,tca6416"; - reg =3D <0x20>; - gpio-controller; - #gpio-cells =3D <2>; - gpio-line-names =3D "PCIE1_2L_MODE_SEL", "PCIE1_4L_PERSTZ", "PCIE1_2L_RC= _RSTZ", - "PCIE1_2L_EP_RST_EN", "PCIE0_4L_MODE_SEL", "PCIE0_4L_PERSTZ", - "PCIE0_4L_RC_RSTZ", "PCIE0_4L_EP_RST_EN", "PCIE1_4L_PRSNT#", - "PCIE0_4L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", - "AUDIO_MUX_SEL", "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTZ"; - - p12-hog { - /* P12 - AUDIO_MUX_SEL */ - gpio-hog; - gpios =3D <12 GPIO_ACTIVE_HIGH>; - output-low; - line-name =3D "AUDIO_MUX_SEL"; - }; - }; - - exp2: gpio@22 { - compatible =3D "ti,tca6424"; - reg =3D <0x22>; - gpio-controller; - #gpio-cells =3D <2>; - gpio-line-names =3D "R_GPIO_RGMII1_RST", "ENET2_I2CMUX_SEL", "GPIO_USD_P= WR_EN", - "USBC_PWR_EN", "USBC_MODE_SEL1", "USBC_MODE_SEL0", - "GPIO_LIN_EN", "R_CAN_STB", "CTRL_PM_I2C_OE#", - "ENET2_EXP_PWRDN", "ENET2_EXP_SPARE2", "CDCI2_RSTZ", - "USB2.0_MUX_SEL", "CANUART_MUX_SEL0", "CANUART_MUX2_SEL1", - "CANUART_MUX1_SEL1", "ENET1_EXP_PWRDN", "ENET1_EXP_RESETZ", - "ENET1_I2CMUX_SEL", "ENET1_EXP_SPARE2", "ENET2_EXP_RESETZ", - "USER_INPUT1", "USER_LED1", "USER_LED2"; - - p13-hog { - /* P13 - CANUART_MUX_SEL0 */ - gpio-hog; - gpios =3D <13 GPIO_ACTIVE_HIGH>; - output-high; - line-name =3D "CANUART_MUX_SEL0"; - }; - - p15-hog { - /* P15 - CANUART_MUX1_SEL1 */ - gpio-hog; - gpios =3D <15 GPIO_ACTIVE_HIGH>; - output-high; - line-name =3D "CANUART_MUX1_SEL1"; - }; - }; -}; - -&main_i2c5 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&main_i2c5_pins_default>; - clock-frequency =3D <400000>; - status =3D "okay"; - - exp5: gpio@20 { - compatible =3D "ti,tca6408"; - reg =3D <0x20>; - gpio-controller; - #gpio-cells =3D <2>; - gpio-line-names =3D "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", - "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO3", - "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", - "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; - }; -}; - -&main_sdhci0 { - bootph-all; - /* eMMC */ - status =3D "okay"; - non-removable; - ti,driver-strength-ohm =3D <50>; - disable-wp; -}; - -&main_sdhci1 { - bootph-all; - /* SD card */ - status =3D "okay"; - pinctrl-0 =3D <&main_mmc1_pins_default>; - pinctrl-names =3D "default"; - disable-wp; - vmmc-supply =3D <&vdd_mmc1>; - vqmmc-supply =3D <&vdd_sd_dv>; -}; - -&main_gpio0 { - status =3D "okay"; -}; - -&mcu_cpsw { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&mcu_cpsw_pins_default>; -}; - -&davinci_mdio { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&mcu_mdio_pins_default>; - - mcu_phy0: ethernet-phy@0 { - reg =3D <0>; - ti,rx-internal-delay =3D ; - ti,fifo-depth =3D ; - ti,min-output-impedance; - }; -}; - -&mcu_cpsw_port1 { - status =3D "okay"; - phy-mode =3D "rgmii-rxid"; - phy-handle =3D <&mcu_phy0>; -}; - -&main_cpsw1 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&main_cpsw2g_default_pins>; - status =3D "okay"; -}; - -&main_cpsw1_mdio { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&main_cpsw2g_mdio_default_pins>; - status =3D "okay"; - - main_cpsw1_phy0: ethernet-phy@0 { - reg =3D <0>; - ti,rx-internal-delay =3D ; - ti,fifo-depth =3D ; - ti,min-output-impedance; - }; -}; - -&main_cpsw1_port1 { - phy-mode =3D "rgmii-rxid"; - phy-handle =3D <&main_cpsw1_phy0>; - status =3D "okay"; -}; - -&mailbox0_cluster0 { - status =3D "okay"; - interrupts =3D <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status =3D "okay"; - interrupts =3D <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status =3D "okay"; - interrupts =3D <428>; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - status =3D "okay"; - interrupts =3D <424>; - - mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status =3D "okay"; - interrupts =3D <420>; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_c71_1: mbox-c71-1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; }; =20 &mailbox0_cluster5 { - status =3D "okay"; - interrupts =3D <416>; - - mbox_c71_2: mbox-c71-2 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - mbox_c71_3: mbox-c71-3 { ti,mbox-rx =3D <2 0 0>; ti,mbox-tx =3D <3 0 0>; }; }; =20 -&mcu_r5fss0_core0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0_core0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region =3D <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region =3D <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region =3D <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region =3D <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&main_r5fss2_core0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; - memory-region =3D <&main_r5fss2_core0_dma_memory_region>, - <&main_r5fss2_core0_memory_region>; -}; - -&main_r5fss2_core1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; - memory-region =3D <&main_r5fss2_core1_dma_memory_region>, - <&main_r5fss2_core1_memory_region>; -}; - -&c71_0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster4 &mbox_c71_0>; - memory-region =3D <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; - -&c71_1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster4 &mbox_c71_1>; - memory-region =3D <&c71_1_dma_memory_region>, - <&c71_1_memory_region>; -}; - -&c71_2 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster5 &mbox_c71_2>; - memory-region =3D <&c71_2_dma_memory_region>, - <&c71_2_memory_region>; -}; - &c71_3 { - status =3D "okay"; mboxes =3D <&mailbox0_cluster5 &mbox_c71_3>; memory-region =3D <&c71_3_dma_memory_region>, <&c71_3_memory_region>; -}; - -&tscadc0 { - pinctrl-0 =3D <&mcu_adc0_pins_default>; - pinctrl-names =3D "default"; - status =3D "okay"; - adc { - ti,adc-channels =3D <0 1 2 3 4 5 6 7>; - }; -}; - -&tscadc1 { - pinctrl-0 =3D <&mcu_adc1_pins_default>; - pinctrl-names =3D "default"; - status =3D "okay"; - adc { - ti,adc-channels =3D <0 1 2 3 4 5 6 7>; - }; -}; - -&serdes_refclk { - status =3D "okay"; - clock-frequency =3D <100000000>; -}; - -&dss { - status =3D "okay"; - assigned-clocks =3D <&k3_clks 218 2>, - <&k3_clks 218 5>, - <&k3_clks 218 14>, - <&k3_clks 218 18>; - assigned-clock-parents =3D <&k3_clks 218 3>, - <&k3_clks 218 7>, - <&k3_clks 218 16>, - <&k3_clks 218 22>; -}; - -&serdes0 { - status =3D "okay"; - - serdes0_pcie1_link: phy@0 { - reg =3D <0>; - cdns,num-lanes =3D <2>; - #phy-cells =3D <0>; - cdns,phy-type =3D ; - resets =3D <&serdes_wiz0 1>, <&serdes_wiz0 2>; - }; - - serdes0_usb_link: phy@3 { - reg =3D <3>; - cdns,num-lanes =3D <1>; - #phy-cells =3D <0>; - cdns,phy-type =3D ; - resets =3D <&serdes_wiz0 4>; - }; -}; - -&serdes_wiz0 { - status =3D "okay"; -}; - -&usb_serdes_mux { - idle-states =3D <0>; /* USB0 to SERDES lane 3 */ -}; - -&usbss0 { - status =3D "okay"; - pinctrl-0 =3D <&main_usbss0_pins_default>; - pinctrl-names =3D "default"; - ti,vbus-divider; -}; - -&usb0 { - dr_mode =3D "otg"; - maximum-speed =3D "super-speed"; - phys =3D <&serdes0_usb_link>; - phy-names =3D "cdns3,usb3-phy"; -}; - -&serdes_wiz4 { - status =3D "okay"; -}; - -&serdes4 { - status =3D "okay"; - serdes4_dp_link: phy@0 { - reg =3D <0>; - cdns,num-lanes =3D <4>; - #phy-cells =3D <0>; - cdns,phy-type =3D ; - resets =3D <&serdes_wiz4 1>, <&serdes_wiz4 2>, - <&serdes_wiz4 3>, <&serdes_wiz4 4>; - }; -}; - -&mhdp { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&dp0_pins_default>; - phys =3D <&serdes4_dp_link>; - phy-names =3D "dpphy"; -}; - -&dss_ports { - /* DP */ - port { - dpi0_out: endpoint { - remote-endpoint =3D <&dp0_in>; - }; - }; -}; - -&main_i2c4 { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&main_i2c4_pins_default>; - clock-frequency =3D <400000>; - - exp4: gpio@20 { - compatible =3D "ti,tca6408"; - reg =3D <0x20>; - gpio-controller; - #gpio-cells =3D <2>; - }; -}; - -&dp0_ports { - port@0 { - reg =3D <0>; - - dp0_in: endpoint { - remote-endpoint =3D <&dpi0_out>; - }; - }; - - port@4 { - reg =3D <4>; - - dp0_out: endpoint { - remote-endpoint =3D <&dp0_connector_in>; - }; - }; -}; - -&mcu_mcan0 { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&mcu_mcan0_pins_default>; - phys =3D <&transceiver0>; -}; - -&mcu_mcan1 { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&mcu_mcan1_pins_default>; - phys =3D <&transceiver1>; -}; - -&main_mcan16 { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&main_mcan16_pins_default>; - phys =3D <&transceiver2>; -}; - -&main_mcan4 { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&main_mcan4_pins_default>; - phys =3D <&transceiver3>; -}; - -&pcie1_rc { - status =3D "okay"; - num-lanes =3D <2>; - reset-gpios =3D <&exp1 2 GPIO_ACTIVE_HIGH>; - phys =3D <&serdes0_pcie1_link>; - phy-names =3D "pcie-phy"; -}; - -&serdes1 { - status =3D "okay"; - - serdes1_pcie0_link: phy@0 { - reg =3D <0>; - cdns,num-lanes =3D <4>; - #phy-cells =3D <0>; - cdns,phy-type =3D ; - resets =3D <&serdes_wiz1 1>, <&serdes_wiz1 2>, - <&serdes_wiz1 3>, <&serdes_wiz1 4>; - }; -}; - -&serdes_wiz1 { - status =3D "okay"; -}; - -&pcie0_rc { - status =3D "okay"; - reset-gpios =3D <&exp1 6 GPIO_ACTIVE_HIGH>; - phys =3D <&serdes1_pcie0_link>; - phy-names =3D "pcie-phy"; -}; - -&k3_clks { - /* Confiure AUDIO_EXT_REFCLK1 pin as output */ - pinctrl-names =3D "default"; - pinctrl-0 =3D <&audio_ext_refclk1_pins_default>; -}; - -&main_i2c3 { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&main_i2c3_pins_default>; - clock-frequency =3D <400000>; - - exp3: gpio@20 { - compatible =3D "ti,tca6408"; - reg =3D <0x20>; - gpio-controller; - #gpio-cells =3D <2>; - }; - - pcm3168a_1: audio-codec@44 { - compatible =3D "ti,pcm3168a"; - reg =3D <0x44>; - #sound-dai-cells =3D <1>; - reset-gpios =3D <&exp3 0 GPIO_ACTIVE_LOW>; - clocks =3D <&audio_refclk1>; - clock-names =3D "scki"; - VDD1-supply =3D <&vsys_3v3>; - VDD2-supply =3D <&vsys_3v3>; - VCCAD1-supply =3D <&vsys_5v0>; - VCCAD2-supply =3D <&vsys_5v0>; - VCCDA1-supply =3D <&vsys_5v0>; - VCCDA2-supply =3D <&vsys_5v0>; - }; -}; - -&mcasp0 { status =3D "okay"; - #sound-dai-cells =3D <0>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&main_mcasp0_pins_default>; - op-mode =3D <0>; /* MCASP_IIS_MODE */ - tdm-slots =3D <2>; - auxclk-fs-ratio =3D <256>; - serial-dir =3D < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 0 1 - 2 0 0 0 - 0 0 0 0 - 0 0 0 0 - >; }; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch= /arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi new file mode 100644 index 000000000000..32d5db32e86b --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi @@ -0,0 +1,1437 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti= .com/ + * + * EVM Board Schematics(j784s4): https://www.ti.com/lit/zip/sprr458 + * EVM Board Schematics(j742s2): https://www.ti.com/lit/zip/SPAC001 + */ +/ { + chosen { + stdout-path =3D "serial2:115200n8"; + }; + + aliases { + serial0 =3D &wkup_uart0; + serial1 =3D &mcu_uart0; + serial2 =3D &main_uart8; + mmc0 =3D &main_sdhci0; + mmc1 =3D &main_sdhci1; + i2c0 =3D &wkup_i2c0; + i2c3 =3D &main_i2c0; + ethernet0 =3D &mcu_cpsw_port1; + ethernet1 =3D &main_cpsw1_port1; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + secure_ddr: optee@9e800000 { + reg =3D <0x00 0x9e800000 0x00 0x01800000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + main_r5fss2_core0_memory_region: r5f-memory@a6100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + main_r5fss2_core1_memory_region: r5f-memory@a7100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: c71-dma-memory@a8000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa8000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: c71-memory@a8100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa8100000 0x00 0xf00000>; + no-map; + }; + + c71_1_dma_memory_region: c71-dma-memory@a9000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa9000000 0x00 0x100000>; + no-map; + }; + + c71_1_memory_region: c71-memory@a9100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa9100000 0x00 0xf00000>; + no-map; + }; + + c71_2_dma_memory_region: c71-dma-memory@aa000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xaa000000 0x00 0x100000>; + no-map; + }; + + c71_2_memory_region: c71-memory@aa100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xaa100000 0x00 0xf00000>; + no-map; + }; + }; + + evm_12v0: regulator-evm12v0 { + /* main supply */ + compatible =3D "regulator-fixed"; + regulator-name =3D "evm_12v0"; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_3v3: regulator-vsys3v3 { + /* Output of LM5140 */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vsys_3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_5v0: regulator-vsys5v0 { + /* Output of LM5140 */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vsys_5v0"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-sd { + /* Output of TPS22918 */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_mmc1"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply =3D <&vsys_3v3>; + gpio =3D <&exp2 2 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv: regulator-TLV71033 { + /* Output of TLV71033 */ + compatible =3D "regulator-gpio"; + regulator-name =3D "tlv71033"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vdd_sd_dv_pins_default>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + vin-supply =3D <&vsys_5v0>; + gpios =3D <&main_gpio0 8 GPIO_ACTIVE_HIGH>; + states =3D <1800000 0x0>, + <3300000 0x1>; + }; + + dp0_pwr_3v3: regulator-dp0-prw { + compatible =3D "regulator-fixed"; + regulator-name =3D "dp0-pwr"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&exp4 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + dp0: connector-dp0 { + compatible =3D "dp-connector"; + label =3D "DP0"; + type =3D "full-size"; + dp-pwr-supply =3D <&dp0_pwr_3v3>; + + port { + dp0_connector_in: endpoint { + remote-endpoint =3D <&dp0_out>; + }; + }; + }; + + transceiver0: can-phy0 { + compatible =3D "ti,tcan1042"; + #phy-cells =3D <0>; + max-bitrate =3D <5000000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_mcan0_gpio_pins_default>; + standby-gpios =3D <&wkup_gpio0 69 GPIO_ACTIVE_HIGH>; + }; + + transceiver1: can-phy1 { + compatible =3D "ti,tcan1042"; + #phy-cells =3D <0>; + max-bitrate =3D <5000000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_mcan1_gpio_pins_default>; + standby-gpios =3D <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; + }; + + transceiver2: can-phy2 { + /* standby pin has been grounded by default */ + compatible =3D "ti,tcan1042"; + #phy-cells =3D <0>; + max-bitrate =3D <5000000>; + }; + + transceiver3: can-phy3 { + compatible =3D "ti,tcan1042"; + #phy-cells =3D <0>; + max-bitrate =3D <5000000>; + standby-gpios =3D <&exp2 7 GPIO_ACTIVE_HIGH>; + mux-states =3D <&mux1 1>; + }; + + mux1: mux-controller { + compatible =3D "gpio-mux"; + #mux-state-cells =3D <1>; + mux-gpios =3D <&exp2 14 GPIO_ACTIVE_HIGH>; + idle-state =3D <1>; + }; + + codec_audio: sound { + compatible =3D "ti,j7200-cpb-audio"; + model =3D "j784s4-cpb"; + + ti,cpb-mcasp =3D <&mcasp0>; + ti,cpb-codec =3D <&pcm3168a_1>; + + clocks =3D <&k3_clks 265 0>, <&k3_clks 265 1>, + <&k3_clks 157 34>, <&k3_clks 157 63>; + clock-names =3D "cpb-mcasp-auxclk", "cpb-mcasp-auxclk-48000", + "cpb-codec-scki", "cpb-codec-scki-48000"; + }; +}; + +&wkup_gpio0 { + status =3D "okay"; +}; + +&main_pmx0 { + bootph-all; + main_cpsw2g_default_pins: main-cpsw2g-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */ + J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */ + J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */ + J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */ + J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */ + J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL = */ + J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */ + J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */ + J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */ + J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */ + J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */ + J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL = */ + >; + }; + + main_cpsw2g_mdio_default_pins: main-cpsw2g-mdio-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */ + J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */ + >; + }; + + main_uart8_pins_default: main-uart8-default-pins { + bootph-all; + pinctrl-single,pins =3D < + J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ + J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ + J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ + J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ + >; + }; + + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ + J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ + >; + }; + + main_i2c5_pins_default: main-i2c5-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x01c, PIN_INPUT, 8) /* (AG34) MCAN15_TX.I2C5_SCL */ + J784S4_IOPAD(0x018, PIN_INPUT, 8) /* (AK36) MCAN14_RX.I2C5_SDA */ + >; + }; + + main_mmc1_pins_default: main-mmc1-default-pins { + bootph-all; + pinctrl-single,pins =3D < + J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ + J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ + J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */ + J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */ + J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */ + J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */ + J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */ + J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */ + >; + }; + + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ + >; + }; + + dp0_pins_default: dp0-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */ + >; + }; + + main_i2c4_pins_default: main-i2c4-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */ + J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */ + >; + }; + + main_mcan4_pins_default: main-mcan4-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x088, PIN_INPUT, 0) /* (AF36) MCAN4_RX */ + J784S4_IOPAD(0x084, PIN_OUTPUT, 0) /* (AG38) MCAN4_TX */ + >; + }; + + main_mcan16_pins_default: main-mcan16-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x028, PIN_INPUT, 0) /* (AE33) MCAN16_RX */ + J784S4_IOPAD(0x024, PIN_OUTPUT, 0) /* (AH34) MCAN16_TX */ + >; + }; + + main_usbss0_pins_default: main-usbss0-default-pins { + bootph-all; + pinctrl-single,pins =3D < + J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */ + >; + }; + + main_i2c3_pins_default: main-i2c3-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x064, PIN_INPUT, 13) /* (AF38) MCAN0_TX.I2C3_SCL */ + J784S4_IOPAD(0x060, PIN_INPUT, 13) /* (AE36) MCASP2_AXR1.I2C3_SDA */ + >; + }; + + main_mcasp0_pins_default: main-mcasp0-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x038, PIN_OUTPUT_PULLDOWN, 1) /* (AK35) MCASP0_ACLKX */ + J784S4_IOPAD(0x03c, PIN_OUTPUT_PULLDOWN, 1) /* (AK38) MCASP0_AFSX */ + J784S4_IOPAD(0x07c, PIN_OUTPUT_PULLDOWN, 1) /* (AJ38) MCASP0_AXR3 */ + J784S4_IOPAD(0x080, PIN_INPUT_PULLDOWN, 1) /* (AK34) MCASP0_AXR4 */ + >; + }; + + audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x078, PIN_OUTPUT, 1) /* (AH37) MCAN2_RX.AUDIO_EXT_REFCLK1= */ + >; + }; +}; + +&wkup_pmx2 { + bootph-all; + wkup_uart0_pins_default: wkup-uart0-default-pins { + bootph-all; + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ + J784S4_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (K34) WKUP_UART0_TXD */ + >; + }; + + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + bootph-all; + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ + J784S4_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-default-pins { + bootph-all; + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0= _CTSn */ + J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART= 0_RTSn */ + J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0= _RXD */ + J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART= 0_TXD */ + >; + }; + + mcu_cpsw_pins_default: mcu-cpsw-default-pins { + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ + J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ + J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ + J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ + J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ + J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ + J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio-default-pins { + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ + J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ + >; + }; + + mcu_adc0_pins_default: mcu-adc0-default-pins { + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ + J784S4_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ + J784S4_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */ + J784S4_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */ + J784S4_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */ + J784S4_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */ + J784S4_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */ + J784S4_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */ + >; + }; + + mcu_adc1_pins_default: mcu-adc1-default-pins { + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ + J784S4_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ + J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */ + J784S4_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */ + J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */ + J784S4_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */ + J784S4_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */ + J784S4_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ + >; + }; + + mcu_mcan0_pins_default: mcu-mcan0-default-pins { + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */ + J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-default-pins { + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (H35) WKUP_GPIO0_4.MCU_MCAN1= _TX */ + J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_= RX */ + >; + }; + + mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (J38) MCU_SPI0_D1.WKUP_GPIO0_= 69 */ + >; + }; + + mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */ + >; + }; +}; + +&wkup_pmx1 { + status =3D "okay"; + + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins =3D < + /* (G33) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7) + >; + }; +}; + +&wkup_pmx0 { + bootph-all; + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { + bootph-all; + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ + J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ + J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ + J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ + J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ + J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ + J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ + >; + }; +}; + +&wkup_pmx1 { + bootph-all; + mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins { + bootph-all; + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_ECC_FAIL */ + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */ + >; + }; + + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { + bootph-all; + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ + J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ + J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ + J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ + J784S4_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ + J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ + J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ + >; + }; +}; + +&wkup_uart0 { + /* Firmware usage */ + status =3D "reserved"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wkup_uart0_pins_default>; +}; + +&wkup_i2c0 { + bootph-all; + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wkup_i2c0_pins_default>; + clock-frequency =3D <400000>; + + eeprom@50 { + /* CAV24C256WE-GT3 */ + compatible =3D "atmel,24c256"; + reg =3D <0x50>; + }; + + tps659413: pmic@48 { + compatible =3D "ti,tps6594-q1"; + reg =3D <0x48>; + system-power-controller; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_irq_pins_default>; + interrupt-parent =3D <&wkup_gpio0>; + interrupts =3D <39 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells =3D <2>; + ti,primary-pmic; + buck12-supply =3D <&vsys_3v3>; + buck3-supply =3D <&vsys_3v3>; + buck4-supply =3D <&vsys_3v3>; + buck5-supply =3D <&vsys_3v3>; + ldo1-supply =3D <&vsys_3v3>; + ldo2-supply =3D <&vsys_3v3>; + ldo3-supply =3D <&vsys_3v3>; + ldo4-supply =3D <&vsys_3v3>; + + regulators { + bucka12: buck12 { + regulator-name =3D "vdd_ddr_1v1"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka3: buck3 { + regulator-name =3D "vdd_ram_0v85"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka4: buck4 { + regulator-name =3D "vdd_io_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka5: buck5 { + regulator-name =3D "vdd_mcu_0v85"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa1: ldo1 { + regulator-name =3D "vdd_mcuio_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa2: ldo2 { + regulator-name =3D "vdd_mcuio_3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa3: ldo3 { + regulator-name =3D "vds_dll_0v8"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa4: ldo4 { + regulator-name =3D "vda_mcu_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + tps62873a: regulator@40 { + compatible =3D "ti,tps62873"; + reg =3D <0x40>; + bootph-pre-ram; + regulator-name =3D "VDD_CPU_AVS"; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <1330000>; + regulator-boot-on; + regulator-always-on; + }; + + tps62873b: regulator@43 { + compatible =3D "ti,tps62873"; + reg =3D <0x43>; + regulator-name =3D "VDD_CORE_0V8"; + regulator-min-microvolt =3D <760000>; + regulator-max-microvolt =3D <840000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&mcu_uart0 { + bootph-all; + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_uart0_pins_default>; +}; + +&main_uart8 { + bootph-all; + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_uart8_pins_default>; +}; + +&ufs_wrapper { + status =3D "okay"; +}; + +&fss { + bootph-all; + status =3D "okay"; +}; + +&ospi0 { + bootph-all; + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_def= ault>; + + flash@0 { + bootph-all; + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + spi-tx-bus-width =3D <8>; + spi-rx-bus-width =3D <8>; + spi-max-frequency =3D <25000000>; + cdns,tshsl-ns =3D <60>; + cdns,tsd2d-ns =3D <60>; + cdns,tchsh-ns =3D <60>; + cdns,tslch-ns =3D <60>; + cdns,read-delay =3D <4>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "ospi.tiboot3"; + reg =3D <0x0 0x80000>; + }; + + partition@80000 { + label =3D "ospi.tispl"; + reg =3D <0x80000 0x200000>; + }; + + partition@280000 { + label =3D "ospi.u-boot"; + reg =3D <0x280000 0x400000>; + }; + + partition@680000 { + label =3D "ospi.env"; + reg =3D <0x680000 0x40000>; + }; + + partition@6c0000 { + label =3D "ospi.env.backup"; + reg =3D <0x6c0000 0x40000>; + }; + + partition@800000 { + label =3D "ospi.rootfs"; + reg =3D <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + bootph-all; + label =3D "ospi.phypattern"; + reg =3D <0x3fc0000 0x40000>; + }; + }; + }; +}; + +&ospi1 { + bootph-all; + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_fss0_ospi1_pins_default>; + + flash@0 { + bootph-all; + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + spi-tx-bus-width =3D <1>; + spi-rx-bus-width =3D <4>; + spi-max-frequency =3D <40000000>; + cdns,tshsl-ns =3D <60>; + cdns,tsd2d-ns =3D <60>; + cdns,tchsh-ns =3D <60>; + cdns,tslch-ns =3D <60>; + cdns,read-delay =3D <2>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "qspi.tiboot3"; + reg =3D <0x0 0x80000>; + }; + + partition@80000 { + label =3D "qspi.tispl"; + reg =3D <0x80000 0x200000>; + }; + + partition@280000 { + label =3D "qspi.u-boot"; + reg =3D <0x280000 0x400000>; + }; + + partition@680000 { + label =3D "qspi.env"; + reg =3D <0x680000 0x40000>; + }; + + partition@6c0000 { + label =3D "qspi.env.backup"; + reg =3D <0x6c0000 0x40000>; + }; + + partition@800000 { + label =3D "qspi.rootfs"; + reg =3D <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + bootph-all; + label =3D "qspi.phypattern"; + reg =3D <0x3fc0000 0x40000>; + }; + }; + + }; +}; + +&main_i2c0 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c0_pins_default>; + + clock-frequency =3D <400000>; + + exp1: gpio@20 { + compatible =3D "ti,tca6416"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "PCIE1_2L_MODE_SEL", "PCIE1_4L_PERSTZ", "PCIE1_2L_RC= _RSTZ", + "PCIE1_2L_EP_RST_EN", "PCIE0_4L_MODE_SEL", "PCIE0_4L_PERSTZ", + "PCIE0_4L_RC_RSTZ", "PCIE0_4L_EP_RST_EN", "PCIE1_4L_PRSNT#", + "PCIE0_4L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", + "AUDIO_MUX_SEL", "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTZ"; + + p12-hog { + /* P12 - AUDIO_MUX_SEL */ + gpio-hog; + gpios =3D <12 GPIO_ACTIVE_HIGH>; + output-low; + line-name =3D "AUDIO_MUX_SEL"; + }; + }; + + exp2: gpio@22 { + compatible =3D "ti,tca6424"; + reg =3D <0x22>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "R_GPIO_RGMII1_RST", "ENET2_I2CMUX_SEL", "GPIO_USD_P= WR_EN", + "USBC_PWR_EN", "USBC_MODE_SEL1", "USBC_MODE_SEL0", + "GPIO_LIN_EN", "R_CAN_STB", "CTRL_PM_I2C_OE#", + "ENET2_EXP_PWRDN", "ENET2_EXP_SPARE2", "CDCI2_RSTZ", + "USB2.0_MUX_SEL", "CANUART_MUX_SEL0", "CANUART_MUX2_SEL1", + "CANUART_MUX1_SEL1", "ENET1_EXP_PWRDN", "ENET1_EXP_RESETZ", + "ENET1_I2CMUX_SEL", "ENET1_EXP_SPARE2", "ENET2_EXP_RESETZ", + "USER_INPUT1", "USER_LED1", "USER_LED2"; + + p13-hog { + /* P13 - CANUART_MUX_SEL0 */ + gpio-hog; + gpios =3D <13 GPIO_ACTIVE_HIGH>; + output-high; + line-name =3D "CANUART_MUX_SEL0"; + }; + + p15-hog { + /* P15 - CANUART_MUX1_SEL1 */ + gpio-hog; + gpios =3D <15 GPIO_ACTIVE_HIGH>; + output-high; + line-name =3D "CANUART_MUX1_SEL1"; + }; + }; +}; + +&main_i2c5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c5_pins_default>; + clock-frequency =3D <400000>; + status =3D "okay"; + + exp5: gpio@20 { + compatible =3D "ti,tca6408"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", + "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO3", + "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", + "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; + }; +}; + +&main_sdhci0 { + bootph-all; + /* eMMC */ + status =3D "okay"; + non-removable; + ti,driver-strength-ohm =3D <50>; + disable-wp; +}; + +&main_sdhci1 { + bootph-all; + /* SD card */ + status =3D "okay"; + pinctrl-0 =3D <&main_mmc1_pins_default>; + pinctrl-names =3D "default"; + disable-wp; + vmmc-supply =3D <&vdd_mmc1>; + vqmmc-supply =3D <&vdd_sd_dv>; +}; + +&main_gpio0 { + status =3D "okay"; +}; + +&mcu_cpsw { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_cpsw_pins_default>; +}; + +&davinci_mdio { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_mdio_pins_default>; + + mcu_phy0: ethernet-phy@0 { + reg =3D <0>; + ti,rx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,min-output-impedance; + }; +}; + +&mcu_cpsw_port1 { + status =3D "okay"; + phy-mode =3D "rgmii-rxid"; + phy-handle =3D <&mcu_phy0>; +}; + +&main_cpsw1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_cpsw2g_default_pins>; + status =3D "okay"; +}; + +&main_cpsw1_mdio { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_cpsw2g_mdio_default_pins>; + status =3D "okay"; + + main_cpsw1_phy0: ethernet-phy@0 { + reg =3D <0>; + ti,rx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,min-output-impedance; + }; +}; + +&main_cpsw1_port1 { + phy-mode =3D "rgmii-rxid"; + phy-handle =3D <&main_cpsw1_phy0>; + status =3D "okay"; +}; + +&mailbox0_cluster0 { + status =3D "okay"; + interrupts =3D <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status =3D "okay"; + interrupts =3D <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + status =3D "okay"; + interrupts =3D <428>; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mailbox0_cluster3 { + status =3D "okay"; + interrupts =3D <424>; + + mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mailbox0_cluster4 { + status =3D "okay"; + interrupts =3D <420>; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_c71_1: mbox-c71-1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mailbox0_cluster5 { + status =3D "okay"; + interrupts =3D <416>; + + mbox_c71_2: mbox-c71-2 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mcu_r5fss0_core0 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&main_r5fss0_core0 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region =3D <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region =3D <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + memory-region =3D <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + memory-region =3D <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&main_r5fss2_core0 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; + memory-region =3D <&main_r5fss2_core0_dma_memory_region>, + <&main_r5fss2_core0_memory_region>; +}; + +&main_r5fss2_core1 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; + memory-region =3D <&main_r5fss2_core1_dma_memory_region>, + <&main_r5fss2_core1_memory_region>; +}; + +&c71_0 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster4 &mbox_c71_0>; + memory-region =3D <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; + +&c71_1 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster4 &mbox_c71_1>; + memory-region =3D <&c71_1_dma_memory_region>, + <&c71_1_memory_region>; +}; + +&c71_2 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster5 &mbox_c71_2>; + memory-region =3D <&c71_2_dma_memory_region>, + <&c71_2_memory_region>; +}; + +&tscadc0 { + pinctrl-0 =3D <&mcu_adc0_pins_default>; + pinctrl-names =3D "default"; + status =3D "okay"; + adc { + ti,adc-channels =3D <0 1 2 3 4 5 6 7>; + }; +}; + +&tscadc1 { + pinctrl-0 =3D <&mcu_adc1_pins_default>; + pinctrl-names =3D "default"; + status =3D "okay"; + adc { + ti,adc-channels =3D <0 1 2 3 4 5 6 7>; + }; +}; + +&serdes_refclk { + status =3D "okay"; + clock-frequency =3D <100000000>; +}; + +&dss { + status =3D "okay"; + assigned-clocks =3D <&k3_clks 218 2>, + <&k3_clks 218 5>, + <&k3_clks 218 14>, + <&k3_clks 218 18>; + assigned-clock-parents =3D <&k3_clks 218 3>, + <&k3_clks 218 7>, + <&k3_clks 218 16>, + <&k3_clks 218 22>; +}; + +&serdes0 { + status =3D "okay"; + + serdes0_pcie1_link: phy@0 { + reg =3D <0>; + cdns,num-lanes =3D <2>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz0 1>, <&serdes_wiz0 2>; + }; + + serdes0_usb_link: phy@3 { + reg =3D <3>; + cdns,num-lanes =3D <1>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz0 4>; + }; +}; + +&serdes_wiz0 { + status =3D "okay"; +}; + +&usb_serdes_mux { + idle-states =3D <0>; /* USB0 to SERDES lane 3 */ +}; + +&usbss0 { + status =3D "okay"; + pinctrl-0 =3D <&main_usbss0_pins_default>; + pinctrl-names =3D "default"; + ti,vbus-divider; +}; + +&usb0 { + dr_mode =3D "otg"; + maximum-speed =3D "super-speed"; + phys =3D <&serdes0_usb_link>; + phy-names =3D "cdns3,usb3-phy"; +}; + +&serdes_wiz4 { + status =3D "okay"; +}; + +&serdes4 { + status =3D "okay"; + serdes4_dp_link: phy@0 { + reg =3D <0>; + cdns,num-lanes =3D <4>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz4 1>, <&serdes_wiz4 2>, + <&serdes_wiz4 3>, <&serdes_wiz4 4>; + }; +}; + +&mhdp { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&dp0_pins_default>; + phys =3D <&serdes4_dp_link>; + phy-names =3D "dpphy"; +}; + +&dss_ports { + /* DP */ + port { + dpi0_out: endpoint { + remote-endpoint =3D <&dp0_in>; + }; + }; +}; + +&main_i2c4 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c4_pins_default>; + clock-frequency =3D <400000>; + + exp4: gpio@20 { + compatible =3D "ti,tca6408"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + }; +}; + +&dp0_ports { + port@0 { + reg =3D <0>; + + dp0_in: endpoint { + remote-endpoint =3D <&dpi0_out>; + }; + }; + + port@4 { + reg =3D <4>; + + dp0_out: endpoint { + remote-endpoint =3D <&dp0_connector_in>; + }; + }; +}; + +&mcu_mcan0 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_mcan0_pins_default>; + phys =3D <&transceiver0>; +}; + +&mcu_mcan1 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_mcan1_pins_default>; + phys =3D <&transceiver1>; +}; + +&main_mcan16 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_mcan16_pins_default>; + phys =3D <&transceiver2>; +}; + +&main_mcan4 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_mcan4_pins_default>; + phys =3D <&transceiver3>; +}; + +&pcie1_rc { + status =3D "okay"; + num-lanes =3D <2>; + reset-gpios =3D <&exp1 2 GPIO_ACTIVE_HIGH>; + phys =3D <&serdes0_pcie1_link>; + phy-names =3D "pcie-phy"; +}; + +&serdes1 { + status =3D "okay"; + + serdes1_pcie0_link: phy@0 { + reg =3D <0>; + cdns,num-lanes =3D <4>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz1 1>, <&serdes_wiz1 2>, + <&serdes_wiz1 3>, <&serdes_wiz1 4>; + }; +}; + +&serdes_wiz1 { + status =3D "okay"; +}; + +&pcie0_rc { + status =3D "okay"; + reset-gpios =3D <&exp1 6 GPIO_ACTIVE_HIGH>; + phys =3D <&serdes1_pcie0_link>; + phy-names =3D "pcie-phy"; +}; + +&k3_clks { + /* Confiure AUDIO_EXT_REFCLK1 pin as output */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&audio_ext_refclk1_pins_default>; +}; + +&main_i2c3 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c3_pins_default>; + clock-frequency =3D <400000>; + + exp3: gpio@20 { + compatible =3D "ti,tca6408"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + }; + + pcm3168a_1: audio-codec@44 { + compatible =3D "ti,pcm3168a"; + reg =3D <0x44>; + #sound-dai-cells =3D <1>; + reset-gpios =3D <&exp3 0 GPIO_ACTIVE_LOW>; + clocks =3D <&audio_refclk1>; + clock-names =3D "scki"; + VDD1-supply =3D <&vsys_3v3>; + VDD2-supply =3D <&vsys_3v3>; + VCCAD1-supply =3D <&vsys_5v0>; + VCCAD2-supply =3D <&vsys_5v0>; + VCCDA1-supply =3D <&vsys_5v0>; + VCCDA2-supply =3D <&vsys_5v0>; + }; +}; + +&mcasp0 { + status =3D "okay"; + #sound-dai-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_mcasp0_pins_default>; + op-mode =3D <0>; /* MCASP_IIS_MODE */ + tdm-slots =3D <2>; + auxclk-fs-ratio =3D <256>; + serial-dir =3D < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 0 1 + 2 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; +}; --=20 2.46.0