From nobody Fri Dec 19 13:50:57 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BAFD4C92 for ; Tue, 27 Aug 2024 05:09:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724735381; cv=none; b=TaL1iW2AbpVM1Nxi3OgkirHbF0PjyJQAwOBEQDHswt4ffJ0L2SWt1Mcr0NH/IZ6KVwfXxBICsvJQAeqTDxBifTjhKdOljpPqnrY3HGFy98Pji/VpVsd7qAzXUatO6W1E6btCVMyDjRJOEl77xFmk7BR9xmtI9EqAz2x66Ba+2dk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724735381; c=relaxed/simple; bh=CIvKikOPhEGLHf7EWowVUA0K+rreGMGnHAgAKNeRrJk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=OPlmq6bbSxlVK8ktKJKOTCJogK3ocAzN+z1iJEGLSuXHK3BY8GgfwhH9aYG81yX79MI99Pt8Fh72MGXjx7KmNGCaNquH/mj7FjtQ9KynmmxEC2S9kBgU7xeA8d58QjtgW+o30+xorBicPfo9mlKMgOJksQRmaGkx7w9vXWCs7pU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ftlakTUv; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ftlakTUv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724735380; x=1756271380; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=CIvKikOPhEGLHf7EWowVUA0K+rreGMGnHAgAKNeRrJk=; b=ftlakTUv6pCgL/5C/7tt5UiSB525t+Zc23bY8Ro1Z0xcGqAWrSfb3+ly 3s7097R/2A1X7DXvhuk0m+RS07kNlBMtV9y5pkROlXvDwK7g1NgQfJHha EW5y69AJM0Hv6VrOz1uXc2PcIZcrXvbLw/C+To9Y1hRRdZaGnZdgoNlLC rU7HzL4w7r684faxwH+a43A9iqV6K7yBrECZzJ9QGzgoosTuf3bfQa5qX 6T/tzgrbl38cYXSFC+DbKdl7fy6+nVwlHogOYv7o3uuN9ZHaQJM8Dp15x rZumqcV2GPP/TxgYI00zY1vuxSb0Xw921RRUJHbY/tVxlzrDi4vdiO9aS w==; X-CSE-ConnectionGUID: jWyjv9BAQiaPFpbmdlDf5g== X-CSE-MsgGUID: 5vCeqWLzTk+18wNsA/jL2w== X-IronPort-AV: E=McAfee;i="6700,10204,11176"; a="13230470" X-IronPort-AV: E=Sophos;i="6.10,179,1719903600"; d="scan'208";a="13230470" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2024 22:09:38 -0700 X-CSE-ConnectionGUID: kZ2OVvyJRUahBDIhj4T2/Q== X-CSE-MsgGUID: nuUhmEumSBK3LD55NUWluw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,179,1719903600"; d="scan'208";a="62703855" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orviesa009.jf.intel.com with ESMTP; 26 Aug 2024 22:09:37 -0700 From: Ricardo Neri To: x86@kernel.org Cc: Andreas Herrmann , Catalin Marinas , Chen Yu , Len Brown , Radu Rendec , Pierre Gondois , Pu Wen , "Rafael J. Wysocki" , Sudeep Holla , Srinivas Pandruvada , Will Deacon , Zhang Rui , Nikolay Borisov , Huang Ying , Ricardo Neri , linux-kernel@vger.kernel.org Subject: [PATCH v5 1/4] cacheinfo: Check for null last-level cache info Date: Mon, 26 Aug 2024 22:16:32 -0700 Message-Id: <20240827051635.9114-2-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240827051635.9114-1-ricardo.neri-calderon@linux.intel.com> References: <20240827051635.9114-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Before determining the validity of the last-level cache info, ensure that it has been allocated. Simply checking for non-zero cache_leaves() is not sufficient, as some architectures (e.g., Intel processors) have non-zero cache_leaves() before allocation. Dereferencing NULL cacheinfo can occur in update_per_cpu_data_slice_size(). This function iterates over all online CPUs. However, a CPU may have come online recently, but its cacheinfo may not have been allocated yet. Reviewed-by: Sudeep Holla Signed-off-by: Ricardo Neri Reviewed-by: Andreas Herrmann Tested-by: Andreas Herrmann --- Cc: Andreas Herrmann Cc: Catalin Marinas Cc: Chen Yu Cc: Huang Ying Cc: Len Brown Cc: Nikolay Borisov Cc: Radu Rendec Cc: Pierre Gondois Cc: Pu Wen Cc: "Rafael J. Wysocki" Cc: Sudeep Holla Cc: Srinivas Pandruvada Cc: Will Deacon Cc: Zhang Rui Cc: linux-arm-kernel@lists.infradead.org Cc: stable@vger.kernel.org # 6.3+ --- Changes since v4: * Combined checks for per_cpu_cacheinfo() and cache_leaves() in a single line. (Sudeep) * Added Reviewed-by tag from Sudeep. Thanks! Changes since v3: * Introduced this patch. Changes since v2: * N/A Changes since v1: * N/A --- The dereference of a NULL cacheinfo is not observed today because cache_leaves(cpu) is zero until after init_cache_level() is called (during the CPU hotplug callback). A subsequent changeset will set the number of cache leaves earlier and the NULL-pointer dereference will be observed. --- drivers/base/cacheinfo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index 23b8cba4a2a3..77f2e0f91589 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -58,7 +58,7 @@ bool last_level_cache_is_valid(unsigned int cpu) { struct cacheinfo *llc; =20 - if (!cache_leaves(cpu)) + if (!cache_leaves(cpu) || !per_cpu_cacheinfo(cpu)) return false; =20 llc =3D per_cpu_cacheinfo_idx(cpu, cache_leaves(cpu) - 1); --=20 2.34.1 From nobody Fri Dec 19 13:50:57 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6AB7A374CB for ; Tue, 27 Aug 2024 05:09:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724735382; cv=none; b=sxPmGcy3x7wUviW0kQnMkK8Uwu0UVQe4bC/+CCV7ixPsGno2tBH3OBo7I+ygp7ByIs/owxe/01d3vZ/CMewFLYIhrvbbyME/BaTctTn3B83xgXNPJonrJZxk2B4O9Bo+VehR7CfUCg15sluJnGdy49uuTHV3L93ghNIj6Dl5NKg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724735382; c=relaxed/simple; bh=77vrI8QF6pQcPHd+P8e88yX25IUCKQzDSU9AalQ85S4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=c9FUP9HYOkiDP4Bf0g9C9PmcSepNLNreQ9EpDlHrCc6zghxshyagVb6ViEN2cv9p/MAV14Y8onmrSysyl2gF/yTBou28jt8ju11E8PKNkQUghESmKdPF10d4MgvT1dC8lDP3ZJtwXFv8jJllHDki22BvQ3enHacPMfY9wCQwEIw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=IllUf02X; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="IllUf02X" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724735381; x=1756271381; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=77vrI8QF6pQcPHd+P8e88yX25IUCKQzDSU9AalQ85S4=; b=IllUf02XGrZK8vWh+gfYwlziGn11S2f8imO+DU8q4gDNI5O8ib+mcLwh 8MNwZ1kEclB2q7+lMn3WtLjNdnj8pmk0XxMWCocwwQxeTTaqYnR5cNv19 +M96IurJKVVAwpAC/tMD7jLhMN2ufM8QFc8kJzrOn1XUBZmtuPW0pTYoK pD3ckrZ8VZizXE4gU6jbv5iKfVfVwktTkrMSy9UZXFXrIVexMGZvdm3XJ TmRtp4yMxLlxKtfWEANitJNq0R7ewfq0UQaOguPo1ZDhB2ozixz5/x1CO 0Ilh1DGcnN4SQ4fO1K4RYvoQUvZSDgTpyyA+2jrEwvxk2VUC9+OkwvtdP g==; X-CSE-ConnectionGUID: ZSqB5L9rRmW5mCWAnr3Lvg== X-CSE-MsgGUID: eFXvJG46R12qeigclDjYLA== X-IronPort-AV: E=McAfee;i="6700,10204,11176"; a="13230476" X-IronPort-AV: E=Sophos;i="6.10,179,1719903600"; d="scan'208";a="13230476" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2024 22:09:38 -0700 X-CSE-ConnectionGUID: Xns2i46TTq2or46uFithiw== X-CSE-MsgGUID: rBqynKrUT6uu9nrS+VFhhQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,179,1719903600"; d="scan'208";a="62703859" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orviesa009.jf.intel.com with ESMTP; 26 Aug 2024 22:09:38 -0700 From: Ricardo Neri To: x86@kernel.org Cc: Andreas Herrmann , Catalin Marinas , Chen Yu , Len Brown , Radu Rendec , Pierre Gondois , Pu Wen , "Rafael J. Wysocki" , Sudeep Holla , Srinivas Pandruvada , Will Deacon , Zhang Rui , Nikolay Borisov , Huang Ying , Ricardo Neri , linux-kernel@vger.kernel.org Subject: [PATCH v5 2/4] cacheinfo: Allocate memory for memory if not done from the primary CPU Date: Mon, 26 Aug 2024 22:16:33 -0700 Message-Id: <20240827051635.9114-3-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240827051635.9114-1-ricardo.neri-calderon@linux.intel.com> References: <20240827051635.9114-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Commit 5944ce092b97 ("arch_topology: Build cacheinfo from primary CPU") adds functionality that architectures can use to optionally allocate and build cacheinfo early during boot. Commit 6539cffa9495 ("cacheinfo: Add arch specific early level initializer") lets secondary CPUs correct (and reallocate memory) cacheinfo data if needed. If the early build functionality is not used and cacheinfo does not need correction, memory for cacheinfo is never allocated. x86 does not use the early build functionality. Consequently, during the cacheinfo CPU hotplug callback, last_level_cache_is_valid() attempts to dereference a NULL pointer: BUG: kernel NULL pointer dereference, address: 0000000000000100 #PF: supervisor read access in kernel mode #PF: error_code(0x0000) - not present page PGD 0 P4D 0 Oops: 0000 [#1] PREEPMT SMP NOPTI CPU: 0 PID 19 Comm: cpuhp/0 Not tainted 6.4.0-rc2 #1 RIP: 0010: last_level_cache_is_valid+0x95/0xe0a Allocate memory for cacheinfo during the cacheinfo CPU hotplug callback if not done earlier. Reviewed-by: Radu Rendec Reviewed-by: Sudeep Holla Fixes: 6539cffa9495 ("cacheinfo: Add arch specific early level initializer") Signed-off-by: Ricardo Neri Reviewed-by: Andreas Herrmann Reviewed-by: Nikolay Borisov Tested-by: Andreas Herrmann --- Cc: Andreas Herrmann Cc: Catalin Marinas Cc: Chen Yu Cc: Huang Ying Cc: Len Brown Cc: Nikolay Borisov Cc: Radu Rendec Cc: Pierre Gondois Cc: Pu Wen Cc: "Rafael J. Wysocki" Cc: Sudeep Holla Cc: Srinivas Pandruvada Cc: Will Deacon Cc: Zhang Rui Cc: linux-arm-kernel@lists.infradead.org Cc: stable@vger.kernel.org # 6.3+ --- The motivation for commit 5944ce092b97 was to prevent a BUG splat in PREEMPT_RT kernels during memory allocation. This splat is not observed on x86 because the memory allocation for cacheinfo happens in detect_cache_attributes() from the cacheinfo CPU hotplug callback. The dereference of a NULL pointer is not observed today because cache_leaves(cpu) is zero until after init_cache_level() is called (also during the CPU hotplug callback). A subsequent changeset will set the number of cache leaves earlier and the NULL-pointer dereference will be observed. --- Changes since v4: * None Changes since v3: * Added Reviewed-by tag from Radu and Sudeep. Thanks! Changes since v2: * Introduced this patch. Changes since v1: * N/A --- drivers/base/cacheinfo.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index 77f2e0f91589..0332148691f9 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -554,7 +554,11 @@ static inline int init_level_allocate_ci(unsigned int = cpu) */ ci_cacheinfo(cpu)->early_ci_levels =3D false; =20 - if (cache_leaves(cpu) <=3D early_leaves) + /* + * Some architectures (e.g., x86) do not use early initialization. + * Allocate memory now in such case. + */ + if (cache_leaves(cpu) <=3D early_leaves && per_cpu_cacheinfo(cpu)) return 0; =20 kfree(per_cpu_cacheinfo(cpu)); --=20 2.34.1 From nobody Fri Dec 19 13:50:57 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDF7856458 for ; Tue, 27 Aug 2024 05:09:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724735382; cv=none; b=NW11o1xlxsmJPVV+vT4220YeYNwPitbOpprJqwROmVL+IRoBZGOPSTMI/iS6SP+Xl2bl36h2cjzDK/QTQxM7E6zVxkzRmcWG8X40Z707RdsI8zqLll0FWGTGPXKqlXz7/p1CKvJl2IG7D1dPrm1aP2NUuavhovyT5mm/eo6/7VA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724735382; c=relaxed/simple; bh=8m7BRzUErIAfRzt2aUpEvMJTMH5Swkur4vUpuj50EOw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=p/5rz4R7rMhuGhT7u2+DuMmg3E/gPby/wHqVL1owosLIZcmtLrW7oHnb3a/JQRkJaPMh5ovv6o//tX+7fyf2ihuePYs3qYdnuBMihxaqVFfwsLsYGLOWtq+zO/cK+I58Ol+cuY7YwuAoKPojTO8klu9ftrmBe7FhFtwhkh49pEU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Ce8jNOq+; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Ce8jNOq+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724735381; x=1756271381; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=8m7BRzUErIAfRzt2aUpEvMJTMH5Swkur4vUpuj50EOw=; b=Ce8jNOq+6zQPybsYemdAqOFusutuph988IOdrnN6/VNtHBaptsaujcw+ tlfZTgC9Q50ZoDAqXtterFiDL0ga5fqGfwnBt/5ai+mrcKZiVqh5UIfmK sYIrpMjxP+iiz1V7J3J0SIzLkaeUTZJZ47/+FqW/8JP6rsQA094IYC85L geH21Ew72kX2fPgQEon5DrvylQhUocd+SC4Do+hd++YTHhhzen2fHPIxZ izRW4zkjilfZlJrw93jBfuzyXxR6GyDpqUjPAjSZRMbE52djWZ4tQ9R7J P2IWwcw7eLy7NSzj6/z9pywHaUxQ/ch+at1iooYaiQ9S4FuA8ZTsx1bNL w==; X-CSE-ConnectionGUID: mr7xkTjPRfC6nMiM1hCsBA== X-CSE-MsgGUID: 4bQmao+RQ5iZHlLr9vVwOA== X-IronPort-AV: E=McAfee;i="6700,10204,11176"; a="13230482" X-IronPort-AV: E=Sophos;i="6.10,179,1719903600"; d="scan'208";a="13230482" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2024 22:09:39 -0700 X-CSE-ConnectionGUID: T/tEQ8O7QzWPUhkyZHcw8w== X-CSE-MsgGUID: iQnm5bk0R+m2IHOWeG5LVA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,179,1719903600"; d="scan'208";a="62703862" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orviesa009.jf.intel.com with ESMTP; 26 Aug 2024 22:09:38 -0700 From: Ricardo Neri To: x86@kernel.org Cc: Andreas Herrmann , Catalin Marinas , Chen Yu , Len Brown , Radu Rendec , Pierre Gondois , Pu Wen , "Rafael J. Wysocki" , Sudeep Holla , Srinivas Pandruvada , Will Deacon , Zhang Rui , Nikolay Borisov , Huang Ying , Ricardo Neri , linux-kernel@vger.kernel.org Subject: [PATCH v5 3/4] x86/cacheinfo: Delete global num_cache_leaves Date: Mon, 26 Aug 2024 22:16:34 -0700 Message-Id: <20240827051635.9114-4-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240827051635.9114-1-ricardo.neri-calderon@linux.intel.com> References: <20240827051635.9114-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Linux remembers cpu_cachinfo::num_leaves per CPU, but x86 initializes all CPUs from the same global "num_cache_leaves". This is erroneous on systems such as Meteor Lake, where each CPU has a distinct num_leaves value. Delete the global "num_cache_leaves" and initialize num_leaves on each CPU. Reviewed-by: Len Brown Signed-off-by: Ricardo Neri Reviewed-by: Andreas Herrmann Reviewed-by: Nikolay Borisov Tested-by: Andreas Herrmann --- Cc: Andreas Herrmann Cc: Catalin Marinas Cc: Chen Yu Cc: Huang Ying Cc: Len Brown Cc: Nikolay Borisov Cc: Radu Rendec Cc: Pierre Gondois Cc: Pu Wen Cc: "Rafael J. Wysocki" Cc: Sudeep Holla Cc: Srinivas Pandruvada Cc: Will Deacon Cc: Zhang Rui Cc: linux-arm-kernel@lists.infradead.org Cc: stable@vger.kernel.org # 6.3+ --- After this change, all CPUs will traverse CPUID leaf 0x4 when booted for the first time. On systems with symmetric cache topologies this is useless work. Creating a list of processor models that have asymmetric cache topologies was considered. The burden of maintaining such list would outweigh the performance benefit of skipping this extra step. --- Changes since v4: * None Changes since v3: * Rebased on v6.7-rc5. Changes since v2: * None Changes since v1: * Do not make num_cache_leaves a per-CPU variable. Instead, reuse the existing per-CPU ci_cpu_cacheinfo variable. (Dave Hansen) --- arch/x86/kernel/cpu/cacheinfo.c | 44 +++++++++++++++++++-------------- 1 file changed, 26 insertions(+), 18 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 392d09c936d6..b5e216677a46 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -178,7 +178,16 @@ struct _cpuid4_info_regs { struct amd_northbridge *nb; }; =20 -static unsigned short num_cache_leaves; +static inline unsigned int get_num_cache_leaves(unsigned int cpu) +{ + return get_cpu_cacheinfo(cpu)->num_leaves; +} + +static inline void +set_num_cache_leaves(unsigned int nr_leaves, unsigned int cpu) +{ + get_cpu_cacheinfo(cpu)->num_leaves =3D nr_leaves; +} =20 /* AMD doesn't have CPUID4. Emulate it here to report the same information to the user. This makes some assumptions about the machine: @@ -718,19 +727,21 @@ void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *= c) void init_amd_cacheinfo(struct cpuinfo_x86 *c) { =20 + unsigned int cpu =3D c->cpu_index; + if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { - num_cache_leaves =3D find_num_cache_leaves(c); + set_num_cache_leaves(find_num_cache_leaves(c), cpu); } else if (c->extended_cpuid_level >=3D 0x80000006) { if (cpuid_edx(0x80000006) & 0xf000) - num_cache_leaves =3D 4; + set_num_cache_leaves(4, cpu); else - num_cache_leaves =3D 3; + set_num_cache_leaves(3, cpu); } } =20 void init_hygon_cacheinfo(struct cpuinfo_x86 *c) { - num_cache_leaves =3D find_num_cache_leaves(c); + set_num_cache_leaves(find_num_cache_leaves(c), c->cpu_index); } =20 void init_intel_cacheinfo(struct cpuinfo_x86 *c) @@ -742,19 +753,19 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) unsigned int l2_id =3D 0, l3_id =3D 0, num_threads_sharing, index_msb; =20 if (c->cpuid_level > 3) { - static int is_initialized; - - if (is_initialized =3D=3D 0) { - /* Init num_cache_leaves from boot CPU */ - num_cache_leaves =3D find_num_cache_leaves(c); - is_initialized++; - } + /* + * There should be at least one leaf. A non-zero value means + * that the number of leaves has been initialized. + */ + if (!get_num_cache_leaves(c->cpu_index)) + set_num_cache_leaves(find_num_cache_leaves(c), + c->cpu_index); =20 /* * Whenever possible use cpuid(4), deterministic cache * parameters cpuid leaf to find the cache details */ - for (i =3D 0; i < num_cache_leaves; i++) { + for (i =3D 0; i < get_num_cache_leaves(c->cpu_index); i++) { struct _cpuid4_info_regs this_leaf =3D {}; int retval; =20 @@ -790,14 +801,14 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) * Don't use cpuid2 if cpuid4 is supported. For P4, we use cpuid2 for * trace cache */ - if ((num_cache_leaves =3D=3D 0 || c->x86 =3D=3D 15) && c->cpuid_level > 1= ) { + if ((!get_num_cache_leaves(c->cpu_index) || c->x86 =3D=3D 15) && c->cpuid= _level > 1) { /* supports eax=3D2 call */ int j, n; unsigned int regs[4]; unsigned char *dp =3D (unsigned char *)regs; int only_trace =3D 0; =20 - if (num_cache_leaves !=3D 0 && c->x86 =3D=3D 15) + if (get_num_cache_leaves(c->cpu_index) && c->x86 =3D=3D 15) only_trace =3D 1; =20 /* Number of times to iterate */ @@ -993,12 +1004,9 @@ int init_cache_level(unsigned int cpu) { struct cpu_cacheinfo *this_cpu_ci =3D get_cpu_cacheinfo(cpu); =20 - if (!num_cache_leaves) - return -ENOENT; if (!this_cpu_ci) return -EINVAL; this_cpu_ci->num_levels =3D 3; - this_cpu_ci->num_leaves =3D num_cache_leaves; return 0; } =20 --=20 2.34.1 From nobody Fri Dec 19 13:50:57 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 421F371B3A for ; Tue, 27 Aug 2024 05:09:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724735382; cv=none; b=mWpUJh8QYb4pPziWNn8d+lxNeU/IbLcqlCj+eoivrqgRfEAF9JZyHyEA5z7cJ3QWt7+NKZYl9H4jlBRGsiK9bVYdUAb29GCzaXwEWw5gH5YjaUcYjUr8zB7hfOkJoNnszdwYi+qxi0KI9B8l/b4O49KI0VXWW/4/4eS6YBtqrfg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724735382; c=relaxed/simple; bh=Fxb9EB2+t66KeDUfeYI2ZYfBCt/W8W8Cq7hOkfJ7WVI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=O2LP7Tk+wXK6xf56+OiTFeo6dCpdOyoebm50bagomvbGCeJUMpsxyBDZH+ZtbyosE+q22Go5w0oGp0QHEiVp/P0NSmHFLWfgkZyQzynu0kkxZQ32+n6d2iJ/6/2iSo+BWrHoREpgsVnfbAGBY+3/X65SITJfC3SAhy0zEnA5PXY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=kXLHy4By; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="kXLHy4By" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724735381; x=1756271381; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=Fxb9EB2+t66KeDUfeYI2ZYfBCt/W8W8Cq7hOkfJ7WVI=; b=kXLHy4ByMVMQPnyuR2l/9yymoouWIVkGr8RsA8+yUr7eSxoKR/zwa/uq VYiSJnB7kQd5fea4dE+exXtrqJcn9zaaTOvSGfzC5j0CenjO+2UqxhW3E /OdiEf6XOdyh/vv7l0t90kv0xmiV66sJWWmpF+QtEBpG/WTEsTWaGYcGE xhKxSsdhu5v9T8E5ehwu4+0rltp20PXFUoZorcB9/tN/oNcy7LOJBZz3f 9OHAKX0aqDD66TL4vkr/BGQ8JiLfUGuZfngPnmuH11m7tholAo2YrYlju ThR7vmRnD531u5GJzUghVMSDlHlTjjFJY6uk1BqvMgDTciuGfjrnBQYqE g==; X-CSE-ConnectionGUID: WsD1bKuHT3OtDPdjbsQu1Q== X-CSE-MsgGUID: 6cvHIx4mTbut/0DwZKol6A== X-IronPort-AV: E=McAfee;i="6700,10204,11176"; a="13230488" X-IronPort-AV: E=Sophos;i="6.10,179,1719903600"; d="scan'208";a="13230488" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2024 22:09:39 -0700 X-CSE-ConnectionGUID: QqkpBhfQTISliPkxHFC2yw== X-CSE-MsgGUID: vX9VQROrRSafoMbq527X4w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,179,1719903600"; d="scan'208";a="62703865" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orviesa009.jf.intel.com with ESMTP; 26 Aug 2024 22:09:39 -0700 From: Ricardo Neri To: x86@kernel.org Cc: Andreas Herrmann , Catalin Marinas , Chen Yu , Len Brown , Radu Rendec , Pierre Gondois , Pu Wen , "Rafael J. Wysocki" , Sudeep Holla , Srinivas Pandruvada , Will Deacon , Zhang Rui , Nikolay Borisov , Huang Ying , Ricardo Neri , linux-kernel@vger.kernel.org Subject: [PATCH v5 4/4] x86/cacheinfo: Clean out init_cache_level() Date: Mon, 26 Aug 2024 22:16:35 -0700 Message-Id: <20240827051635.9114-5-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240827051635.9114-1-ricardo.neri-calderon@linux.intel.com> References: <20240827051635.9114-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" init_cache_level() no longer has a purpose on x86. It no longer needs to set num_leaves, and it never had to set num_levels, which was unnecessary on x86. Replace it with "return 0" simply to override the weak function, which would return an error. Reviewed-by: Len Brown Signed-off-by: Ricardo Neri Reviewed-by: Andreas Herrmann Reviewed-by: Nikolay Borisov Tested-by: Andreas Herrmann --- Cc: Andreas Herrmann Cc: Catalin Marinas Cc: Chen Yu CC: Huang Ying Cc: Len Brown Cc: Nikolay Borisov Cc: Radu Rendec Cc: Pierre Gondois Cc: Pu Wen Cc: "Rafael J. Wysocki" Cc: Sudeep Holla Cc: Srinivas Pandruvada Cc: Will Deacon Cc: Zhang Rui Cc: linux-arm-kernel@lists.infradead.org Cc: stable@vger.kernel.org # 6.3+ --- Changes since v4: * None Changes since v3: * Rebased on v6.7-rc5. Changes since v2: * None Changes since v1: * Introduced this patch. --- arch/x86/kernel/cpu/cacheinfo.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index b5e216677a46..d7375328bc1f 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -1002,11 +1002,6 @@ static void ci_leaf_init(struct cacheinfo *this_leaf, =20 int init_cache_level(unsigned int cpu) { - struct cpu_cacheinfo *this_cpu_ci =3D get_cpu_cacheinfo(cpu); - - if (!this_cpu_ci) - return -EINVAL; - this_cpu_ci->num_levels =3D 3; return 0; } =20 --=20 2.34.1