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([82.78.167.144]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a86e548781csm446566b.28.2024.08.26.10.31.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2024 10:31:26 -0700 (PDT) From: Claudiu Beznea To: nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH 3/3] ARM: dts: microchip: Use SCKC_{TD, MD}_SLCK IDs for clk32k clocks Date: Mon, 26 Aug 2024 20:31:16 +0300 Message-Id: <20240826173116.3628337-4-claudiu.beznea@tuxon.dev> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240826173116.3628337-1-claudiu.beznea@tuxon.dev> References: <20240826173116.3628337-1-claudiu.beznea@tuxon.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use the newly introduced macros instead of raw number. With this device tree code is a bit easier to understand. Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sam9x60.dtsi | 18 +++++++++--------- arch/arm/boot/dts/microchip/sama7g5.dtsi | 16 ++++++++-------- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm/boot/dts/microchip/sam9x60.dtsi b/arch/arm/boot/dts/m= icrochip/sam9x60.dtsi index 04a6d716ecaf..eeda277e684f 100644 --- a/arch/arm/boot/dts/microchip/sam9x60.dtsi +++ b/arch/arm/boot/dts/microchip/sam9x60.dtsi @@ -560,7 +560,7 @@ tcb0: timer@f8008000 { #size-cells =3D <0>; reg =3D <0xf8008000 0x100>; interrupts =3D <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks =3D <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k SCKC_MD_SLCK>; clock-names =3D "t0_clk", "slow_clk"; }; =20 @@ -570,7 +570,7 @@ tcb1: timer@f800c000 { #size-cells =3D <0>; reg =3D <0xf800c000 0x100>; interrupts =3D <45 IRQ_TYPE_LEVEL_HIGH 0>; - clocks =3D <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k SCKC_MD_SLCK>; clock-names =3D "t0_clk", "slow_clk"; }; =20 @@ -1038,7 +1038,7 @@ hlcdc: hlcdc@f8038000 { compatible =3D "microchip,sam9x60-hlcdc"; reg =3D <0xf8038000 0x4000>; interrupts =3D <25 IRQ_TYPE_LEVEL_HIGH 0>; - clocks =3D <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&cl= k32k 1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&cl= k32k SCKC_TD_SLCK>; clock-names =3D "periph_clk","sys_clk", "slow_clk"; assigned-clocks =3D <&pmc PMC_TYPE_GCK 25>; assigned-clock-parents =3D <&pmc PMC_TYPE_CORE PMC_MCK>; @@ -1313,20 +1313,20 @@ pmc: clock-controller@fffffc00 { reg =3D <0xfffffc00 0x200>; interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH 7>; #clock-cells =3D <2>; - clocks =3D <&clk32k 1>, <&clk32k 0>, <&main_xtal>; + clocks =3D <&clk32k SCKC_TD_SLCK>, <&clk32k SCKC_MD_SLCK>, <&main_xtal= >; clock-names =3D "td_slck", "md_slck", "main_xtal"; }; =20 reset_controller: reset-controller@fffffe00 { compatible =3D "microchip,sam9x60-rstc"; reg =3D <0xfffffe00 0x10>; - clocks =3D <&clk32k 0>; + clocks =3D <&clk32k SCKC_MD_SLCK>; }; =20 shutdown_controller: poweroff@fffffe10 { compatible =3D "microchip,sam9x60-shdwc"; reg =3D <0xfffffe10 0x10>; - clocks =3D <&clk32k 0>; + clocks =3D <&clk32k SCKC_MD_SLCK>; #address-cells =3D <1>; #size-cells =3D <0>; atmel,wakeup-rtc-timer; @@ -1338,7 +1338,7 @@ rtt: rtc@fffffe20 { compatible =3D "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; reg =3D <0xfffffe20 0x20>; interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks =3D <&clk32k 1>; + clocks =3D <&clk32k SCKC_TD_SLCK>; }; =20 pit: timer@fffffe40 { @@ -1364,14 +1364,14 @@ rtc: rtc@fffffea8 { compatible =3D "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc"; reg =3D <0xfffffea8 0x100>; interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks =3D <&clk32k 1>; + clocks =3D <&clk32k SCKC_TD_SLCK>; }; =20 watchdog: watchdog@ffffff80 { compatible =3D "microchip,sam9x60-wdt"; reg =3D <0xffffff80 0x24>; interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks =3D <&clk32k 0>; + clocks =3D <&clk32k SCKC_MD_SLCK>; status =3D "disabled"; }; }; diff --git a/arch/arm/boot/dts/microchip/sama7g5.dtsi b/arch/arm/boot/dts/m= icrochip/sama7g5.dtsi index 17bcdcf0cf4a..2efca9838d69 100644 --- a/arch/arm/boot/dts/microchip/sama7g5.dtsi +++ b/arch/arm/boot/dts/microchip/sama7g5.dtsi @@ -246,7 +246,7 @@ pmc: clock-controller@e0018000 { reg =3D <0xe0018000 0x200>; interrupts =3D ; #clock-cells =3D <2>; - clocks =3D <&clk32k 1>, <&clk32k 0>, <&main_xtal>; + clocks =3D <&clk32k SCKC_TD_SLCK>, <&clk32k SCKC_MD_SLCK>, <&main_xtal>; clock-names =3D "td_slck", "md_slck", "main_xtal"; }; =20 @@ -254,13 +254,13 @@ reset_controller: reset-controller@e001d000 { compatible =3D "microchip,sama7g5-rstc"; reg =3D <0xe001d000 0xc>, <0xe001d0e4 0x4>; #reset-cells =3D <1>; - clocks =3D <&clk32k 0>; + clocks =3D <&clk32k SCKC_MD_SLCK>; }; =20 shdwc: poweroff@e001d010 { compatible =3D "microchip,sama7g5-shdwc", "syscon"; reg =3D <0xe001d010 0x10>; - clocks =3D <&clk32k 0>; + clocks =3D <&clk32k SCKC_MD_SLCK>; #address-cells =3D <1>; #size-cells =3D <0>; atmel,wakeup-rtc-timer; @@ -272,7 +272,7 @@ rtt: rtc@e001d020 { compatible =3D "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel= ,at91sam9260-rtt"; reg =3D <0xe001d020 0x30>; interrupts =3D ; - clocks =3D <&clk32k 1>; + clocks =3D <&clk32k SCKC_TD_SLCK>; }; =20 clk32k: clock-controller@e001d050 { @@ -291,14 +291,14 @@ rtc: rtc@e001d0a8 { compatible =3D "microchip,sama7g5-rtc", "microchip,sam9x60-rtc"; reg =3D <0xe001d0a8 0x30>; interrupts =3D ; - clocks =3D <&clk32k 1>; + clocks =3D <&clk32k SCKC_TD_SLCK>; }; =20 ps_wdt: watchdog@e001d180 { compatible =3D "microchip,sama7g5-wdt"; reg =3D <0xe001d180 0x24>; interrupts =3D ; - clocks =3D <&clk32k 0>; + clocks =3D <&clk32k SCKC_MD_SLCK>; }; =20 chipid@e0020000 { @@ -312,7 +312,7 @@ tcb1: timer@e0800000 { #size-cells =3D <0>; reg =3D <0xe0800000 0x100>; interrupts =3D , , ; - clocks =3D <&pmc PMC_TYPE_PERIPHERAL 91>, <&pmc PMC_TYPE_PERIPHERAL 92>= , <&pmc PMC_TYPE_PERIPHERAL 93>, <&clk32k 1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 91>, <&pmc PMC_TYPE_PERIPHERAL 92>= , <&pmc PMC_TYPE_PERIPHERAL 93>, <&clk32k SCKC_TD_SLCK>; clock-names =3D "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; =20 @@ -906,7 +906,7 @@ tcb0: timer@e2814000 { #size-cells =3D <0>; reg =3D <0xe2814000 0x100>; interrupts =3D , , ; - clocks =3D <&pmc PMC_TYPE_PERIPHERAL 88>, <&pmc PMC_TYPE_PERIPHERAL 89>= , <&pmc PMC_TYPE_PERIPHERAL 90>, <&clk32k 1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 88>, <&pmc PMC_TYPE_PERIPHERAL 89>= , <&pmc PMC_TYPE_PERIPHERAL 90>, <&clk32k SCKC_TD_SLCK>; clock-names =3D "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; =20 --=20 2.39.2