From nobody Wed Dec 17 01:25:17 2025 Received: from mail-40133.protonmail.ch (mail-40133.protonmail.ch [185.70.40.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56811185931; Mon, 26 Aug 2024 12:38:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.40.133 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724675918; cv=none; b=KR29KSGhwTVAaSXmGywiUVGb9OrJqN5VhLFArwcYo117uWyXuRcN/rpWAGdJVHqwhoz5gpjAKFerGLab4Sh6RRHTpfv0rAB0kKmNWjKiltWVJC818Ln3TKw5F3/M6DqXIufRM9dWX9BK46p5L84G/palPfAs2JFd3lHZjxMGy7s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724675918; c=relaxed/simple; bh=FBOWkOJ8Fv8/HjudbpS8HPnjZSATpEa1kECwdzoWEUs=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=AqYLL2BK86wOB/J0k+JcowZ0esKaDYFALrBrcwY7ZebrzXjQmDARQ4stv4N1nWd60lQ1xcK0t3mTTUCfcjlEEoJgcENkmpIriS3b8gO2SqMWtNF1HFkvY5Ozyq3cV3t6VFWs2hjNCHvuS3V57ITbgfFsh3H2Hp9fa6knZH9Q5/k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=protonmail.com; spf=pass smtp.mailfrom=protonmail.com; dkim=pass (2048-bit key) header.d=protonmail.com header.i=@protonmail.com header.b=HjEsGjgf; arc=none smtp.client-ip=185.70.40.133 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=protonmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=protonmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=protonmail.com header.i=@protonmail.com header.b="HjEsGjgf" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.com; s=protonmail3; t=1724675908; x=1724935108; bh=0DFY+wLkYuEWyBy/mhSUmuzkOWFdO8lFfTnXo28Nt74=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=HjEsGjgf7W37hkP1e5QLGoI0+JYT5Uf7dmKXwDzgBTfU4bV4ON5OjRMfm3IacW5BT SoYLHbxQt07XGk5rtFdPNAJO3MgtmWF2l2COlFX/pJX4PMMdQr90EiuoCQL9ARxPnE olqXL5ptOWeAmhTkLMYd1TfqIO7APF74Mo8kvkEQsR9VTyf63nsb74ztgPuf3CZBs/ VrRMzUBDslq83Av8BpZV1nMv8njthYTsBGMgNBPAd10l4dQAwSdpdlyyVazJz/3LcU aR+6uXulhQ5VE8YTViSrrqL18C05H5PaRrqQBLfa15Jp3a2fzd9DS4FcLJKNkFOMY+ 7bdqNqg8ON01A== Date: Mon, 26 Aug 2024 12:38:24 +0000 To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Simek , Greg Kroah-Hartman From: Harry Austen Cc: Shubhrajyoti Datta , Dave Ertman , Ira Weiny , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Harry Austen Subject: [PATCH v3 4/9] clk: clocking-wizard: move clock registration to separate function Message-ID: <20240826123602.1872-5-hpausten@protonmail.com> In-Reply-To: <20240826123602.1872-1-hpausten@protonmail.com> References: <20240826123602.1872-1-hpausten@protonmail.com> Feedback-ID: 53116287:user:proton X-Pm-Message-ID: 45e8454da06f098c8983fadc75a227a513988076 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Provide clear separation of dynamic reconfiguration logic, by moving its setup procedure to its own dedicated function. Signed-off-by: Harry Austen --- drivers/clk/xilinx/clk-xlnx-clock-wizard.c | 143 +++++++++++---------- 1 file changed, 75 insertions(+), 68 deletions(-) diff --git a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c b/drivers/clk/xilin= x/clk-xlnx-clock-wizard.c index f332e0eee56c8..1a65a7d153c35 100644 --- a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c +++ b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c @@ -962,72 +962,30 @@ static const struct versal_clk_data versal_data =3D { .is_versal =3D true, }; =20 -static int clk_wzrd_probe(struct platform_device *pdev) +static int clk_wzrd_register_output_clocks(struct device *dev, int nr_outp= uts) { const char *clkout_name, *clk_name, *clk_mul_name; + struct clk_wzrd *clk_wzrd =3D dev_get_drvdata(dev); u32 regl, regh, edge, regld, reghd, edged, div; - struct device_node *np =3D pdev->dev.of_node; const struct versal_clk_data *data; - struct clk_wzrd *clk_wzrd; unsigned long flags =3D 0; + bool is_versal =3D false; void __iomem *ctrl_reg; u32 reg, reg_f, mult; - bool is_versal =3D false; - unsigned long rate; - int nr_outputs; - int i, ret; - - ret =3D of_property_read_u32(np, "xlnx,nr-outputs", &nr_outputs); - if (ret || nr_outputs > WZRD_NUM_OUTPUTS) - return -EINVAL; - - clk_wzrd =3D devm_kzalloc(&pdev->dev, struct_size(clk_wzrd, clk_data.hws,= nr_outputs), - GFP_KERNEL); - if (!clk_wzrd) - return -ENOMEM; - platform_set_drvdata(pdev, clk_wzrd); - - clk_wzrd->base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(clk_wzrd->base)) - return PTR_ERR(clk_wzrd->base); - - ret =3D of_property_read_u32(np, "xlnx,speed-grade", &clk_wzrd->speed_gra= de); - if (!ret) { - if (clk_wzrd->speed_grade < 1 || clk_wzrd->speed_grade > 3) { - dev_warn(&pdev->dev, "invalid speed grade '%d'\n", - clk_wzrd->speed_grade); - clk_wzrd->speed_grade =3D 0; - } - } - - clk_wzrd->clk_in1 =3D devm_clk_get(&pdev->dev, "clk_in1"); - if (IS_ERR(clk_wzrd->clk_in1)) - return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->clk_in1), - "clk_in1 not found\n"); + int i; =20 - clk_wzrd->axi_clk =3D devm_clk_get_enabled(&pdev->dev, "s_axi_aclk"); - if (IS_ERR(clk_wzrd->axi_clk)) - return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->axi_clk), - "s_axi_aclk not found\n"); - rate =3D clk_get_rate(clk_wzrd->axi_clk); - if (rate > WZRD_ACLK_MAX_FREQ) { - dev_err(&pdev->dev, "s_axi_aclk frequency (%lu) too high\n", - rate); - return -EINVAL; - } - - data =3D device_get_match_data(&pdev->dev); + data =3D device_get_match_data(dev); if (data) is_versal =3D data->is_versal; =20 - clkout_name =3D devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_out0", dev_nam= e(&pdev->dev)); + clkout_name =3D devm_kasprintf(dev, GFP_KERNEL, "%s_out0", dev_name(dev)); if (!clkout_name) return -ENOMEM; =20 if (is_versal) { if (nr_outputs =3D=3D 1) { clk_wzrd->clk_data.hws[0] =3D clk_wzrd_ver_register_divider - (&pdev->dev, clkout_name, + (dev, clkout_name, __clk_get_name(clk_wzrd->clk_in1), 0, clk_wzrd->base, WZRD_CLK_CFG_REG(is_versal, 3), WZRD_CLKOUT_DIVIDE_SHIFT, @@ -1035,7 +993,7 @@ static int clk_wzrd_probe(struct platform_device *pdev) CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, DIV_ALL, &clkwzrd_lock); =20 - goto out; + return 0; } /* register multiplier */ edge =3D !!(readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 0)) & @@ -1060,7 +1018,7 @@ static int clk_wzrd_probe(struct platform_device *pde= v) } else { if (nr_outputs =3D=3D 1) { clk_wzrd->clk_data.hws[0] =3D clk_wzrd_register_divider - (&pdev->dev, clkout_name, + (dev, clkout_name, __clk_get_name(clk_wzrd->clk_in1), 0, clk_wzrd->base, WZRD_CLK_CFG_REG(is_versal, 3), WZRD_CLKOUT_DIVIDE_SHIFT, @@ -1068,7 +1026,7 @@ static int clk_wzrd_probe(struct platform_device *pde= v) CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, DIV_ALL, &clkwzrd_lock); =20 - goto out; + return 0; } reg =3D readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 0)); reg_f =3D reg & WZRD_CLKFBOUT_FRAC_MASK; @@ -1079,19 +1037,19 @@ static int clk_wzrd_probe(struct platform_device *p= dev) mult =3D (reg * 1000) + reg_f; div =3D 1000; } - clk_name =3D devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_mul", dev_name(&p= dev->dev)); + clk_name =3D devm_kasprintf(dev, GFP_KERNEL, "%s_mul", dev_name(dev)); if (!clk_name) return -ENOMEM; clk_wzrd->clks_internal[wzrd_clk_mul] =3D devm_clk_hw_register_fixed_fact= or - (&pdev->dev, clk_name, + (dev, clk_name, __clk_get_name(clk_wzrd->clk_in1), 0, mult, div); if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul])) { - dev_err(&pdev->dev, "unable to register fixed-factor clock\n"); + dev_err(dev, "unable to register fixed-factor clock\n"); return PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul]); } =20 - clk_name =3D devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_mul_div", dev_nam= e(&pdev->dev)); + clk_name =3D devm_kasprintf(dev, GFP_KERNEL, "%s_mul_div", dev_name(dev)); if (!clk_name) return -ENOMEM; =20 @@ -1108,31 +1066,29 @@ static int clk_wzrd_probe(struct platform_device *p= dev) =20 clk_mul_name =3D clk_hw_get_name(clk_wzrd->clks_internal[wzrd_clk_mul]); clk_wzrd->clks_internal[wzrd_clk_mul_div] =3D - devm_clk_hw_register_fixed_factor(&pdev->dev, clk_name, - clk_mul_name, 0, 1, div); + devm_clk_hw_register_fixed_factor(dev, clk_name, clk_mul_name, 0, 1, di= v); } else { ctrl_reg =3D clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 0); clk_wzrd->clks_internal[wzrd_clk_mul_div] =3D devm_clk_hw_register_divid= er - (&pdev->dev, clk_name, + (dev, clk_name, clk_hw_get_name(clk_wzrd->clks_internal[wzrd_clk_mul]), flags, ctrl_reg, 0, 8, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, &clkwzrd_lock); } if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div])) { - dev_err(&pdev->dev, "unable to register divider clock\n"); + dev_err(dev, "unable to register divider clock\n"); return PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div]); } =20 /* register div per output */ for (i =3D nr_outputs - 1; i >=3D 0 ; i--) { - clkout_name =3D devm_kasprintf(&pdev->dev, GFP_KERNEL, - "%s_out%d", dev_name(&pdev->dev), i); + clkout_name =3D devm_kasprintf(dev, GFP_KERNEL, "%s_out%d", dev_name(dev= ), i); if (!clkout_name) return -ENOMEM; =20 if (is_versal) { clk_wzrd->clk_data.hws[i] =3D clk_wzrd_ver_register_divider - (&pdev->dev, + (dev, clkout_name, clk_name, 0, clk_wzrd->base, (WZRD_CLK_CFG_REG(is_versal, 3) + i * 8), @@ -1144,7 +1100,7 @@ static int clk_wzrd_probe(struct platform_device *pde= v) } else { if (!i) clk_wzrd->clk_data.hws[i] =3D clk_wzrd_register_divf - (&pdev->dev, clkout_name, clk_name, flags, clk_wzrd->base, + (dev, clkout_name, clk_name, flags, clk_wzrd->base, (WZRD_CLK_CFG_REG(is_versal, 2) + i * 12), WZRD_CLKOUT_DIVIDE_SHIFT, WZRD_CLKOUT_DIVIDE_WIDTH, @@ -1152,7 +1108,7 @@ static int clk_wzrd_probe(struct platform_device *pde= v) DIV_O, &clkwzrd_lock); else clk_wzrd->clk_data.hws[i] =3D clk_wzrd_register_divider - (&pdev->dev, clkout_name, clk_name, 0, clk_wzrd->base, + (dev, clkout_name, clk_name, 0, clk_wzrd->base, (WZRD_CLK_CFG_REG(is_versal, 2) + i * 12), WZRD_CLKOUT_DIVIDE_SHIFT, WZRD_CLKOUT_DIVIDE_WIDTH, @@ -1160,13 +1116,64 @@ static int clk_wzrd_probe(struct platform_device *p= dev) DIV_O, &clkwzrd_lock); } if (IS_ERR(clk_wzrd->clk_data.hws[i])) { - dev_err(&pdev->dev, - "unable to register divider clock\n"); + dev_err(dev, "unable to register divider clock\n"); return PTR_ERR(clk_wzrd->clk_data.hws[i]); } } =20 -out: + return 0; +} + +static int clk_wzrd_probe(struct platform_device *pdev) +{ + struct device_node *np =3D pdev->dev.of_node; + struct clk_wzrd *clk_wzrd; + unsigned long rate; + int nr_outputs; + int ret; + + ret =3D of_property_read_u32(np, "xlnx,nr-outputs", &nr_outputs); + if (ret || nr_outputs > WZRD_NUM_OUTPUTS) + return -EINVAL; + + clk_wzrd =3D devm_kzalloc(&pdev->dev, struct_size(clk_wzrd, clk_data.hws,= nr_outputs), + GFP_KERNEL); + if (!clk_wzrd) + return -ENOMEM; + platform_set_drvdata(pdev, clk_wzrd); + + clk_wzrd->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(clk_wzrd->base)) + return PTR_ERR(clk_wzrd->base); + + ret =3D of_property_read_u32(np, "xlnx,speed-grade", &clk_wzrd->speed_gra= de); + if (!ret) { + if (clk_wzrd->speed_grade < 1 || clk_wzrd->speed_grade > 3) { + dev_warn(&pdev->dev, "invalid speed grade '%d'\n", + clk_wzrd->speed_grade); + clk_wzrd->speed_grade =3D 0; + } + } + + clk_wzrd->clk_in1 =3D devm_clk_get(&pdev->dev, "clk_in1"); + if (IS_ERR(clk_wzrd->clk_in1)) + return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->clk_in1), + "clk_in1 not found\n"); + + clk_wzrd->axi_clk =3D devm_clk_get_enabled(&pdev->dev, "s_axi_aclk"); + if (IS_ERR(clk_wzrd->axi_clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->axi_clk), + "s_axi_aclk not found\n"); + rate =3D clk_get_rate(clk_wzrd->axi_clk); + if (rate > WZRD_ACLK_MAX_FREQ) { + dev_err(&pdev->dev, "s_axi_aclk frequency (%lu) too high\n", rate); + return -EINVAL; + } + + ret =3D clk_wzrd_register_output_clocks(&pdev->dev, nr_outputs); + if (ret) + return ret; + clk_wzrd->clk_data.num =3D nr_outputs; ret =3D devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get, &c= lk_wzrd->clk_data); if (ret) { --=20 2.46.0