From nobody Thu Sep 19 19:32:48 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4097E80603 for ; Mon, 26 Aug 2024 06:07:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724652434; cv=none; b=mC3AXpPjZZIM5qyCft9jb6GzqhutZKnEf1SfIRm9b1IviLCwevN34gHLHiivMVrEfzbMLEtOxbCJzJAb3lJRFHGu42cdFVNp6aLzvG5BM24Hu6L6jWKCHCaCA4x7zgww7G3fWKFcIzfAi9BO4ZlXGYVADDg9VFMYCIggs2NhEhg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724652434; c=relaxed/simple; bh=yl961lceJEZQ9ymatorRCSTi9T7xuYy8X1Z+bM31i00=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=srzgd2Qn3soP124kqnx0Be8ptZkvAuxY84TKGkaX3d9O4qcL5mNjoxq03YpkMsdIUz+IeUhByIQXb1J0tiYsQr7XcN9bAtzHm8kWzUZFyh3UuQfXQvOm+ucdn9eYjd9TjBxLzuyWUVOwhike8t0KZHkOtchYScUl2FO4ZWXFHe0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=qBvrLMhf; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="qBvrLMhf" X-UUID: 6731d2ba637111ef8593d301e5c8a9c0-20240826 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=Jywz5mOWgU6WNvfbwYrlvZc1NoCCk1aB4yuwINTE8rg=; b=qBvrLMhfJLkRPoTodiafp31kNegr5FORlTC2MH+pDL3/gp1nLShr+Ud3hPKJSZ1MjVTYeJ1tlDK/j9tl1XCH1XQxRXlDaSmJqbKEdTMnYJHNwWmBVb27XU0rOrtMst8HyFtTSnUbHEOWoI7U0CwllY+KApK8geWtOcWoWzwTcTU=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.41,REQID:e2372296-6fd6-4d7d-bf88-edb89511b9a2,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:6dc6a47,CLOUDID:04a0ca14-737d-40b3-9394-11d4ad6e91a1,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES :1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: 6731d2ba637111ef8593d301e5c8a9c0-20240826 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1950966389; Mon, 26 Aug 2024 14:06:58 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 26 Aug 2024 14:06:59 +0800 Received: from mszsdhlt06.gcn.mediatek.inc (10.16.6.206) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 26 Aug 2024 14:06:59 +0800 From: Shuijing Li To: , , , , , , CC: , , , , , Shuijing Li Subject: [PATCH v8] drm/mediatek: dsi: Add dsi per-frame lp code for mt8188 Date: Mon, 26 Aug 2024 14:06:20 +0800 Message-ID: <20240826060654.24038-1-shuijing.li@mediatek.com> X-Mailer: git-send-email 2.45.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" Adding the per-frame lp function of mt8188, which can keep HFP in HS and reduce the time required for each line to enter and exit low power. Per Frame LP: |<----------One Active Frame-------->| --______________________________________----___________________ ^HSA+HBP^^RGB^^HFP^^HSA+HBP^^RGB^^HFP^ ^HSA+HBP^^RGB^^HFP^ Per Line LP: |<---------------One Active Frame----------->| --______________--______________--______________----______________ ^HSA+HBP^^RGB^ ^HSA+HBP^^RGB^ ^HSA+HBP^^RGB^ ^HSA+HBP^^RGB^ Signed-off-by: Shuijing Li Reviewed-by: CK Hu --- Changes in v8: Directly write value into DSI_HSTX_CKL_WC without check per suggestion from= previous thread: https://patchwork.kernel.org/project/linux-mediatek/patch/20240819061333.26= 069-1-shuijing.li@mediatek.com/ Changes in v7: Fix code style and simplify the code per suggestion from previous thread: https://patchwork.kernel.org/project/linux-mediatek/patch/20240813022315.18= 502-1-shuijing.li@mediatek.com/ Changes in v6: Simplify the code per suggestion from previous thread: https://patchwork.kernel.org/project/linux-mediatek/patch/20240812070341.26= 053-1-shuijing.li@mediatek.com/ Changes in v5: Fix code style issue and add per-line-lp function to be symmetrical with pe= r-frame-lp. per suggestion from previous thread: https://patchwork.kernel.org/project/linux-mediatek/patch/20240801081144.22= 372-1-shuijing.li@mediatek.com/ Changes in v4: Drop the code related to bllp_en and bllp_wc, adjust ps_wc to dsi->vm.hacti= ve * dsi_buf_bpp. Changes in v3: Use function in bitfield.h and get value from phy timing, per suggestion from previous thread: https://patchwork.kernel.org/project/linux-mediatek/patch/20240424091639.22= 759-1-shuijing.li@mediatek.com/ Changes in v2: Use bitfield macros and add new function for per prame lp and improve the format, per suggestion from previous thread: https://patchwork.kernel.org/project/linux-mediatek/patch/20240314094238.33= 15-1-shuijing.li@mediatek.com/ --- drivers/gpu/drm/mediatek/mtk_dsi.c | 106 +++++++++++++++++++++++++---- 1 file changed, 94 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/= mtk_dsi.c index b6e3c011a12d..eeec641cab60 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -88,12 +88,15 @@ #define DSI_HSA_WC 0x50 #define DSI_HBP_WC 0x54 #define DSI_HFP_WC 0x58 +#define HFP_HS_VB_PS_WC GENMASK(30, 16) +#define HFP_HS_EN BIT(31) =20 #define DSI_CMDQ_SIZE 0x60 #define CMDQ_SIZE 0x3f #define CMDQ_SIZE_SEL BIT(15) =20 #define DSI_HSTX_CKL_WC 0x64 +#define HSTX_CKL_WC GENMASK(15, 2) =20 #define DSI_RX_DATA0 0x74 #define DSI_RX_DATA1 0x78 @@ -187,6 +190,7 @@ struct mtk_dsi_driver_data { bool has_shadow_ctl; bool has_size_ctl; bool cmdq_long_packet_ctl; + bool support_per_frame_lp; }; =20 struct mtk_dsi { @@ -426,7 +430,75 @@ static void mtk_dsi_ps_control(struct mtk_dsi *dsi, bo= ol config_vact) writel(ps_val, dsi->regs + DSI_PSCTRL); } =20 -static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) +static void mtk_dsi_config_vdo_timing_per_frame_lp(struct mtk_dsi *dsi) +{ + u32 horizontal_sync_active_byte; + u32 horizontal_backporch_byte; + u32 horizontal_frontporch_byte; + u32 hfp_byte_adjust, v_active_adjust; + u32 cklp_wc_min_adjust, cklp_wc_max_adjust; + u32 dsi_tmp_buf_bpp; + unsigned int da_hs_trail; + unsigned int ps_wc, hs_vb_ps_wc; + u32 v_active_roundup, hstx_cklp_wc; + u32 hstx_cklp_wc_max, hstx_cklp_wc_min; + struct videomode *vm =3D &dsi->vm; + + if (dsi->format =3D=3D MIPI_DSI_FMT_RGB565) + dsi_tmp_buf_bpp =3D 2; + else + dsi_tmp_buf_bpp =3D 3; + + da_hs_trail =3D dsi->phy_timing.da_hs_trail; + ps_wc =3D vm->hactive * dsi_tmp_buf_bpp; + + if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { + horizontal_sync_active_byte =3D + vm->hsync_len * dsi_tmp_buf_bpp - 10; + horizontal_backporch_byte =3D + vm->hback_porch * dsi_tmp_buf_bpp - 10; + hfp_byte_adjust =3D 12; + v_active_adjust =3D 32 + horizontal_sync_active_byte; + cklp_wc_min_adjust =3D 12 + 2 + 4 + horizontal_sync_active_byte; + cklp_wc_max_adjust =3D 20 + 6 + 4 + horizontal_sync_active_byte; + } else { + horizontal_sync_active_byte =3D vm->hsync_len * dsi_tmp_buf_bpp - 4; + horizontal_backporch_byte =3D (vm->hback_porch + vm->hsync_len) * + dsi_tmp_buf_bpp - 10; + cklp_wc_min_adjust =3D 4; + cklp_wc_max_adjust =3D 12 + 4 + 4; + if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { + hfp_byte_adjust =3D 18; + v_active_adjust =3D 28; + } else { + hfp_byte_adjust =3D 12; + v_active_adjust =3D 22; + } + } + horizontal_frontporch_byte =3D vm->hfront_porch * dsi_tmp_buf_bpp - hfp_b= yte_adjust; + v_active_roundup =3D (v_active_adjust + horizontal_backporch_byte + ps_wc= + + horizontal_frontporch_byte) % dsi->lanes; + if (v_active_roundup) + horizontal_backporch_byte +=3D dsi->lanes - v_active_roundup; + hstx_cklp_wc_min =3D (DIV_ROUND_UP(cklp_wc_min_adjust, dsi->lanes) + da_h= s_trail + 1) + * dsi->lanes / 6 - 1; + hstx_cklp_wc_max =3D (DIV_ROUND_UP((cklp_wc_max_adjust + horizontal_backp= orch_byte + + ps_wc), dsi->lanes) + da_hs_trail + 1) * dsi->lanes / 6 - 1; + + hstx_cklp_wc =3D FIELD_PREP(HSTX_CKL_WC, (hstx_cklp_wc_min + hstx_cklp_wc= _max) / 2); + writel(hstx_cklp_wc, dsi->regs + DSI_HSTX_CKL_WC); + + hs_vb_ps_wc =3D ps_wc - (dsi->phy_timing.lpx + dsi->phy_timing.da_hs_exit= + + dsi->phy_timing.da_hs_prepare + dsi->phy_timing.da_hs_zero + 2) * = dsi->lanes; + horizontal_frontporch_byte |=3D FIELD_PREP(HFP_HS_EN, 1) | + FIELD_PREP(HFP_HS_VB_PS_WC, hs_vb_ps_wc); + + writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC); + writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); + writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC); +} + +static void mtk_dsi_config_vdo_timing_per_line_lp(struct mtk_dsi *dsi) { u32 horizontal_sync_active_byte; u32 horizontal_backporch_byte; @@ -436,7 +508,6 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *d= si) u32 dsi_tmp_buf_bpp, data_phy_cycles; u32 delta; struct mtk_phy_timing *timing =3D &dsi->phy_timing; - struct videomode *vm =3D &dsi->vm; =20 if (dsi->format =3D=3D MIPI_DSI_FMT_RGB565) @@ -444,16 +515,6 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *= dsi) else dsi_tmp_buf_bpp =3D 3; =20 - writel(vm->vsync_len, dsi->regs + DSI_VSA_NL); - writel(vm->vback_porch, dsi->regs + DSI_VBP_NL); - writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL); - writel(vm->vactive, dsi->regs + DSI_VACT_NL); - - if (dsi->driver_data->has_size_ctl) - writel(FIELD_PREP(DSI_HEIGHT, vm->vactive) | - FIELD_PREP(DSI_WIDTH, vm->hactive), - dsi->regs + DSI_SIZE_CON); - horizontal_sync_active_byte =3D (vm->hsync_len * dsi_tmp_buf_bpp - 10); =20 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) @@ -499,6 +560,26 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *= dsi) writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC); writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC); +} + +static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) +{ + struct videomode *vm =3D &dsi->vm; + + writel(vm->vsync_len, dsi->regs + DSI_VSA_NL); + writel(vm->vback_porch, dsi->regs + DSI_VBP_NL); + writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL); + writel(vm->vactive, dsi->regs + DSI_VACT_NL); + + if (dsi->driver_data->has_size_ctl) + writel(FIELD_PREP(DSI_HEIGHT, vm->vactive) | + FIELD_PREP(DSI_WIDTH, vm->hactive), + dsi->regs + DSI_SIZE_CON); + + if (dsi->driver_data->support_per_frame_lp) + mtk_dsi_config_vdo_timing_per_frame_lp(dsi); + else + mtk_dsi_config_vdo_timing_per_line_lp(dsi); =20 mtk_dsi_ps_control(dsi, false); } @@ -1197,6 +1278,7 @@ static const struct mtk_dsi_driver_data mt8188_dsi_dr= iver_data =3D { .has_shadow_ctl =3D true, .has_size_ctl =3D true, .cmdq_long_packet_ctl =3D true, + .support_per_frame_lp =3D true, }; =20 static const struct of_device_id mtk_dsi_of_match[] =3D { --=20 2.45.2