From nobody Sun Feb 8 21:26:32 2026 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C24A01C8251; Fri, 23 Aug 2024 21:54:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724450097; cv=none; b=MRwnkErfPbpVy0YefY3VDErpcnFZzfcSgfWKytezW6d//0UJJjuts2k81kiA8bAEZRRRBxIYlWI31U7LtWzQQsxVTSmpgnLk6mjnQwWcNQnVOuD/y7ln4j6zW1Bm7mme4gq9qRNB8iaGjALH8ExVgSK5VbK/6ssiyXwg6rNnQHI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724450097; c=relaxed/simple; bh=G3IAVHLyG7E87LHtcgIvTkH6X5CEXq/IcP/RA6DZXUk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=gTuDidOvDWSTCGG6oiJd1VVA0CkIns2vlQYg45yPlsfU3R7eLFi4b37+oU0gDAS8Um39lNMZF5jW8rOjACc2OQWv0W/ztFjyUmjz/g/4TRr/spE/l99mBWtQ0dAhspsA/irak1C4RVXqvDuybSJkrdHH09sanCFApmmmRKPD/HI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=OMZ1a/6L; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="OMZ1a/6L" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 47NLsakj001381; Fri, 23 Aug 2024 16:54:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1724450076; bh=cEWNIRUzHtIaxI9fuJhOFnL1nhF5wnfExxcbBlbemPU=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=OMZ1a/6L7BuS6uID2d8z8T/EfnKU/i1fBik1w3nSDadfhVCdlf8mxc+HaE84MNLII 2cYyOzx12EJOWy9TMcpZLVe/px3/LqXiblEaH46RfCRRQCab+mJ5GeehA0Xfj/C+Rt slqCO2kfYBVNPimyQLbq1efUGL72YnCBcyOJYF8k= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 47NLsaPD058883 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 23 Aug 2024 16:54:36 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 23 Aug 2024 16:54:35 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 23 Aug 2024 16:54:35 -0500 Received: from localhost (bb.dhcp.ti.com [128.247.81.12]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 47NLsast123812; Fri, 23 Aug 2024 16:54:36 -0500 From: Bryan Brattlof Date: Fri, 23 Aug 2024 16:54:30 -0500 Subject: [PATCH v2 3/4] arm64: dts: ti: k3-am62p: add opp frequencies Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240823-opp-v2-3-e2f67b37c299@ti.com> References: <20240823-opp-v2-0-e2f67b37c299@ti.com> In-Reply-To: <20240823-opp-v2-0-e2f67b37c299@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Bryan Brattlof X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3687; i=bb@ti.com; h=from:subject:message-id; bh=G3IAVHLyG7E87LHtcgIvTkH6X5CEXq/IcP/RA6DZXUk=; b=owNCWmg5MUFZJlNZBqpeLQAAa3///rZtf79v7M3/4/WXv35bt7Wz/HTtal7Peqn+1ff+5v+wA RsYHaj1GgNAA0AAAAAAaAHpDQDQ0Ggeo0HqAaMgB6jQyADQ00HqZPTRMmNHqRA0AA9QBpoANDQ0 GgBoHqADQAaaaNHqeoaD1AAN6UA9R+lGmgAPUPU9Ro0ND1ABkh6gM1BoaaYTQyaGmmRkMJkAMmm QGJkBk0wjI0YRggAAMQGIAAAAAEETGobmKwQQuzvCkSrkhFvQIU98twqwVJAcQbLaUSiYJFOkNu ICpGl5OZAQASWi/6fRRsJoTKAjVKIxPcYDUdzxiphW8yMI4S5tKzMh3UtQmq1IhVyy4Dkaockpi z8JRB2rD1dqHibgCGyz8Shk40KAAUruruyTJ2oXLyOGewfj3IxuyLRHsBwalGae+WNNBY+d/BEN D6lxHGxbesBH2KUs/arF88gY1J7KVzIAp1n0CdYn1YIsMCH2gVioUk8BN27SJax+djlV+P3Gjwo kodehhkEUW2YGwqwpQ6rC89cR8G8UeZOPyZOZQqSeE9o2zT3cK5AMVSKYKe61o8RL+Gtuzi8pmE oP3i4JmkMsXxLyAVMpVlddTcIcxkIGFnjRacZIQW159cMCWea0pO5rNm4VUQdt14D/nakA33H+L uSKcKEgDVS8Wg== X-Developer-Key: i=bb@ti.com; a=openpgp; fpr=D3D177E40A38DF4D1853FEEF41B90D5D71D56CE0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 ONe power management technique available to the Cortex-A53s is their ability to dynamically scale their frequency across the device's Operating Performance Points (OPP) The OPPs available for the Cortex-A53s on the AM62Px can vary based on the silicon variant used. The SoC variant is encoded into the WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register which is used to limit the OPP entries the SoC supports. A table of all these variants can be found in its data sheet[0] for the AM62Px processor family. Add the OPP table into the SoC's ftdi file along with the syscon node to describe the WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register to detect the SoC variant. Signed-off-by: Bryan Brattlof --- .../boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi | 5 +++ arch/arm64/boot/dts/ti/k3-am62p5.dtsi | 47 ++++++++++++++++++= ++++ 2 files changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi b/arc= h/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi index 315d0092e7366..6f32135f00a55 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi @@ -20,6 +20,11 @@ chipid: chipid@14 { bootph-all; }; =20 + opp_efuse_table: syscon@18 { + compatible =3D "ti,am62-opp-efuse-table", "syscon"; + reg =3D <0x18 0x4>; + }; + cpsw_mac_syscon: ethernet-mac-syscon@200 { compatible =3D "ti,am62p-cpsw-mac-efuse", "syscon"; reg =3D <0x200 0x8>; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi b/arch/arm64/boot/dts/ti= /k3-am62p5.dtsi index 41f479dca4555..140587d02e88e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi @@ -47,6 +47,7 @@ cpu0: cpu@0 { d-cache-line-size =3D <64>; d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; + operating-points-v2 =3D <&a53_opp_table>; clocks =3D <&k3_clks 135 0>; }; =20 @@ -62,6 +63,7 @@ cpu1: cpu@1 { d-cache-line-size =3D <64>; d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; + operating-points-v2 =3D <&a53_opp_table>; clocks =3D <&k3_clks 136 0>; }; =20 @@ -77,6 +79,7 @@ cpu2: cpu@2 { d-cache-line-size =3D <64>; d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; + operating-points-v2 =3D <&a53_opp_table>; clocks =3D <&k3_clks 137 0>; }; =20 @@ -92,10 +95,54 @@ cpu3: cpu@3 { d-cache-line-size =3D <64>; d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; + operating-points-v2 =3D <&a53_opp_table>; clocks =3D <&k3_clks 138 0>; }; }; =20 + a53_opp_table: opp-table { + compatible =3D "operating-points-v2-ti-cpu"; + opp-shared; + syscon =3D <&opp_efuse_table>; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + opp-supported-hw =3D <0x01 0x0007>; + clock-latency-ns =3D <6000000>; + }; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + opp-supported-hw =3D <0x01 0x0007>; + clock-latency-ns =3D <6000000>; + }; + + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + opp-supported-hw =3D <0x01 0x0007>; + clock-latency-ns =3D <6000000>; + }; + + opp-800000000 { + opp-hz =3D /bits/ 64 <800000000>; + opp-supported-hw =3D <0x01 0x0007>; + clock-latency-ns =3D <6000000>; + }; + + opp-1000000000 { + opp-hz =3D /bits/ 64 <1000000000>; + opp-supported-hw =3D <0x01 0x0006>; + clock-latency-ns =3D <6000000>; + }; + + opp-1250000000 { + opp-hz =3D /bits/ 64 <1250000000>; + opp-supported-hw =3D <0x01 0x0004>; + clock-latency-ns =3D <6000000>; + opp-suspend; + }; + }; + l2_0: l2-cache0 { compatible =3D "cache"; cache-unified; --=20 2.45.2