From nobody Fri Sep 12 07:49:16 2025 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F21617C7DC; Thu, 22 Aug 2024 09:30:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724319008; cv=none; b=PwHyzszxjM8bYW42OekGjFX+0RdRKYa2BabbHYfcOn54GWE6sCAgNUIQ5WJKYWgGsU03KBs7cB0KWeo6jvlZnu7csZdupHp5xJVfdOlEg5WX3pRXe5GvBr0ZrxCdWQUAuXy/boliUFdD8qeKhrKaJwn/pmqD74zD2hxx5jq3a5Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724319008; c=relaxed/simple; bh=NKAjSJOr1O1+lYKx8SdVpDFqGJTvAAUc/0naBzjxrNs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=iT4GFpgZbVue9JLbm+mZGeqrQIAqTQ8qxxG4rqvNxSVFk+9A6SgVuQbQHREpTXk/sjTSOyTNyAcOTncCzTGSCIAaHwj8H1TQajgHqX1UTxLspJZHq5A/Nf0h/1KuWlddTTZLkZNgQ9nGWkkorqRT3GQfD1XVyAMMSIaTkwuaZt8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=EUOc0/Ed; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="EUOc0/Ed" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 47M9Tul0082800; Thu, 22 Aug 2024 04:29:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1724318996; bh=2yq9EdVFU1wiVZsxsN1yRfuuU6wcY+sxCt8DmlG08Bo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=EUOc0/EdjwXh9S4FS7A1NHHj4vP8SNY1zRJp7YdboqtwTyob4B+Obti4Zj3bWqpPk g5AskfAiDGF2l9r5D/KTXi0OEGSvSN+F9E4xGRY1Wm16kEV4YQxhMUHw4lNYAJqDvR paN8U2JO7j8E2FWXclX2umB+EEd+sny5CMYt/Cx4= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 47M9TuXq010794 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 22 Aug 2024 04:29:56 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 22 Aug 2024 04:29:56 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 22 Aug 2024 04:29:56 -0500 Received: from localhost ([10.249.48.175]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 47M9TubJ044832; Thu, 22 Aug 2024 04:29:56 -0500 From: Hari Nagalla To: , , , , , , , CC: , , Subject: [PATCH v5 4/4] arm64: dts: ti: k3-am62a7-sk: Enable ipc with Remoteproc nodes Date: Thu, 22 Aug 2024 04:29:55 -0500 Message-ID: <20240822092955.22037-5-hnagalla@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240822092955.22037-1-hnagalla@ti.com> References: <20240822092955.22037-1-hnagalla@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Devarsh Thakkar Reserve memory for Remoteproc IPC and bind the mailbox assignments for each Remoteproc. Two memory regions are reserved for each remote processor. The first region of 1MB of memory is used for Vring shared buffers and the second region is used as external memory to the remote processor, resource table and as tracebuffer. Signed-off-by: Devarsh Thakkar Signed-off-by: Hari Nagalla --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 71 +++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62a7-sk.dts index 67faf46d7a35..c9c504626b14 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -61,11 +61,41 @@ secure_ddr: optee@9e800000 { no-map; }; =20 + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c800000 0x00 0x100000>; + no-map; + }; + wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9c900000 0x00 0x01e00000>; no-map; }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b900000 0x00 0x0f00000>; + no-map; + }; + + c7x_0_dma_memory_region: c7x-dma-memory@99800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x99800000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: c7x-memory@99900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x99900000 0x00 0x01f00000>; + no-map; + }; }; =20 vmain_pd: regulator-0 { @@ -728,3 +758,44 @@ dpi1_out: endpoint { }; }; }; + +&mailbox0_cluster0 { + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster2 { + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&c7x_0 { + mboxes =3D <&mailbox0_cluster1 &mbox_c7x_0>; + memory-region =3D <&c7x_0_dma_memory_region>, + <&c7x_0_memory_region>; + status =3D "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; + memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster2 &mbox_mcu_r5_0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + status =3D "okay"; +}; --=20 2.34.1