From nobody Sun Feb 8 11:21:20 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8430616A94F; Wed, 21 Aug 2024 23:36:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724283381; cv=none; b=X7leYKLR3T8S863DE9o+uuDFIpQe5I3085fjvtJ9m5Ydjuzb/Nb29DELZX9k2JbF6yzL9lpv2e2C85f21DsfiXAsfdE8Q1rVLIOpTrol9aazIBaJ5ODxp6WuUqpSHCJbgaG8iZouWBlj0T+cYG09RvWKlgKclUVPvjWB0LRvt80= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724283381; c=relaxed/simple; bh=TnLcZV5j0h1vfwLf7V+sLcnJs4449D1TH0HuTBuSxFY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fKt20TFOzJmBKty8IX92j09zXVi3enXIeKR6GpBO2pBdAX+BO3zzYr8m1RhhhZOokauvu7NFlQoScZrbb4w6UBTc9U+CeGQz+Y6Z5Gj1Oqn7/wLn+0EvAB58WHr+bf4D5AGAl8DYyHSULOc1wf5LsQt+ut9sQ+YNz7U/DddJbuI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=UVJODIBk; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UVJODIBk" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2DBC0C32782; Wed, 21 Aug 2024 23:36:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724283381; bh=TnLcZV5j0h1vfwLf7V+sLcnJs4449D1TH0HuTBuSxFY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=UVJODIBkPa2yzzOUczJ87OFjHeeEH3ykt9CBt7yjiV4HZYE5kvEx26ie2f9J75OUg ThXNgMfoHS7mdPzOmzkZGPY8Lo/VAEQdAIBMan1I9NcdtDPdC4hxtg5F14hJL47pJC BrBWMwsjc2wGJNt5+IF/MKpI/hBRJq0FApyf49L8mn0SbIBElWTgyKdX6Vqhe4n+rt gsNQFRQVBMTYTR2RyslAaCrlQBNmuGQrsw5AxH0O6p5iZeCnQ7ZxTlPNccy5aC6erg ZgEL6Pr28BareoygcSb0dZnI/LkeXtCAlqw5X+2oqdsYQo78sInWDMbRoZRi6dSXCe X11aUKnWCkePA== From: Mark Brown Date: Thu, 22 Aug 2024 00:35:36 +0100 Subject: [PATCH v2 1/3] KVM: arm64: Define helper for EL2 registers with custom visibility Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240822-kvm-arm64-hide-pie-regs-v2-1-376624fa829c@kernel.org> References: <20240822-kvm-arm64-hide-pie-regs-v2-0-376624fa829c@kernel.org> In-Reply-To: <20240822-kvm-arm64-hide-pie-regs-v2-0-376624fa829c@kernel.org> To: Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Joey Gouly Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, Mark Brown , 20240813144738.2048302-1-maz@kernel.org X-Mailer: b4 0.15-dev-37811 X-Developer-Signature: v=1; a=openpgp-sha256; l=1399; i=broonie@kernel.org; h=from:subject:message-id; bh=TnLcZV5j0h1vfwLf7V+sLcnJs4449D1TH0HuTBuSxFY=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBmxnnp/eE7jfejNCJhPTNlB8GBsgUEO1dh38EUFkDi 7nBBSjSJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZsZ56QAKCRAk1otyXVSH0DiTB/ 9XkFXBeTHJFPIz0WRf13WK1WV5XrzrlUYRwxzkALiU6IEwF6/lfutvjFO6yGScRYuAsjHcXbTNdrDW 3iSSUULIKNAAmnzc8CMe8cGCDJCexf0uuXVKeiijGCpBI+y+u0L9SUckx7e0iE6oU03cBoqYSWQDst VUM/WL4ChuK4zB3cR7uZnHY/GYZGd30WxU4aeo82V6S78S5UJqZ9UppAlJDJ3eADeFTojthIOTzMWq 4y1ibnm+17XUpCSVsZolSJB9cK/AdQkTEDt1iOKWHuoBKKCK+A4SU7RNcWXGgVqk8HfXEjwtCKHlWm fmedslXbWsubOhmpAac9L+gDeYD4wz X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB In preparation for adding more visibility filtering for EL2 registers add a helper macro like EL2_REG() which allows specification of a custom visibility operation. Signed-off-by: Mark Brown --- arch/arm64/kvm/sys_regs.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index d0b4509e59cb..1af15140e067 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2136,6 +2136,15 @@ static bool bad_redir_trap(struct kvm_vcpu *vcpu, .val =3D v, \ } =20 +#define EL2_REG_FILTERED(name, acc, rst, v, filter) { \ + SYS_DESC(SYS_##name), \ + .access =3D acc, \ + .reset =3D rst, \ + .reg =3D name, \ + .visibility =3D filter, \ + .val =3D v, \ +} + #define EL2_REG_VNCR(name, rst, v) EL2_REG(name, bad_vncr_trap, rst, v) #define EL2_REG_REDIR(name, rst, v) EL2_REG(name, bad_redir_trap, rst, v) =20 @@ -2803,8 +2812,8 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { EL2_REG_VNCR(HFGITR_EL2, reset_val, 0), EL2_REG_VNCR(HACR_EL2, reset_val, 0), =20 - { SYS_DESC(SYS_ZCR_EL2), .access =3D access_zcr_el2, .reset =3D reset_val, - .visibility =3D sve_el2_visibility, .reg =3D ZCR_EL2 }, + EL2_REG_FILTERED(ZCR_EL2, access_zcr_el2, reset_val, 0, + sve_el2_visibility), =20 EL2_REG_VNCR(HCRX_EL2, reset_val, 0), =20 --=20 2.39.2 From nobody Sun Feb 8 11:21:20 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 442EC16A94F; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Dq2tt++t" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BF502C32781; Wed, 21 Aug 2024 23:36:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724283386; bh=b9JzN3spvWcKQGpRCCgrRJFy7/vr27MdGqrdOp6NEms=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Dq2tt++tWUppxeQc+fnyL3Jb+OUgXEToC1M4G/g8sM4R/emFtqJP45Ap8BWJIxYR0 DcWvsR5C4Bw4nA+OIZV440sH537D9LjvyMEQxnjUvbqg1bkrMNeE3A+MF4Iwh1V3LO niikM4IQHKurNhSf0H97WGMVBC2WfQD6a//yQO0SQ5khGZSqueePLxk1Io61gTP0E+ QgTGlp2zm6YXWgUJ9lCNjUFFUoHEJjVF+CdOiueTZwsS1glYacN+quYTYmuWwdSoGB JCQOcH4umwOgPhL+lM7AOrTzcSSClxMdGWUiOJCIaOYYi/lke0H8A70OG6NR1Pp0uw vMgi/oeb8qtyg== From: Mark Brown Date: Thu, 22 Aug 2024 00:35:37 +0100 Subject: [PATCH v2 2/3] KVM: arm64: Hide TCR2_EL1 from userspace when disabled for guests Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240822-kvm-arm64-hide-pie-regs-v2-2-376624fa829c@kernel.org> References: <20240822-kvm-arm64-hide-pie-regs-v2-0-376624fa829c@kernel.org> In-Reply-To: <20240822-kvm-arm64-hide-pie-regs-v2-0-376624fa829c@kernel.org> To: Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Joey Gouly Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, Mark Brown , 20240813144738.2048302-1-maz@kernel.org X-Mailer: b4 0.15-dev-37811 X-Developer-Signature: v=1; a=openpgp-sha256; l=3081; i=broonie@kernel.org; h=from:subject:message-id; bh=b9JzN3spvWcKQGpRCCgrRJFy7/vr27MdGqrdOp6NEms=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBmxnnqCSwLUG2jEupZw0pru27MOrYtdiLVk5Ppo6LW 61ok4LiJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZsZ56gAKCRAk1otyXVSH0O7JB/ 4lldS+6iSSLUcMtVy4BnN+HyPylNvRhL2FI795oVu72JrMwQ218IadFn7hHe7Xv2KPgF3A7fdUuYkg yB5BtsCRnrpybvmwG+SIxBy8GkvUxBkrSUBqQOPOZKLHtV5GCBbMAtGdhquPaCL1sOBYz2/BXjWOUo otuR0T9r5u3luNGXxVjleuyKVDkn+Ibd1caM0mydZEh58I+UN9vCDheNcoDSq7sfWFu0UGsRXxlUHK OKHoazQyunC/N1hQ6kRnKTeRHST8uSozu0Rd+xGyPfyke5pjfx7aBz9JaQrk1x8FNpwQqWSb8CE8oK 9jvT8SYTym5978W6lSJmGDX91jYfHk X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB When the guest does not support FEAT_TCR2 we should not allow any access to it in order to ensure that we do not create spurious issues with guest migration. Add a visibility operation for it. Fixes: fbff56068232 ("KVM: arm64: Save/restore TCR2_EL1") Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_host.h | 3 +++ arch/arm64/kvm/sys_regs.c | 29 ++++++++++++++++++++++++++--- 2 files changed, 29 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index ab4c675b491d..7889e5f4009f 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -1476,4 +1476,7 @@ void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 = val); (pa + pi + pa3) =3D=3D 1; \ }) =20 +#define kvm_has_tcr2(k) \ + (kvm_has_feat((k), ID_AA64MMFR3_EL1, TCRX, IMP)) + #endif /* __ARM64_KVM_HOST_H__ */ diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 1af15140e067..6d5f43781042 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2319,6 +2319,27 @@ static bool access_zcr_el2(struct kvm_vcpu *vcpu, return true; } =20 +static unsigned int tcr2_visibility(const struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd) +{ + if (kvm_has_tcr2(vcpu->kvm)) + return 0; + + return REG_HIDDEN; +} + +static unsigned int tcr2_el2_visibility(const struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd) +{ + unsigned int r; + + r =3D el2_visibility(vcpu, rd); + if (r) + return r; + + return tcr2_visibility(vcpu, rd); +} + /* * Architected system registers. * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 @@ -2503,7 +2524,8 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, - { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0 }, + { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0, + .visibility =3D tcr2_visibility }, =20 PTRAUTH_KEY(APIA), PTRAUTH_KEY(APIB), @@ -2820,7 +2842,8 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { EL2_REG(TTBR0_EL2, access_rw, reset_val, 0), EL2_REG(TTBR1_EL2, access_rw, reset_val, 0), EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1), - EL2_REG(TCR2_EL2, access_tcr2_el2, reset_val, TCR2_EL2_RES1), + EL2_REG_FILTERED(TCR2_EL2, access_tcr2_el2, reset_val, TCR2_EL2_RES1, + tcr2_el2_visibility), EL2_REG_VNCR(VTTBR_EL2, reset_val, 0), EL2_REG_VNCR(VTCR_EL2, reset_val, 0), =20 @@ -4626,7 +4649,7 @@ void kvm_calculate_traps(struct kvm_vcpu *vcpu) if (kvm_has_feat(kvm, ID_AA64ISAR2_EL1, MOPS, IMP)) vcpu->arch.hcrx_el2 |=3D (HCRX_EL2_MSCEn | HCRX_EL2_MCE2); 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a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB When the guest does not support S1PIE we should not allow any access to the system registers it adds in order to ensure that we do not create spurious issues with guest migration. Add a visibility operation for these registers. Fixes: 86f9de9db178 ("KVM: arm64: Save/restore PIE registers") Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_host.h | 3 +++ arch/arm64/kvm/sys_regs.c | 35 ++++++++++++++++++++++++++++++----- 2 files changed, 33 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 7889e5f4009f..fd161d41df52 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -1479,4 +1479,7 @@ void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 = val); #define kvm_has_tcr2(k) \ (kvm_has_feat((k), ID_AA64MMFR3_EL1, TCRX, IMP)) =20 +#define kvm_has_s1pie(k) \ + (kvm_has_feat((k), ID_AA64MMFR3_EL1, S1PIE, IMP)) + #endif /* __ARM64_KVM_HOST_H__ */ diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 6d5f43781042..3824f6d13bf6 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2340,6 +2340,27 @@ static unsigned int tcr2_el2_visibility(const struct= kvm_vcpu *vcpu, return tcr2_visibility(vcpu, rd); } =20 +static unsigned int s1pie_visibility(const struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd) +{ + if (kvm_has_s1pie(vcpu->kvm)) + return 0; + + return REG_HIDDEN; +} + +static unsigned int s1pie_el2_visibility(const struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd) +{ + unsigned int r; + + r =3D el2_visibility(vcpu, rd); + if (r) + return r; + + return s1pie_visibility(vcpu, rd); +} + /* * Architected system registers. * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 @@ -2577,8 +2598,10 @@ static const struct sys_reg_desc sys_reg_descs[] =3D= { { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, =20 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, - { SYS_DESC(SYS_PIRE0_EL1), NULL, reset_unknown, PIRE0_EL1 }, - { SYS_DESC(SYS_PIR_EL1), NULL, reset_unknown, PIR_EL1 }, + { SYS_DESC(SYS_PIRE0_EL1), NULL, reset_unknown, PIRE0_EL1, + .visibility =3D s1pie_visibility }, + { SYS_DESC(SYS_PIR_EL1), NULL, reset_unknown, PIR_EL1, + .visibility =3D s1pie_visibility }, { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, =20 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, @@ -2875,8 +2898,10 @@ static const struct sys_reg_desc sys_reg_descs[] =3D= { EL2_REG(HPFAR_EL2, access_rw, reset_val, 0), =20 EL2_REG(MAIR_EL2, access_rw, reset_val, 0), - EL2_REG(PIRE0_EL2, check_s1pie_access_rw, reset_val, 0), - EL2_REG(PIR_EL2, check_s1pie_access_rw, reset_val, 0), + EL2_REG_FILTERED(PIRE0_EL2, check_s1pie_access_rw, reset_val, 0, + s1pie_el2_visibility), + EL2_REG_FILTERED(PIR_EL2, check_s1pie_access_rw, reset_val, 0, + s1pie_el2_visibility), EL2_REG(AMAIR_EL2, access_rw, reset_val, 0), =20 EL2_REG(VBAR_EL2, access_rw, reset_val, 0), @@ -4691,7 +4716,7 @@ void kvm_calculate_traps(struct kvm_vcpu *vcpu) HFGITR_EL2_TLBIRVAAE1OS | HFGITR_EL2_TLBIRVAE1OS); =20 - if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S1PIE, IMP)) + if (!kvm_has_s1pie(kvm)) kvm->arch.fgu[HFGxTR_GROUP] |=3D (HFGxTR_EL2_nPIRE0_EL1 | HFGxTR_EL2_nPIR_EL1); =20 --=20 2.39.2