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a=openssh; fpr=SHA256:LOxhPHcL6HLuSaOVHuI2Yq7hvD2blbngN1ohWi2rJOw AD4630-24 and AD4630-16 are 2 channels ADCs. Both channels are interleaved bit per bit on SDO line. Signed-off-by: Esteban Blanc --- drivers/iio/adc/ad4030.c | 197 +++++++++++++++++++++++++++++++++++++++++--= ---- 1 file changed, 173 insertions(+), 24 deletions(-) diff --git a/drivers/iio/adc/ad4030.c b/drivers/iio/adc/ad4030.c index e1e1dbf0565c..dbba5287b630 100644 --- a/drivers/iio/adc/ad4030.c +++ b/drivers/iio/adc/ad4030.c @@ -32,6 +32,8 @@ #define AD4030_REG_PRODUCT_ID_H 0x05 #define AD4030_REG_CHIP_GRADE 0x06 #define AD4030_REG_CHIP_GRADE_AD4030_24_GRADE 0x10 +#define AD4030_REG_CHIP_GRADE_AD4630_16_GRADE 0x03 +#define AD4030_REG_CHIP_GRADE_AD4630_24_GRADE 0x00 #define AD4030_REG_CHIP_GRADE_MASK_CHIP_GRADE GENMASK(7, 3) #define AD4030_REG_SCRATCH_PAD 0x0A #define AD4030_REG_SPI_REVISION 0x0B @@ -159,10 +161,14 @@ struct ad4030_state { struct { union { u8 raw[AD4030_MAXIMUM_RX_BUFFER_SIZE]; - struct { - s32 val; - u32 common; - } __packed buffered[AD4030_MAX_HARDWARE_CHANNEL_NB]; + union { + s32 diff[AD4030_MAX_HARDWARE_CHANNEL_NB]; + struct { + s32 diff; + u32 common; + } __packed + buffered_common[AD4030_MAX_HARDWARE_CHANNEL_NB]; + }; }; } rx_data __aligned(IIO_DMA_MINALIGN); }; @@ -171,7 +177,7 @@ struct ad4030_state { .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), \ .type =3D IIO_VOLTAGE, \ .indexed =3D 1, \ - .channel =3D _idx * 2 + 2, \ + .channel =3D _idx * 3 + 2, \ .scan_index =3D _idx * 2 + 1, \ .extend_name =3D "Channel" #_idx " common byte part", \ .scan_type =3D { \ @@ -194,8 +200,8 @@ struct ad4030_state { BIT(IIO_CHAN_INFO_CALIBSCALE), \ .type =3D IIO_VOLTAGE, \ .indexed =3D 1, \ - .channel =3D _idx * 2, \ - .channel2 =3D _idx * 2 + 1, \ + .channel =3D _idx * 3, \ + .channel2 =3D _idx * 3 + 1, \ .scan_index =3D _idx * 2, \ .extend_name =3D "Channel" #_idx " differential part", \ .differential =3D true, \ @@ -412,7 +418,7 @@ static int ad4030_set_avg_frame_len(struct iio_dev *dev= , unsigned int avg_len) static bool ad4030_is_common_byte_asked(struct ad4030_state *st, unsigned int mask) { - /* Common byte channel is after the "real" differential sample channel */ + /* Common byte channels are after each differential channel */ return mask & AD4030_COMMON_BYTE_CHANNELS_FILTER; } =20 @@ -420,18 +426,69 @@ static int ad4030_set_mode(struct iio_dev *indio_dev,= unsigned long mask) { struct ad4030_state *st =3D iio_priv(indio_dev); =20 - if (st->avg_len) + if (st->avg_len) { st->mode =3D AD4030_OUT_DATA_MD_30_AVERAGED_DIFF; - else if (ad4030_is_common_byte_asked(st, mask)) - st->mode =3D AD4030_OUT_DATA_MD_24_DIFF_8_COM; - else + } else if (ad4030_is_common_byte_asked(st, mask)) { + switch (st->chip->precision_bits) { + case 16: + st->mode =3D AD4030_OUT_DATA_MD_16_DIFF_8_COM; + break; + + case 24: + st->mode =3D AD4030_OUT_DATA_MD_24_DIFF_8_COM; + break; + + default: + return -EINVAL; + } + } else { st->mode =3D AD4030_OUT_DATA_MD_24_DIFF; + } =20 return regmap_update_bits(st->regmap, AD4030_REG_MODES, AD4030_REG_MODES_MASK_OUT_DATA_MODE, st->mode); } =20 +/* + * @brief Descramble 2 32bits numbers out of a 64bits. The bits are interl= eaved: + * 1 bit for first number, 1 bit for the second, and so on... + */ +static void ad4030_extract_interleaved(u8 *src, u32 *ch0, u32 *ch1) +{ + u8 h0, h1, l0, l1; + u32 out0, out1; + u8 *out0_raw =3D (u8 *)&out0; + u8 *out1_raw =3D (u8 *)&out1; + + for (int i =3D 0; i < 4; i++) { + h0 =3D src[i * 2]; + l1 =3D src[i * 2 + 1]; + h1 =3D h0 << 1; + l0 =3D l1 >> 1; + + h0 &=3D 0xAA; + l0 &=3D 0x55; + h1 &=3D 0xAA; + l1 &=3D 0x55; + + h0 =3D (h0 | h0 << 001) & 0xCC; + h1 =3D (h1 | h1 << 001) & 0xCC; + l0 =3D (l0 | l0 >> 001) & 0x33; + l1 =3D (l1 | l1 >> 001) & 0x33; + h0 =3D (h0 | h0 << 002) & 0xF0; + h1 =3D (h1 | h1 << 002) & 0xF0; + l0 =3D (l0 | l0 >> 002) & 0x0F; + l1 =3D (l1 | l1 >> 002) & 0x0F; + + out0_raw[i] =3D h0 | l0; + out1_raw[i] =3D h1 | l1; + } + + *ch0 =3D out0; + *ch1 =3D out1; +} + static int ad4030_conversion(struct ad4030_state *st, const struct iio_chan_spec *chan) { @@ -460,12 +517,21 @@ static int ad4030_conversion(struct ad4030_state *st, if (ret) return ret; =20 - if (st->mode !=3D AD4030_OUT_DATA_MD_24_DIFF_8_COM) + if (st->chip->num_channels =3D=3D 2) + ad4030_extract_interleaved(st->rx_data.raw, + &st->rx_data.diff[0], + &st->rx_data.diff[1]); + + if (st->mode !=3D AD4030_OUT_DATA_MD_16_DIFF_8_COM && + st->mode !=3D AD4030_OUT_DATA_MD_24_DIFF_8_COM) return 0; =20 byte_index =3D BITS_TO_BYTES(chan->scan_type.realbits); - for (i =3D 0; i < st->chip->num_channels; i++) - st->rx_data.buffered[i].common =3D ((u8 *)&st->rx_data.buffered[i].val)[= byte_index]; + /* Doing it backward to avoid overlap when reordering */ + for (i =3D st->chip->num_channels - 1; i > 0; i--) { + st->rx_data.buffered_common[i].diff =3D st->rx_data.diff[i]; + st->rx_data.buffered_common[i].common =3D ((u8 *)&st->rx_data.diff[i])[b= yte_index]; + } =20 return 0; } @@ -489,9 +555,9 @@ static int ad4030_single_conversion(struct iio_dev *ind= io_dev, goto out_error; =20 if (chan->channel % 2) - *val =3D st->rx_data.buffered[chan->channel / 2].common; + *val =3D st->rx_data.buffered_common[chan->channel / 2].common; else - *val =3D st->rx_data.buffered[chan->channel / 2].val; + *val =3D st->rx_data.diff[chan->channel / 2]; =20 out_error: ad4030_enter_config_mode(st); @@ -582,14 +648,17 @@ static int ad4030_read_raw(struct iio_dev *indio_dev, return IIO_VAL_FRACTIONAL_LOG2; =20 case IIO_CHAN_INFO_CALIBSCALE: - ret =3D ad4030_get_chan_gain(indio_dev, chan->channel, - val, val2); + ret =3D ad4030_get_chan_gain(indio_dev, + chan->scan_index / 2, + val, + val2); if (ret) return ret; return IIO_VAL_INT_PLUS_MICRO; =20 case IIO_CHAN_INFO_CALIBBIAS: - ret =3D ad4030_get_chan_offset(indio_dev, chan->channel, + ret =3D ad4030_get_chan_offset(indio_dev, + chan->scan_index / 2, val); if (ret) return ret; @@ -614,11 +683,14 @@ static int ad4030_write_raw(struct iio_dev *indio_dev, iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { switch (info) { case IIO_CHAN_INFO_CALIBSCALE: - return ad4030_set_chan_gain(indio_dev, chan->channel, - val, val2); + return ad4030_set_chan_gain(indio_dev, + chan->scan_index / 2, + val, + val2); =20 case IIO_CHAN_INFO_CALIBBIAS: - return ad4030_set_chan_offset(indio_dev, chan->channel, + return ad4030_set_chan_offset(indio_dev, + chan->scan_index / 2, val); =20 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: @@ -801,10 +873,24 @@ static int ad4030_detect_chip_info(const struct ad403= 0_state *st) =20 static int ad4030_config(struct ad4030_state *st) { + int ret; + u8 reg_modes; + st->offset_avail[0] =3D (int)BIT(st->chip->precision_bits - 1) * -1; st->offset_avail[1] =3D 1; st->offset_avail[2] =3D BIT(st->chip->precision_bits - 1) - 1; =20 + if (st->chip->num_channels > 1) + reg_modes =3D FIELD_PREP(AD4030_REG_MODES_MASK_LANE_MODE, + AD4030_LANE_MD_INTERLEAVED); + else + reg_modes =3D FIELD_PREP(AD4030_REG_MODES_MASK_LANE_MODE, + AD4030_LANE_MD_1_PER_CH); + + ret =3D regmap_write(st->regmap, AD4030_REG_MODES, reg_modes); + if (ret) + return ret; + if (st->vio_uv < AD4030_VIO_THRESHOLD_UV) return regmap_write(st->regmap, AD4030_REG_IO, AD4030_REG_IO_MASK_IO2X); @@ -891,8 +977,16 @@ static const unsigned long ad4030_channel_masks[] =3D { 0, }; =20 +static const unsigned long ad4630_channel_masks[] =3D { + /* Differential only */ + BIT(0) | BIT(2), + /* Differential with common byte */ + GENMASK(3, 0), + 0, +}; + static const struct iio_scan_type ad4030_24_scan_types[] =3D { - [AD4030_SCAN_TYPE_NORMAL] =3D { + [AD4030_OUT_DATA_MD_24_DIFF] =3D { .sign =3D 's', .storagebits =3D 32, .realbits =3D 24, @@ -908,6 +1002,23 @@ static const struct iio_scan_type ad4030_24_scan_type= s[] =3D { }, }; =20 +static const struct iio_scan_type ad4030_16_scan_types[] =3D { + [AD4030_SCAN_TYPE_NORMAL] =3D { + .sign =3D 's', + .storagebits =3D 32, + .realbits =3D 16, + .shift =3D 16, + .endianness =3D IIO_BE, + }, + [AD4030_SCAN_TYPE_AVG] =3D { + .sign =3D 's', + .storagebits =3D 32, + .realbits =3D 30, + .shift =3D 2, + .endianness =3D IIO_BE, + } +}; + static const struct ad4030_chip_info ad4030_24_chip_info =3D { .name =3D "ad4030-24", .available_masks =3D ad4030_channel_masks, @@ -923,14 +1034,52 @@ static const struct ad4030_chip_info ad4030_24_chip_= info =3D { .tcyc =3D AD4030_TCYC_ADJUSTED_NS, }; =20 +static const struct ad4030_chip_info ad4630_16_chip_info =3D { + .name =3D "ad4630-16", + .available_masks =3D ad4630_channel_masks, + .available_masks_len =3D ARRAY_SIZE(ad4630_channel_masks), + .channels =3D { + AD4030_CHAN_IN(0, ad4030_16_scan_types), + AD4030_CHAN_CMO(0), + AD4030_CHAN_IN(1, ad4030_16_scan_types), + AD4030_CHAN_CMO(1), + IIO_CHAN_SOFT_TIMESTAMP(4), + }, + .grade =3D AD4030_REG_CHIP_GRADE_AD4630_16_GRADE, + .precision_bits =3D 16, + .num_channels =3D 2, + .tcyc =3D AD4030_TCYC_ADJUSTED_NS, +}; + +static const struct ad4030_chip_info ad4630_24_chip_info =3D { + .name =3D "ad4630-24", + .available_masks =3D ad4630_channel_masks, + .available_masks_len =3D ARRAY_SIZE(ad4630_channel_masks), + .channels =3D { + AD4030_CHAN_IN(0, ad4030_24_scan_types), + AD4030_CHAN_CMO(0), + AD4030_CHAN_IN(1, ad4030_24_scan_types), + AD4030_CHAN_CMO(1), + IIO_CHAN_SOFT_TIMESTAMP(4), + }, + .grade =3D AD4030_REG_CHIP_GRADE_AD4630_24_GRADE, + .precision_bits =3D 24, + .num_channels =3D 2, + .tcyc =3D AD4030_TCYC_ADJUSTED_NS, +}; + static const struct spi_device_id ad4030_id_table[] =3D { { "ad4030-24", (kernel_ulong_t)&ad4030_24_chip_info }, + { "ad4630-16", (kernel_ulong_t)&ad4630_16_chip_info }, + { "ad4630-24", (kernel_ulong_t)&ad4630_24_chip_info }, {} }; MODULE_DEVICE_TABLE(spi, ad4030_id_table); =20 static const struct of_device_id ad4030_of_match[] =3D { { .compatible =3D "adi,ad4030-24", .data =3D &ad4030_24_chip_info }, + { .compatible =3D "adi,ad4630-16", .data =3D &ad4630_16_chip_info }, + { .compatible =3D "adi,ad4630-24", .data =3D &ad4630_24_chip_info }, {} }; MODULE_DEVICE_TABLE(of, ad4030_of_match); --=20 2.44.1