From nobody Fri Dec 19 19:00:45 2025 Received: from mail.thorsis.com (mail.thorsis.com [217.92.40.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F8CE1BAEC5 for ; Wed, 21 Aug 2024 11:00:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.92.40.78 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724238003; cv=none; b=JHb+oXyh58POTsfF4mtLMoVn8sFiLYkqEmyEuhHqVSJ9MooKdlSbbUB3+uAM7B35V9GoLRkXL0wO3jdtHF/Ceux3E5l0r9KAIlIMpb9I9wF0/gmd/2/zyqUuVUKSgdCWXCHusuIiKnkxm7fDK64xRRKWvH6T6gw0YmQNYw9b1qg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724238003; c=relaxed/simple; bh=1K56cFtxqRrqKL3dsbtsNJZdC6zpznB5RkaKOagcN9M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RKO7c6nYBNpHX/8yW3DwaxzmNul7dXMwxmz9XvnH4Xj72z+SmtDQILlWw+cVewkdEbf6EY1IUgpTuzXU/HUjEM+o5ZCu/8180Wo0c+2guwV2Lw5ACAfmBU9j2pC9GqBoXmQm+gh7p+hLu1CS4tW30V5P374pIgnZwp21oyOaMeU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com; spf=pass smtp.mailfrom=thorsis.com; dkim=pass (2048-bit key) header.d=thorsis.com header.i=@thorsis.com header.b=vBc/BFZP; arc=none smtp.client-ip=217.92.40.78 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=thorsis.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=thorsis.com header.i=@thorsis.com header.b="vBc/BFZP" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 1EFAA1483DF2; Wed, 21 Aug 2024 12:59:59 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=thorsis.com; s=dkim; t=1724237999; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=jovbb058QzzCeFDP4Da8Wb3JHly5Xy6YvCLwu8Ic6q4=; b=vBc/BFZPkHoTOZP55cWp8jIcwt2YXJwPdq0Zk3/yQHb06gka0w8sOFpxXT3RYBpDw73D7f IxKKLjFxrDTticjvnANOv6RIRKzqRqJpaDjZrL2Nq65z4K64/o5Q/azqfms4KPsCnSQECW pR6Y4w6MlJKoacR6z9p7hEEhwJulCg+/wDcYCB2Ayg8fehf5DYPGWx0+7GrW6MsQJ6Aw4D Zsan9FH9auUf3k/suXz2EDAoMI4G284/YeHGF9u4qiHunWMzDggWfJbCDNXqIIayEIGAoV PbWg+pxA5tkvoKw075F2xMN5E35BP8ML+unevBlaleYvWD11N1Z6q+YKkY6qLg== From: Alexander Dahl To: Claudiu Beznea Cc: Christian Melki , Srinivas Kandagatla , linux-arm-kernel@lists.infradead.org (moderated list:MICROCHIP OTPC DRIVER), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v1 11/12] nvmem: microchip-otpc: Enable main RC oscillator clock Date: Wed, 21 Aug 2024 12:59:42 +0200 Message-Id: <20240821105943.230281-12-ada@thorsis.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240821105943.230281-1-ada@thorsis.com> References: <20240821105943.230281-1-ada@thorsis.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Without enabling that clock, initializing the packet list leads to a read timeout on the first packet. According to SAM9X60 datasheet (DS60001579G) section "23.4 Product Dependencies" the clock must be enabled for reading and writing. Tested on sam9x60-curiosity board. Signed-off-by: Alexander Dahl --- drivers/nvmem/microchip-otpc.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/nvmem/microchip-otpc.c b/drivers/nvmem/microchip-otpc.c index a80535c3d162..047ca5ac6407 100644 --- a/drivers/nvmem/microchip-otpc.c +++ b/drivers/nvmem/microchip-otpc.c @@ -8,6 +8,7 @@ */ =20 #include +#include #include #include #include @@ -54,6 +55,7 @@ struct mchp_otpc { void __iomem *base; struct device *dev; + struct clk *clk; struct list_head packets; u32 npackets; }; @@ -272,6 +274,15 @@ static int mchp_otpc_probe(struct platform_device *pde= v) if (IS_ERR(otpc->base)) return PTR_ERR(otpc->base); =20 + // NOTE: Maybe make this optional, especially if sama7g5 testing + // shows the clock is not required there? + otpc->clk =3D devm_clk_get_enabled(&pdev->dev, "main_rc_osc"); + if (IS_ERR(otpc->clk)) { + dev_err(&pdev->dev, "Error (%ld) getting clock!\n", + PTR_ERR(otpc->clk)); + return PTR_ERR(otpc->clk); + } + reg =3D readl_relaxed(otpc->base + MCHP_OTPC_WPSR); if (reg) dev_warn(&pdev->dev, --=20 2.39.2