From nobody Sun Dec 14 12:12:40 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7222218C014; Tue, 20 Aug 2024 09:24:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724145871; cv=none; b=iG20ADYPEwJluTF2GQVxEVB5EFLEKvTEg5Gq7ZKOSWG2THTiysDmTyfU5kvfCTIURGfWMnfYgZ6cHKa7W01uNQv20VQNIn5hcBU0zTjtBVkmyjXwOS4V0+va2xNX8kVBKoY1NF2ObeBvaujqU+YWgVgIw6WTBHF1SFTghQ4GxIE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724145871; c=relaxed/simple; bh=iGj7qj63w6YFCj6Bt4ILro3u4D1lhAk1mwTyNcoKvak=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=tyADF01iH5JZawmwm72TXIJMctJSj6YFKzRGDQ1/HgNxMTsCwBcy8hR/GiNMhFZh+BVOgKuJ651Fg67Z/HLZ3Wa/OVYxKQt+bhWu3IvGUQv7Z/CEuVqH41R7Q/kljqw43sWoScpAru9Kv31cYjH6mqUo8Hg8c1x9iJ0xRjuIpbc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=IS6HhOkW; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="IS6HhOkW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724145870; x=1755681870; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iGj7qj63w6YFCj6Bt4ILro3u4D1lhAk1mwTyNcoKvak=; b=IS6HhOkWz+NUWIodMsK6qmk0rqm+lzoAa6UjctZRxI+KYWxWzZk7vn/6 wq7N7s01Klsz3qWLftNyRunu1KVAa//SHo4BdyT750hIn7aYAtI7UIL1g FeQANMiwy2AexK45okJZUXwIfhhFxqrUx8T9w9jLslH+so4+ZutTPRf/A srBzKpoK4qBITe4k3qub461fmckN7xwc71qNRCiVwpydXtumK16Na2VWM BGg6tOH6bB39yMrVqQHB4IK5iaLsiHh+XqlofAjvvXqw9Yul0migSu5qd s+yHS4FQeLMtlKpHgadJYcr+DQwrXRk+mkeG9Erdf3AgtfOlK1ggL2dra g==; X-CSE-ConnectionGUID: BAcMeHFYTRO8GVy1A4fYvA== X-CSE-MsgGUID: Bqz7xrqyQSC8uiEjRN1T9w== X-IronPort-AV: E=McAfee;i="6700,10204,11169"; a="22578406" X-IronPort-AV: E=Sophos;i="6.10,161,1719903600"; d="scan'208";a="22578406" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Aug 2024 02:24:30 -0700 X-CSE-ConnectionGUID: ktB26yIaTGKenjETphR+uw== X-CSE-MsgGUID: pqkAzJkMQE2mheNVJmNc1g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,161,1719903600"; d="scan'208";a="65495036" Received: from inlubt0246.iind.intel.com ([10.191.24.87]) by orviesa003.jf.intel.com with ESMTP; 20 Aug 2024 02:24:26 -0700 From: subramanian.mohan@intel.com To: linux-drivers-review@eclists.intel.com, tglx@linutronix.de, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: gregkh@linuxfoundation.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, pandith.n@intel.com, thejesh.reddy.t.r@intel.com Subject: [PATCH v11 1/3] pps: generators: Add PPS Generator TIO Driver Date: Tue, 20 Aug 2024 14:54:18 +0530 Message-Id: <20240820092420.9185-2-subramanian.mohan@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240820092420.9185-1-subramanian.mohan@intel.com> References: <20240820092420.9185-1-subramanian.mohan@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Subramanian Mohan The Intel Timed IO PPS generator driver outputs a PPS signal using dedicated hardware that is more accurate than software actuated PPS. The Timed IO hardware generates output events using the ART timer. The ART timer period varies based on platform type, but is less than 100 nanoseconds for all current platforms. Timed IO output accuracy is within 1 ART period. PPS output is enabled by writing '1' the 'enable' sysfs attribute. The driver uses hrtimers to schedule a wake-up 10 ms before each event (edge) target time. At wakeup, the driver converts the target time in terms of CLOCK_REALTIME to ART trigger time and writes this to the Timed IO hardware. The Timed IO hardware generates an event precisely at the requested system time without software involvement. Co-developed-by: Christopher Hall Signed-off-by: Christopher Hall Co-developed-by: Pandith N Signed-off-by: Pandith N Co-developed-by: Thejesh Reddy T R Signed-off-by: Thejesh Reddy T R Signed-off-by: Lakshmi Sowjanya D Reviewed-by: Eddie Dong Reviewed-by: Andy Shevchenko Acked-by: Rodolfo Giometti Signed-off-by: Subramanian Mohan --- drivers/pps/generators/Kconfig | 16 ++ drivers/pps/generators/Makefile | 1 + drivers/pps/generators/pps_gen_tio.c | 262 +++++++++++++++++++++++++++ 3 files changed, 279 insertions(+) create mode 100644 drivers/pps/generators/pps_gen_tio.c diff --git a/drivers/pps/generators/Kconfig b/drivers/pps/generators/Kconfig index d615e640fcad..0f090932336f 100644 --- a/drivers/pps/generators/Kconfig +++ b/drivers/pps/generators/Kconfig @@ -12,3 +12,19 @@ config PPS_GENERATOR_PARPORT If you say yes here you get support for a PPS signal generator which utilizes STROBE pin of a parallel port to send PPS signals. It uses parport abstraction layer and hrtimers to precisely control the signal. + +config PPS_GENERATOR_TIO + tristate "TIO PPS signal generator" + depends on X86 && CPU_SUP_INTEL + help + If you say yes here you get support for a PPS TIO signal generator + which generates a pulse at a prescribed time based on the system clock. + It uses time translation and hrtimers to precisely generate a pulse. + This hardware is present on 2019 and newer Intel CPUs. However, this + driver is not useful without adding highly specialized hardware outside + the Linux system to observe these pulses. + + To compile this driver as a module, choose M here: the module + will be called pps_gen_tio. + + If unsure, say N. diff --git a/drivers/pps/generators/Makefile b/drivers/pps/generators/Makef= ile index 2589fd0f2481..714e847ae193 100644 --- a/drivers/pps/generators/Makefile +++ b/drivers/pps/generators/Makefile @@ -4,5 +4,6 @@ # =20 obj-$(CONFIG_PPS_GENERATOR_PARPORT) +=3D pps_gen_parport.o +obj-$(CONFIG_PPS_GENERATOR_TIO) +=3D pps_gen_tio.o =20 ccflags-$(CONFIG_PPS_DEBUG) :=3D -DDEBUG diff --git a/drivers/pps/generators/pps_gen_tio.c b/drivers/pps/generators/= pps_gen_tio.c new file mode 100644 index 000000000000..ae5d351be479 --- /dev/null +++ b/drivers/pps/generators/pps_gen_tio.c @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel PPS signal Generator Driver + * + * Copyright (C) 2024 Intel Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define TIOCTL 0x00 +#define TIOCOMPV 0x10 +#define TIOEC 0x30 + +/* Control Register */ +#define TIOCTL_EN BIT(0) +#define TIOCTL_DIR BIT(1) +#define TIOCTL_EP GENMASK(3, 2) +#define TIOCTL_EP_RISING_EDGE FIELD_PREP(TIOCTL_EP, 0) +#define TIOCTL_EP_FALLING_EDGE FIELD_PREP(TIOCTL_EP, 1) +#define TIOCTL_EP_TOGGLE_EDGE FIELD_PREP(TIOCTL_EP, 2) + +#define SAFE_TIME_NS (10 * NSEC_PER_MSEC) /* Safety time to set hrtimer = early */ +#define MAGIC_CONST (NSEC_PER_SEC - SAFE_TIME_NS) +#define ART_HW_DELAY_CYCLES 2 + +struct pps_tio { + struct hrtimer timer; + struct device *dev; + spinlock_t lock; + struct attribute_group attrs; + void __iomem *base; + bool enabled; + u32 prev_count; +}; + +static inline u32 pps_tio_read(struct pps_tio *tio, u32 offset) +{ + return readl(tio->base + offset); +} + +static inline void pps_ctl_write(struct pps_tio *tio, u32 value) +{ + writel(value, tio->base + TIOCTL); +} + +/* For COMPV register, It's safer to write higher 32-bit followed by lower= 32-bit */ +static inline void pps_compv_write(struct pps_tio *tio, u64 value) +{ + hi_lo_writeq(value, tio->base + TIOCOMPV); +} + +static inline ktime_t first_event(struct pps_tio *tio) +{ + return ktime_set(ktime_get_real_seconds() + 1, MAGIC_CONST); +} + +static u32 pps_tio_disable(struct pps_tio *tio) +{ + u32 ctrl; + + ctrl =3D pps_tio_read(tio, TIOCTL); + pps_compv_write(tio, 0); + + ctrl &=3D ~TIOCTL_EN; + pps_ctl_write(tio, ctrl); + tio->enabled =3D false; + tio->prev_count =3D 0; + + return ctrl; +} + +static void pps_tio_enable(struct pps_tio *tio) +{ + u32 ctrl; + + ctrl =3D pps_tio_read(tio, TIOCTL); + ctrl |=3D TIOCTL_EN; + pps_ctl_write(tio, ctrl); + tio->enabled =3D true; +} + +static void pps_tio_direction_output(struct pps_tio *tio) +{ + u32 ctrl; + + ctrl =3D pps_tio_disable(tio); + + /* We enable the device, be sure that the 'compare' value is invalid */ + pps_compv_write(tio, 0); + + ctrl &=3D ~(TIOCTL_DIR | TIOCTL_EP); + ctrl |=3D TIOCTL_EP_TOGGLE_EDGE; + pps_ctl_write(tio, ctrl); + pps_tio_enable(tio); +} + +static bool pps_generate_next_pulse(struct pps_tio *tio, ktime_t expires) +{ + u64 art; + + if (!ktime_real_to_base_clock(expires, CSID_X86_ART, &art)) { + pps_tio_disable(tio); + return false; + } + + pps_compv_write(tio, art - ART_HW_DELAY_CYCLES); + return true; +} + +static enum hrtimer_restart hrtimer_callback(struct hrtimer *timer) +{ + struct pps_tio *tio =3D container_of(timer, struct pps_tio, timer); + ktime_t expires, now; + u32 event_count; + + guard(spinlock)(&tio->lock); + + /* Check if any event is missed. If an event is missed, TIO will be disab= led*/ + event_count =3D pps_tio_read(tio, TIOEC); + if (tio->prev_count && tio->prev_count =3D=3D event_count) + goto err; + tio->prev_count =3D event_count; + expires =3D hrtimer_get_expires(timer); + now =3D ktime_get_real(); + + if (now - expires >=3D SAFE_TIME_NS) + goto err; + + tio->enabled =3D pps_generate_next_pulse(tio, expires + SAFE_TIME_NS); + if (!tio->enabled) + return HRTIMER_NORESTART; + + hrtimer_forward(timer, now, NSEC_PER_SEC / 2); + return HRTIMER_RESTART; +err: + dev_err(tio->dev, "Event missed, Disabling Timed I/O"); + pps_tio_disable(tio); + return HRTIMER_NORESTART; +} + +static ssize_t enable_store(struct device *dev, struct device_attribute *a= ttr, const char *buf, + size_t count) +{ + struct pps_tio *tio =3D dev_get_drvdata(dev); + bool enable; + int err; + + if (!timekeeping_clocksource_has_base(CSID_X86_ART)) { + dev_err_once(dev, "PPS cannot be used as clock is not related to ART"); + return -ENODEV; + } + + err =3D kstrtobool(buf, &enable); + if (err) + return err; + + guard(spinlock_irqsave)(&tio->lock); + if (enable && !tio->enabled) { + pps_tio_direction_output(tio); + hrtimer_start(&tio->timer, first_event(tio), HRTIMER_MODE_ABS); + } else if (!enable && tio->enabled) { + hrtimer_cancel(&tio->timer); + pps_tio_disable(tio); + } + return count; +} + +static ssize_t enable_show(struct device *dev, struct device_attribute *de= vattr, char *buf) +{ + struct pps_tio *tio =3D dev_get_drvdata(dev); + + return sysfs_emit(buf, "%u\n", tio->enabled); +} +static DEVICE_ATTR_RW(enable); + +static struct attribute *pps_tio_attrs[] =3D { + &dev_attr_enable.attr, + NULL +}; +ATTRIBUTE_GROUPS(pps_tio); + +static int pps_gen_tio_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct pps_tio *tio; + + if (!(cpu_feature_enabled(X86_FEATURE_TSC_KNOWN_FREQ) && + cpu_feature_enabled(X86_FEATURE_ART))) { + dev_warn(dev, "TSC/ART is not enabled"); + return -ENODEV; + } + + tio =3D devm_kzalloc(dev, sizeof(*tio), GFP_KERNEL); + if (!tio) + return -ENOMEM; + + tio->dev =3D dev; + tio->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(tio->base)) + return PTR_ERR(tio->base); + + pps_tio_disable(tio); + hrtimer_init(&tio->timer, CLOCK_REALTIME, HRTIMER_MODE_ABS); + tio->timer.function =3D hrtimer_callback; + spin_lock_init(&tio->lock); + platform_set_drvdata(pdev, tio); + + return 0; +} + +static void pps_gen_tio_remove(struct platform_device *pdev) +{ + struct pps_tio *tio =3D platform_get_drvdata(pdev); + + hrtimer_cancel(&tio->timer); + pps_tio_disable(tio); +} + +static const struct acpi_device_id intel_pmc_tio_acpi_match[] =3D { + { "INTC1021" }, + { "INTC1022" }, + { "INTC1023" }, + { "INTC1024" }, + {} +}; +MODULE_DEVICE_TABLE(acpi, intel_pmc_tio_acpi_match); + +static struct platform_driver pps_gen_tio_driver =3D { + .probe =3D pps_gen_tio_probe, + .remove =3D pps_gen_tio_remove, + .driver =3D { + .name =3D "intel-pps-gen-tio", + .acpi_match_table =3D intel_pmc_tio_acpi_match, + .dev_groups =3D pps_tio_groups, + }, +}; +module_platform_driver(pps_gen_tio_driver); + +MODULE_AUTHOR("Lakshmi Sowjanya D "); +MODULE_AUTHOR("Christopher Hall "); +MODULE_AUTHOR("Pandith N "); +MODULE_AUTHOR("Thejesh Reddy T R "); +MODULE_DESCRIPTION("Intel PMC Time-Aware IO Generator Driver"); +MODULE_LICENSE("GPL"); --=20 2.35.3 From nobody Sun Dec 14 12:12:40 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44AD518C34F; Tue, 20 Aug 2024 09:24:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724145874; cv=none; b=HDyyV17i3rTkku3+PXSHBuVDZfqx61wHb2MQzNhTRbYUkCFlhL/7dbH1QLSA8dZJGMHviU1n8HVMmlkMHl5TVrOSKndsmF7fmN6pz+biTCAHlz2XmY/bYA9r7zCFyc2rKEWHrq97oFNIcnWtQ9w7sj6OcymFOFRtd4LjvLgWRgU= ARC-Message-Signature: i=1; a=rsa-sha256; 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d="scan'208";a="65495047" Received: from inlubt0246.iind.intel.com ([10.191.24.87]) by orviesa003.jf.intel.com with ESMTP; 20 Aug 2024 02:24:30 -0700 From: subramanian.mohan@intel.com To: linux-drivers-review@eclists.intel.com, tglx@linutronix.de, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: gregkh@linuxfoundation.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, pandith.n@intel.com, thejesh.reddy.t.r@intel.com Subject: [PATCH v11 2/3] Documentation: driver-api: pps: Add Intel Timed I/O PPS generator Date: Tue, 20 Aug 2024 14:54:19 +0530 Message-Id: <20240820092420.9185-3-subramanian.mohan@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240820092420.9185-1-subramanian.mohan@intel.com> References: <20240820092420.9185-1-subramanian.mohan@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Subramanian Mohan Add Intel Timed I/O PPS usage instructions. Co-developed-by: Pandith N Signed-off-by: Pandith N Signed-off-by: Lakshmi Sowjanya D Reviewed-by: Andy Shevchenko Acked-by: Rodolfo Giometti Signed-off-by: Subramanian Mohan --- Documentation/driver-api/pps.rst | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/driver-api/pps.rst b/Documentation/driver-api/pp= s.rst index 78dded03e5d8..75f7b094f963 100644 --- a/Documentation/driver-api/pps.rst +++ b/Documentation/driver-api/pps.rst @@ -246,3 +246,27 @@ delay between assert and clear edge as small as possib= le to reduce system latencies. But if it is too small slave won't be able to capture clear edge transition. The default of 30us should be good enough in most situations. The delay can be selected using 'delay' pps_gen_parport module parameter. + + +Intel Timed I/O PPS signal generator +------------------------------------ + +Intel Timed I/O is a high precision device, present on 2019 and newer Intel +CPUs, that can generate PPS signals. + +Timed I/O and system time are both driven by same hardware clock. The sign= al +is generated with a precision of ~20 nanoseconds. The generated PPS signal +is used to synchronize an external device with system clock. For example, +it can be used to share your clock with a device that receives PPS signal, +generated by Timed I/O device. There are dedicated Timed I/O pins to deliv= er +the PPS signal to an external device. + +Usage of Intel Timed I/O as PPS generator: + +Start generating PPS signal:: + + $echo 1 > /sys/devices/platform/INTCxxxx\:00/enable + +Stop generating PPS signal:: + + $echo 0 > /sys/devices/platform/INTCxxxx\:00/enable --=20 2.35.3 From nobody Sun Dec 14 12:12:40 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30EA618C91B; Tue, 20 Aug 2024 09:24:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724145878; cv=none; b=bYm/n56yTLI4LhN+V+ITg8I57Pq4TKVQezgN8yc8t4WzItaSGWz6flh9Yx+c1MO7I3Y1J+vcXsagBC/WcAlwu3g91zqB21uSDFGGmUidIudig1EmW3le+gnvpHkdX3Vd4qvFjRp3CAvna/fQ7Emu7r5ifpDeUKzAT1+yX+EJmas= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724145878; c=relaxed/simple; bh=M7u8dwEi2+oYVWiHViJ2HEDlciSMLJc87pWlx3bLL8Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=u58mOr7k0bQQJsgE55FiDnwJR5hjuE9I0VSdat67hL2712fQ5t4SmW8DpwdGU+sFuI3+8f99488X2DFXYjonhNEqsODaJA/oAOsG17BUXN4RWV9RyrXivM6xYV8o9WkPFD9/lYzbzXrLPek2SuzS/l2VARBB+ga9CchrIdVfxbM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ZkKHsFmG; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ZkKHsFmG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724145878; x=1755681878; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=M7u8dwEi2+oYVWiHViJ2HEDlciSMLJc87pWlx3bLL8Q=; b=ZkKHsFmG1mrH3Va0GO3H9tTWKAZbVnSyz4HZ/bvtRrAJ8237H665lm9T o+KXZEv7RgTzO50wPCZIBYO9zkhFmREHcKvcQswCoXXAnkbx+P6gmTsR1 VCy14S0YO4/kwBIAOuelyo031cMPiwi+jgpov4KMYi4yM4c26JOWkYp+n WH6shY5ZzEimxOIGnWmdX2GLHobS7VmQVT4ai2MD3R1C/nFqr5mPx4YiF cuh8Blcydq73SJGyjHhRhcb/nFgwkCEyH808n/pqzqgRuiyNmNrAyFi7t ddO4OcX3OLpOlzSWwMLP41J+im2ZU1U/1lBBY07fRLbMXc9a8zgJ65hyQ A==; X-CSE-ConnectionGUID: abcGutbORjO6HHnhU5eW9g== X-CSE-MsgGUID: +bQxRgiwQeWs98GLwKD05Q== X-IronPort-AV: E=McAfee;i="6700,10204,11169"; a="22578426" X-IronPort-AV: E=Sophos;i="6.10,161,1719903600"; d="scan'208";a="22578426" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Aug 2024 02:24:37 -0700 X-CSE-ConnectionGUID: NhJfld54QCCNPFsEbmBQbA== X-CSE-MsgGUID: HIbxi3B3SqW/wuDOYEFFvQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,161,1719903600"; d="scan'208";a="65495056" Received: from inlubt0246.iind.intel.com ([10.191.24.87]) by orviesa003.jf.intel.com with ESMTP; 20 Aug 2024 02:24:34 -0700 From: subramanian.mohan@intel.com To: linux-drivers-review@eclists.intel.com, tglx@linutronix.de, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: gregkh@linuxfoundation.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, pandith.n@intel.com, thejesh.reddy.t.r@intel.com Subject: [PATCH v11 3/3] ABI: pps: Add ABI documentation for Intel TIO Date: Tue, 20 Aug 2024 14:54:20 +0530 Message-Id: <20240820092420.9185-4-subramanian.mohan@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240820092420.9185-1-subramanian.mohan@intel.com> References: <20240820092420.9185-1-subramanian.mohan@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Subramanian Mohan Document sysfs interface for Intel Timed I/O PPS driver. Signed-off-by: Lakshmi Sowjanya D Acked-by: Christopher Hall Signed-off-by: Subramanian Mohan --- Documentation/ABI/testing/sysfs-platform-pps-tio | 8 ++++++++ MAINTAINERS | 1 + 2 files changed, 9 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-platform-pps-tio diff --git a/Documentation/ABI/testing/sysfs-platform-pps-tio b/Documentati= on/ABI/testing/sysfs-platform-pps-tio new file mode 100644 index 000000000000..8face1dc8010 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-platform-pps-tio @@ -0,0 +1,8 @@ +What: /sys/devices/platform/INTCxxxx/enable +Date: September 2024 +KernelVersion: 6.12 +Contact: Christopher Hall + Subramanian Mohan +Description: + (RW) Enable or disable PPS TIO generator output, read to + see the status of hardware (Enabled/Disabled). diff --git a/MAINTAINERS b/MAINTAINERS index f328373463b0..242d9784ee5d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18263,6 +18263,7 @@ M: Rodolfo Giometti L: linuxpps@ml.enneenne.com (subscribers-only) S: Maintained W: http://wiki.enneenne.com/index.php/LinuxPPS_support +F: Documentation/ABI/testing/sysfs-platform-pps-tio F: Documentation/ABI/testing/sysfs-pps F: Documentation/devicetree/bindings/pps/pps-gpio.yaml F: Documentation/driver-api/pps.rst --=20 2.35.3