From nobody Sat Feb 7 15:05:56 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA9F91BF58 for ; Tue, 20 Aug 2024 01:55:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724118936; cv=none; b=hjvelmtMc4l7JVPMNQmk/CLmI2OBd1w0tMbFsqstyM7JddBhAx6FN6605jf6OCQNSTIdDjVdb4/msIGvSrJ4lgBEaNOeFKwqOSjwQqjqqZXXF24sPxH6DZRE4+F4FqmY6y5Bug/6IIemA++YKMGxodS6YrFk4i8uiN1LwP05QNY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724118936; c=relaxed/simple; bh=fcvXFnZb2J9/BJD4GIRJxboaymwEMjVV+c4HK73tXzM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=sct+WtqFkIGyDXLcOUP2lMTQr/aAOB6J87Ol9m846LNWSjW1xykdqHDzO4doZ2MsVd0vCgFhtdN+I22UjA6gmRAT0pvscXx7kmLP0MY4i57VUuaxk8kSYwWOXH9/RTPG8BGLMv0s3shUVRvrBA4D/be19Kyo9RWi6WEiFmIhmjU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MehpYpiq; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MehpYpiq" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724118935; x=1755654935; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fcvXFnZb2J9/BJD4GIRJxboaymwEMjVV+c4HK73tXzM=; b=MehpYpiqSCe9GVaFeAnmhhhE7DPArbdwoa6R0t1oSfNa5M+iB7AFnQEj hGG8vxprBuaxyh3kJkggSBp68fkc4VLKQvIHg7X1ptbK3yVXD1GfyDxWu Wl7nbIIs/emQXjw7bxUv4aoD7lK1YFuyFSsFt0Wrfs4tjVx7VNT8S39I3 I8D7o0hX5e9gToHa/4A4nBHgEtclb+QSWvthsI9zcrkHBn/qcnKWwopMx Bqz8P3O4AGQMgpQUaQSHciJYo8CIZF6KLSShB3AhLgIKNsEIhKD8MPL6B JtSQwmg8k37gDb1ANu0uvCckv7cXpYSIn5CgFQC9D9T2TfXKkOnVHwWCZ w==; X-CSE-ConnectionGUID: 6TSzwOImQw2S7HKyESlE9Q== X-CSE-MsgGUID: eiXSh2t2TFaMo5yT1oYShA== X-IronPort-AV: E=McAfee;i="6700,10204,11169"; a="26191778" X-IronPort-AV: E=Sophos;i="6.10,160,1719903600"; d="scan'208";a="26191778" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Aug 2024 18:55:35 -0700 X-CSE-ConnectionGUID: VcusfswFRs6tYL/i+f9Qcg== X-CSE-MsgGUID: uo0vGZedSjePCZ9ss6Veqw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,160,1719903600"; d="scan'208";a="83759627" Received: from emr.sh.intel.com ([10.112.229.56]) by fmviesa002.fm.intel.com with ESMTP; 19 Aug 2024 18:55:31 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Kan Liang Cc: linux-kernel@vger.kernel.org, Andi Kleen , Yongwei Ma , Pawan Gupta , Dapeng Mi , Dapeng Mi Subject: [Patch v3 1/4] perf/x86: Refine hybrid_pmu_type defination Date: Tue, 20 Aug 2024 07:38:50 +0000 Message-Id: <20240820073853.1974746-2-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240820073853.1974746-1-dapeng1.mi@linux.intel.com> References: <20240820073853.1974746-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use macros instead of magic number to define hybrid_pmu_type and remove X86_HYBRID_NUM_PMUS since it's never used. Signed-off-by: Dapeng Mi Tested-by: Yongwei Ma Reviewed-by: Kan Liang --- arch/x86/events/perf_event.h | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index ac1182141bf6..fdd7d0369d42 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -674,19 +674,17 @@ enum hybrid_cpu_type { HYBRID_INTEL_CORE =3D 0x40, }; =20 +#define X86_HYBRID_PMU_ATOM_IDX 0 +#define X86_HYBRID_PMU_CORE_IDX 1 + enum hybrid_pmu_type { not_hybrid, - hybrid_small =3D BIT(0), - hybrid_big =3D BIT(1), + hybrid_small =3D BIT(X86_HYBRID_PMU_ATOM_IDX), + hybrid_big =3D BIT(X86_HYBRID_PMU_CORE_IDX), =20 hybrid_big_small =3D hybrid_big | hybrid_small, /* only used for matching= */ }; =20 -#define X86_HYBRID_PMU_ATOM_IDX 0 -#define X86_HYBRID_PMU_CORE_IDX 1 - -#define X86_HYBRID_NUM_PMUS 2 - struct x86_hybrid_pmu { struct pmu pmu; const char *name; --=20 2.40.1