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[98.183.112.25]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3dd33d5a3efsm2872718b6e.17.2024.08.20.08.58.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Aug 2024 08:58:53 -0700 (PDT) From: David Lechner Date: Tue, 20 Aug 2024 10:58:35 -0500 Subject: [PATCH 1/4] iio: adc: ad4695: add 2nd regmap for 16-bit registers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240820-ad4695-gain-offset-v1-1-c8f6e3b47551@baylibre.com> References: <20240820-ad4695-gain-offset-v1-0-c8f6e3b47551@baylibre.com> In-Reply-To: <20240820-ad4695-gain-offset-v1-0-c8f6e3b47551@baylibre.com> To: Jonathan Cameron Cc: Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Corbet , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, David Lechner X-Mailer: b4 0.14.1 The AD4695 and similar chips have some multibyte registers that have to be read/written in a single operation. So we need to add a 2nd regmap for these registers. These registers are removed from the 8-bit regmap allowable ranges and AD4695_MAX_REG is dropped since it would be ambiguous now. debugfs register access is also updated to automatically use the correct regmap depending on the register address. Signed-off-by: David Lechner --- drivers/iio/adc/ad4695.c | 83 +++++++++++++++++++++++++++++++++++++++-----= ---- 1 file changed, 68 insertions(+), 15 deletions(-) diff --git a/drivers/iio/adc/ad4695.c b/drivers/iio/adc/ad4695.c index b8547914f00f..63d816ad2d1f 100644 --- a/drivers/iio/adc/ad4695.c +++ b/drivers/iio/adc/ad4695.c @@ -34,6 +34,7 @@ /* AD4695 registers */ #define AD4695_REG_SPI_CONFIG_A 0x0000 #define AD4695_REG_SPI_CONFIG_A_SW_RST (BIT(7) | BIT(0)) +#define AD4695_REG_SPI_CONFIG_A_ADDR_DIR BIT(5) #define AD4695_REG_SPI_CONFIG_B 0x0001 #define AD4695_REG_SPI_CONFIG_B_INST_MODE BIT(7) #define AD4695_REG_DEVICE_TYPE 0x0003 @@ -77,7 +78,6 @@ #define AD4695_REG_GAIN_IN(n) (0x00C0 | (2 * (n))) #define AD4695_REG_AS_SLOT(n) (0x0100 | (n)) #define AD4695_REG_AS_SLOT_INX GENMASK(3, 0) -#define AD4695_MAX_REG 0x017F =20 /* Conversion mode commands */ #define AD4695_CMD_EXIT_CNV_MODE 0x0A @@ -121,6 +121,7 @@ struct ad4695_channel_config { struct ad4695_state { struct spi_device *spi; struct regmap *regmap; + struct regmap *regmap16; struct gpio_desc *reset_gpio; /* voltages channels plus temperature and timestamp */ struct iio_chan_spec iio_chan[AD4695_MAX_CHANNELS + 2]; @@ -150,8 +151,10 @@ static const struct regmap_range ad4695_regmap_rd_rang= es[] =3D { regmap_reg_range(AD4695_REG_SPI_CONFIG_C, AD4695_REG_SPI_STATUS), regmap_reg_range(AD4695_REG_STATUS, AD4695_REG_ALERT_STATUS2), regmap_reg_range(AD4695_REG_CLAMP_STATUS, AD4695_REG_CLAMP_STATUS), - regmap_reg_range(AD4695_REG_SETUP, AD4695_REG_TEMP_CTRL), - regmap_reg_range(AD4695_REG_CONFIG_IN(0), AD4695_MAX_REG), + regmap_reg_range(AD4695_REG_SETUP, AD4695_REG_AC_CTRL), + regmap_reg_range(AD4695_REG_GPIO_CTRL, AD4695_REG_TEMP_CTRL), + regmap_reg_range(AD4695_REG_CONFIG_IN(0), AD4695_REG_CONFIG_IN(15)), + regmap_reg_range(AD4695_REG_AS_SLOT(0), AD4695_REG_AS_SLOT(127)), }; =20 static const struct regmap_access_table ad4695_regmap_rd_table =3D { @@ -164,8 +167,10 @@ static const struct regmap_range ad4695_regmap_wr_rang= es[] =3D { regmap_reg_range(AD4695_REG_SCRATCH_PAD, AD4695_REG_SCRATCH_PAD), regmap_reg_range(AD4695_REG_LOOP_MODE, AD4695_REG_LOOP_MODE), regmap_reg_range(AD4695_REG_SPI_CONFIG_C, AD4695_REG_SPI_STATUS), - regmap_reg_range(AD4695_REG_SETUP, AD4695_REG_TEMP_CTRL), - regmap_reg_range(AD4695_REG_CONFIG_IN(0), AD4695_MAX_REG), + regmap_reg_range(AD4695_REG_SETUP, AD4695_REG_AC_CTRL), + regmap_reg_range(AD4695_REG_GPIO_CTRL, AD4695_REG_TEMP_CTRL), + regmap_reg_range(AD4695_REG_CONFIG_IN(0), AD4695_REG_CONFIG_IN(15)), + regmap_reg_range(AD4695_REG_AS_SLOT(0), AD4695_REG_AS_SLOT(127)), }; =20 static const struct regmap_access_table ad4695_regmap_wr_table =3D { @@ -174,15 +179,47 @@ static const struct regmap_access_table ad4695_regmap= _wr_table =3D { }; =20 static const struct regmap_config ad4695_regmap_config =3D { - .name =3D "ad4695", + .name =3D "ad4695-8", .reg_bits =3D 16, .val_bits =3D 8, - .max_register =3D AD4695_MAX_REG, + .max_register =3D AD4695_REG_AS_SLOT(127), .rd_table =3D &ad4695_regmap_rd_table, .wr_table =3D &ad4695_regmap_wr_table, .can_multi_write =3D true, }; =20 +static const struct regmap_range ad4695_regmap16_rd_ranges[] =3D { + regmap_reg_range(AD4695_REG_STD_SEQ_CONFIG, AD4695_REG_STD_SEQ_CONFIG), + regmap_reg_range(AD4695_REG_UPPER_IN(0), AD4695_REG_GAIN_IN(15)), +}; + +static const struct regmap_access_table ad4695_regmap16_rd_table =3D { + .yes_ranges =3D ad4695_regmap16_rd_ranges, + .n_yes_ranges =3D ARRAY_SIZE(ad4695_regmap16_rd_ranges), +}; + +static const struct regmap_range ad4695_regmap16_wr_ranges[] =3D { + regmap_reg_range(AD4695_REG_STD_SEQ_CONFIG, AD4695_REG_STD_SEQ_CONFIG), + regmap_reg_range(AD4695_REG_UPPER_IN(0), AD4695_REG_GAIN_IN(15)), +}; + +static const struct regmap_access_table ad4695_regmap16_wr_table =3D { + .yes_ranges =3D ad4695_regmap16_wr_ranges, + .n_yes_ranges =3D ARRAY_SIZE(ad4695_regmap16_wr_ranges), +}; + +static const struct regmap_config ad4695_regmap16_config =3D { + .name =3D "ad4695-16", + .reg_bits =3D 16, + .reg_stride =3D 2, + .val_bits =3D 16, + .val_format_endian =3D REGMAP_ENDIAN_LITTLE, + .max_register =3D AD4695_REG_GAIN_IN(15), + .rd_table =3D &ad4695_regmap16_rd_table, + .wr_table =3D &ad4695_regmap16_wr_table, + .can_multi_write =3D true, +}; + static const struct iio_chan_spec ad4695_channel_template =3D { .type =3D IIO_VOLTAGE, .indexed =3D 1, @@ -646,13 +683,24 @@ static int ad4695_debugfs_reg_access(struct iio_dev *= indio_dev, struct ad4695_state *st =3D iio_priv(indio_dev); =20 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { - if (readval) - return regmap_read(st->regmap, reg, readval); - - return regmap_write(st->regmap, reg, writeval); + if (readval) { + if (regmap_check_range_table(st->regmap, reg, + &ad4695_regmap_rd_table)) + return regmap_read(st->regmap, reg, readval); + if (regmap_check_range_table(st->regmap16, reg, + &ad4695_regmap16_rd_table)) + return regmap_read(st->regmap16, reg, readval); + } else { + if (regmap_check_range_table(st->regmap, reg, + &ad4695_regmap_wr_table)) + return regmap_write(st->regmap, reg, writeval); + if (regmap_check_range_table(st->regmap16, reg, + &ad4695_regmap16_wr_table)) + return regmap_write(st->regmap16, reg, writeval); + } } =20 - unreachable(); + return -EINVAL; } =20 static const struct iio_info ad4695_info =3D { @@ -807,6 +855,11 @@ static int ad4695_probe(struct spi_device *spi) return dev_err_probe(dev, PTR_ERR(st->regmap), "Failed to initialize regmap\n"); =20 + st->regmap16 =3D devm_regmap_init_spi(spi, &ad4695_regmap16_config); + if (IS_ERR(st->regmap16)) + return dev_err_probe(dev, PTR_ERR(st->regmap16), + "Failed to initialize regmap16\n"); + ret =3D devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(ad4695_power_supplies), ad4695_power_supplies); @@ -876,9 +929,9 @@ static int ad4695_probe(struct spi_device *spi) msleep(AD4695_T_WAKEUP_SW_MS); } =20 - /* Needed for debugfs since it only access registers 1 byte at a time. */ - ret =3D regmap_set_bits(st->regmap, AD4695_REG_SPI_CONFIG_C, - AD4695_REG_SPI_CONFIG_C_MB_STRICT); + /* Needed for regmap16 to be able to work correctly. */ + ret =3D regmap_set_bits(st->regmap, AD4695_REG_SPI_CONFIG_A, + AD4695_REG_SPI_CONFIG_A_ADDR_DIR); if (ret) return ret; =20 --=20 2.43.0