From nobody Sun Feb 8 06:49:55 2026 Received: from mail-pg1-f181.google.com (mail-pg1-f181.google.com [209.85.215.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C7D81E2108 for ; Mon, 19 Aug 2024 23:36:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724110594; cv=none; b=QCDgcNhSvI9BVSyizzKxiK9ivs6eWF+AwtR8RICeOcBcOj7oLdxuutHCuGzzjjvPm4cTOIFQm1qO+ogiNCN/QSBC1BUXeld3EX2pbK5I42vwtHOl+eW3HYt6gjxpSMLJRH33nPKVfkwX26v8Qn8I9JW4V2VWJM8iqglvrBEGGyQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724110594; c=relaxed/simple; bh=Roi5i8LAm2qbYFgu3vbjTEm7hUeJWtdnSFionwzXcEw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Pybm8bd0iik6IBWW+bnzgj+lMqc+JFALaV6kT+Y5qjjJSLJzdkmvIuFtOkU6TRdt2dm4Hmg34ww/qpN0T3lmbhATmo2yIKgbQcV274qD2x5ZOYhqlDndWtYRrXMLhxcxo/6Lxew8TnAQxqWKupum45R7LGPIxrX5Q37J6rE+CZo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=lRUamFfT; arc=none smtp.client-ip=209.85.215.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="lRUamFfT" Received: by mail-pg1-f181.google.com with SMTP id 41be03b00d2f7-6e7b121be30so3233660a12.1 for ; Mon, 19 Aug 2024 16:36:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1724110592; x=1724715392; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MTKeVDX3B7Rec/avu2J3HYCERK0HslRs8x4rP1mNjLc=; b=lRUamFfTS6DsVcWeFWIwQ3+KBQRhl2+x3p+POWL5+2fISjFp+Zo51yzcGXbd/aZaj2 FkwcJC9QRwDZZxsV7OkF3xg2rOvcUXMgE7l1dZrC+yWIrZATVXSCnVNxnff41PCiv+oM yWAoZexk2YKECd5pXyaSDllc9dC7rg7WluhEY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724110592; x=1724715392; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MTKeVDX3B7Rec/avu2J3HYCERK0HslRs8x4rP1mNjLc=; b=iveYPoX2iqPrDSBXDKDxbKWjB8bp1DG4jY7T+ifQHdrKH8xDeCxNSBj90/lsu4M3vg B2Z2FMiSoxCUcZgnV/zsXFE0bjxFCYMILlt5r4VSAnBNVtY+WvHJlcHwKTVD0QLXH9Xl AE2I0vD4tMYfpJbZqurn1WJ1Hc/8nY5657W2IKBSMYCMI1/ybzuxJw672U3U+XpF+bSP qZ1UeRDjwxr2YikhQrUKpzf+rXMO6Ei1W1aGtRwUmUXyzbqgyg77/eZHRdEHtm5LdbCS MHHAM5Z2PdIOFHUhkpDZwLfj20kxd8AmobxV4oso5qR0LXXRjBE90+PXP8TkLZdCYOo5 c2WQ== X-Gm-Message-State: AOJu0Yzq1NvgaoHwJEcaXKOmXGTO/3ENhWdj2q1pd3msVQ2F/sLYE0z9 p68Q/Q824px56vK2KXu0dGxMiK/4LXOc1Gtk7CfusAsyLNV3NhamzssTgNgcQA== X-Google-Smtp-Source: AGHT+IFja8fgz65fqj/HxtsU1jnIOssam1yt+nNI7Qy7HCclfpXJ6+fUompPLNl4vW+lHeeLPkoYmA== X-Received: by 2002:a17:90b:682:b0:2d3:c6dd:4383 with SMTP id 98e67ed59e1d1-2d3dfc6f2cdmr11172016a91.16.1724110591558; Mon, 19 Aug 2024 16:36:31 -0700 (PDT) Received: from localhost (210.73.125.34.bc.googleusercontent.com. [34.125.73.210]) by smtp.gmail.com with UTF8SMTPSA id 98e67ed59e1d1-2d3e3ebfe46sm7816927a91.57.2024.08.19.16.36.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 19 Aug 2024 16:36:31 -0700 (PDT) From: Stephen Boyd To: Konrad Dybcio , Bjorn Andersson , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, patches@lists.linux.dev, linux-clk@vger.kernel.org, Konrad Dybcio , Taniya Das , Amit Pundir Subject: [PATCH 1/2] clk: qcom: gcc-sm8550: Don't use parking clk_ops for QUPs Date: Mon, 19 Aug 2024 16:36:26 -0700 Message-ID: <20240819233628.2074654-2-swboyd@chromium.org> X-Mailer: git-send-email 2.46.0.184.g6999bdac58-goog In-Reply-To: <20240819233628.2074654-1-swboyd@chromium.org> References: <20240819233628.2074654-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The QUPs aren't shared in a way that requires parking the RCG at an always on parent in case some other entity turns on the clk. The hardware is capable of setting a new frequency itself with the DFS mode, so parking is unnecessary. Furthermore, there aren't any GDSCs for these devices, so there isn't a possibility of the GDSC turning on the clks for housekeeping purposes. This wasn't a problem to mark these clks shared until we started parking shared RCGs at clk registration time in commit 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration"). Parking at init is actually harmful to the UART when earlycon is used. If the device is pumping out data while the frequency changes you'll see garbage on the serial console until the driver can probe and actually set a proper frequency. Revert the QUP part of commit 929c75d57566 ("clk: qcom: gcc-sm8550: Mark RCGs shared where applicable") so that the QUPs don't get parked during clk registration and break UART operations. Fixes: 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration") Fixes: 929c75d57566 ("clk: qcom: gcc-sm8550: Mark RCGs shared where applica= ble") Cc: Konrad Dybcio Cc: Bjorn Andersson Cc: Taniya Das Reported-by: Amit Pundir Closes: https://lore.kernel.org/CAMi1Hd1KQBE4kKUdAn8E5FV+BiKzuv+8FoyWQrrTHP= DoYTuhgA@mail.gmail.com Signed-off-by: Stephen Boyd Tested-by: Amit Pundir --- drivers/clk/qcom/gcc-sm8550.c | 52 +++++++++++++++++------------------ 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c index 7944ddb4b47d..0244a05866b8 100644 --- a/drivers/clk/qcom/gcc-sm8550.c +++ b/drivers/clk/qcom/gcc-sm8550.c @@ -536,7 +536,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s0_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -551,7 +551,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s1_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -566,7 +566,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s2_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -581,7 +581,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s3_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -596,7 +596,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s4_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -611,7 +611,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s5_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -626,7 +626,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s6_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -641,7 +641,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s7_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -656,7 +656,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s8_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -671,7 +671,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s9_clk_src =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 @@ -700,7 +700,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src =3D { @@ -717,7 +717,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src =3D { @@ -750,7 +750,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src =3D { @@ -767,7 +767,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src =3D { @@ -784,7 +784,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src =3D { @@ -801,7 +801,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src =3D { @@ -818,7 +818,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src =3D { @@ -835,7 +835,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src =3D { @@ -852,7 +852,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src =3D { @@ -869,7 +869,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src =3D { @@ -886,7 +886,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src =3D { @@ -903,7 +903,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src =3D { @@ -920,7 +920,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src =3D { @@ -937,7 +937,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src =3D { @@ -975,7 +975,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_= init =3D { .parent_data =3D gcc_parent_data_8, .num_parents =3D ARRAY_SIZE(gcc_parent_data_8), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src =3D { @@ -992,7 +992,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_= init =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; 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[34.125.73.210]) by smtp.gmail.com with UTF8SMTPSA id d9443c01a7336-201f0302e84sm67507995ad.32.2024.08.19.16.36.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 19 Aug 2024 16:36:32 -0700 (PDT) From: Stephen Boyd To: Konrad Dybcio , Bjorn Andersson , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, patches@lists.linux.dev, linux-clk@vger.kernel.org, Konrad Dybcio , Taniya Das , Amit Pundir Subject: [PATCH 2/2] clk: qcom: gcc-sm8550: Don't park the USB RCG at registration time Date: Mon, 19 Aug 2024 16:36:27 -0700 Message-ID: <20240819233628.2074654-3-swboyd@chromium.org> X-Mailer: git-send-email 2.46.0.184.g6999bdac58-goog In-Reply-To: <20240819233628.2074654-1-swboyd@chromium.org> References: <20240819233628.2074654-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Amit Pundir reports that audio and USB-C host mode stops working if the gcc_usb30_prim_master_clk_src clk is registered and clk_rcg2_shared_init() parks it on XO. Skip parking this clk at registration time to fix those issues. Partially revert commit 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration") by skipping the parking bit for this clk, but keep the part where we cache the config register. That's still necessary to figure out the true parent of the clk at registration time. Fixes: 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration") Fixes: 929c75d57566 ("clk: qcom: gcc-sm8550: Mark RCGs shared where applica= ble") Cc: Konrad Dybcio Cc: Bjorn Andersson Cc: Taniya Das Reported-by: Amit Pundir Closes: https://lore.kernel.org/CAMi1Hd1KQBE4kKUdAn8E5FV+BiKzuv+8FoyWQrrTHP= DoYTuhgA@mail.gmail.com Signed-off-by: Stephen Boyd Tested-by: Amit Pundir --- drivers/clk/qcom/clk-rcg.h | 1 + drivers/clk/qcom/clk-rcg2.c | 30 ++++++++++++++++++++++++++++++ drivers/clk/qcom/gcc-sm8550.c | 2 +- 3 files changed, 32 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index d7414361e432..8e0f3372dc7a 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -198,6 +198,7 @@ extern const struct clk_ops clk_byte2_ops; extern const struct clk_ops clk_pixel_ops; extern const struct clk_ops clk_gfx3d_ops; extern const struct clk_ops clk_rcg2_shared_ops; +extern const struct clk_ops clk_rcg2_shared_no_init_park_ops; extern const struct clk_ops clk_dp_ops; =20 struct clk_rcg_dfs_data { diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 30b19bd39d08..bf26c5448f00 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -1348,6 +1348,36 @@ const struct clk_ops clk_rcg2_shared_ops =3D { }; EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops); =20 +static int clk_rcg2_shared_no_init_park(struct clk_hw *hw) +{ + struct clk_rcg2 *rcg =3D to_clk_rcg2(hw); + + /* + * Read the config register so that the parent is properly mapped at + * registration time. + */ + regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &rcg->parked_cfg); + + return 0; +} + +/* + * Like clk_rcg2_shared_ops but skip the init so that the clk frequency is= left + * unchanged at registration time. + */ +const struct clk_ops clk_rcg2_shared_no_init_park_ops =3D { + .init =3D clk_rcg2_shared_no_init_park, + .enable =3D clk_rcg2_shared_enable, + .disable =3D clk_rcg2_shared_disable, + .get_parent =3D clk_rcg2_shared_get_parent, + .set_parent =3D clk_rcg2_shared_set_parent, + .recalc_rate =3D clk_rcg2_shared_recalc_rate, + .determine_rate =3D clk_rcg2_determine_rate, + .set_rate =3D clk_rcg2_shared_set_rate, + .set_rate_and_parent =3D clk_rcg2_shared_set_rate_and_parent, +}; +EXPORT_SYMBOL_GPL(clk_rcg2_shared_no_init_park_ops); + /* Common APIs to be used for DFS based RCGR */ static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l, struct freq_tbl *f) diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c index 0244a05866b8..5abaeddd6afc 100644 --- a/drivers/clk/qcom/gcc-sm8550.c +++ b/drivers/clk/qcom/gcc-sm8550.c @@ -1159,7 +1159,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = =3D { .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_shared_no_init_park_ops, }, }; =20 --=20 https://chromeos.dev