From nobody Sun Feb 8 06:05:33 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8430515C121 for ; Mon, 19 Aug 2024 09:11:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724058717; cv=none; b=FyskF/x4Klw8fpUsQsWVXORbRRg0EqM9Aj/BI6K6K7FmtYcSUmIn/hpKTewAEAr7fM0xOQmkZb+ETCUOqNJryN7vkjDhrxV8ihz5kjx0bAzjMctW0pknCeLTV7+zOscIRr/YRbRfzEPG0Ol1slny3X2wCkzkDDMwebBJQsp86Tw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724058717; c=relaxed/simple; bh=wlaugqbw3LFf3hmhiS7UUatTrBz9k3GzQCs168nS3Vs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Tvmpam1nXzCx8Whh/kswr7fN0IZMfreDk2meSDDBb/wcwO0f1QXYHq3sPxAnKhoMIqgW0jOV7B30rNOv8/MRHB6NV1DHtYmQz6Pc7a8LOB7ZBPiftXo5wbyfHXTwi8qRkbN81+zWS3PqAtDkxYKsc4yWtzZzBRmDYE2DeSxqY98= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=hHR+RYjV; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="hHR+RYjV" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724058716; x=1755594716; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wlaugqbw3LFf3hmhiS7UUatTrBz9k3GzQCs168nS3Vs=; b=hHR+RYjVOVHZ/QXhH0t/lbEhOmkTE1VnSGHUAND3Rq3Hq7UfH3nEBAam LUKWu2Vm4vHefcOLdtvRBNnbHCCVNkFWSEmF9VKeA2baL+UcicTQpc2B+ Du+M4lr7W/1Jll1sf74cTnbvQK9aHLq3Ur02bVO6GM9FZFcUxKehVMAxh XervUSUMCrqBnFefXmwXlRNNETrxOOLuEqOQnM9LaccuLg0dO//sGxxm3 Dr7422Z4RqgNBYAFQvEnBh200JN72V8FbbpN59CbI3DxtoHwZnnBVSYF8 w/qobgYSIX0IsVQdzU9LKs0pwu53pBKm9fr0uXKk8yNp3PZCsprtWYN0c A==; X-CSE-ConnectionGUID: WNm/Ap8sR8+JfxKSDnvFLw== X-CSE-MsgGUID: 8sYL9CPdSB6zCMOX0qkD2Q== X-IronPort-AV: E=McAfee;i="6700,10204,11168"; a="33446093" X-IronPort-AV: E=Sophos;i="6.10,158,1719903600"; d="scan'208";a="33446093" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Aug 2024 02:11:56 -0700 X-CSE-ConnectionGUID: W1oaOVW6R6u/ZQQloCG1Iw== X-CSE-MsgGUID: J5Kqa7UcT/Kc6X5HSZZ1rA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,158,1719903600"; d="scan'208";a="61086706" Received: from emr.sh.intel.com ([10.112.229.56]) by orviesa008.jf.intel.com with ESMTP; 19 Aug 2024 02:11:54 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Kan Liang Cc: linux-kernel@vger.kernel.org, Andi Kleen , Yongwei Ma , Pawan Gupta , Dapeng Mi , Dapeng Mi Subject: [Patch v2 1/4] perf/x86: Refine hybrid_pmu_type defination Date: Mon, 19 Aug 2024 14:55:40 +0000 Message-Id: <20240819145543.1833126-2-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240819145543.1833126-1-dapeng1.mi@linux.intel.com> References: <20240819145543.1833126-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use macros instead of magic number to define hybrid_pmu_type and remove X86_HYBRID_NUM_PMUS since it's never used. Signed-off-by: Dapeng Mi Tested-by: Yongwei Ma --- arch/x86/events/perf_event.h | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index ac1182141bf6..fdd7d0369d42 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -674,19 +674,17 @@ enum hybrid_cpu_type { HYBRID_INTEL_CORE =3D 0x40, }; =20 +#define X86_HYBRID_PMU_ATOM_IDX 0 +#define X86_HYBRID_PMU_CORE_IDX 1 + enum hybrid_pmu_type { not_hybrid, - hybrid_small =3D BIT(0), - hybrid_big =3D BIT(1), + hybrid_small =3D BIT(X86_HYBRID_PMU_ATOM_IDX), + hybrid_big =3D BIT(X86_HYBRID_PMU_CORE_IDX), =20 hybrid_big_small =3D hybrid_big | hybrid_small, /* only used for matching= */ }; =20 -#define X86_HYBRID_PMU_ATOM_IDX 0 -#define X86_HYBRID_PMU_CORE_IDX 1 - -#define X86_HYBRID_NUM_PMUS 2 - struct x86_hybrid_pmu { struct pmu pmu; const char *name; --=20 2.40.1