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The main difference between AD7606C-16 & AD7606C-18 is the precision in bits (16 vs 18). Because of that, some scales need to be defined for the 18-bit variants, as they need to be computed against 2**18 (vs 2**16 for the 16 bit-variants). Because the AD7606C-16,18 also supports bipolar & differential channels, for SW-mode, the default range of 10 V or =C2=B110V should be set at probe. On reset, the default range (in the registers) is set to value 0x3 which corresponds to '=C2=B110 V single-ended range', regardless of bipolar or differential configuration. Aside from the scale/ranges, the AD7606C-16 is similar to the AD7606B. And the AD7606C-18 variant offers 18-bit precision. The unfortunate effect of this 18-bit sample size, is that there is no simple/neat way to get the samples into a 32-bit array without having to do a home-brewed bit-buffer. The ADC must read all samples (from all 8 channels) in order to get the N-th sample (this could be reworked to do up-to-N-th sample for scan-direct= ). There doesn't seem to be any quick-trick to be usable to pad the samples up to at least 24 bits. Even the optional status-header is 8-bits, which would mean 26-bits of data per sample. That means that when using a simple SPI controller (which can usually read 8 bit multiples) a simple bit-buffer trick is required. Datasheet links: https://www.analog.com/media/en/technical-documentation/data-sheets/ad760= 6c-16.pdf https://www.analog.com/media/en/technical-documentation/data-sheets/ad760= 6c-18.pdf Signed-off-by: Alexandru Ardelean --- drivers/iio/adc/ad7606.c | 274 ++++++++++++++++++++++++++++++++--- drivers/iio/adc/ad7606.h | 17 ++- drivers/iio/adc/ad7606_spi.c | 94 ++++++++++++ 3 files changed, 357 insertions(+), 28 deletions(-) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index 7533aab4b7c8..55faab321092 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -28,14 +28,44 @@ =20 #include "ad7606.h" =20 +typedef void (*ad7606c_chan_setup_cb_t)(struct ad7606_state *st, int ch, + bool bipolar, bool differential); + /* * Scales are computed as 5000/32768 and 10000/32768 respectively, * so that when applied to the raw values they provide mV values */ -static const unsigned int ad7606_scale_avail[2] =3D { +static const unsigned int ad7606_16bit_hw_scale_avail[2] =3D { 152588, 305176 }; =20 +static const unsigned int ad7606_18bit_hw_scale_avail[2] =3D { + 38147, 76294 +}; + +static const unsigned int ad7606c_16_scale_single_ended_unipolar_avail[3] = =3D { + 76294, 152588, 190735, +}; + +static const unsigned int ad7606c_16_scale_single_ended_bipolar_avail[5] = =3D { + 76294, 152588, 190735, 305176, 381470 +}; + +static const unsigned int ad7606c_16_scale_differential_bipolar_avail[4] = =3D { + 152588, 305176, 381470, 610352 +}; + +static const unsigned int ad7606c_18_scale_single_ended_unipolar_avail[3] = =3D { + 19073, 38147, 47684 +}; + +static const unsigned int ad7606c_18_scale_single_ended_bipolar_avail[5] = =3D { + 19073, 38147, 47684, 76294, 95367 +}; + +static const unsigned int ad7606c_18_scale_differential_bipolar_avail[4] = =3D { + 38147, 76294, 95367, 152588 +}; =20 static const unsigned int ad7616_sw_scale_avail[3] =3D { 76293, 152588, 305176 @@ -84,10 +114,18 @@ static int ad7606_reg_access(struct iio_dev *indio_dev, =20 static int ad7606_read_samples(struct ad7606_state *st) { + unsigned int storagebits =3D st->chip_info->channels[1].scan_type.storage= bits; unsigned int num =3D st->chip_info->num_channels - 1; - u16 *data =3D st->data; + u32 *data32 =3D st->data.d32; + u16 *data16 =3D st->data.d16; + void *data; int ret; =20 + if (storagebits > 16) + data =3D data32; + else + data =3D data16; + /* * The frstdata signal is set to high while and after reading the sample * of the first channel and low for all other channels. This can be used @@ -108,7 +146,10 @@ static int ad7606_read_samples(struct ad7606_state *st) return -EIO; } =20 - data++; + if (storagebits > 16) + data32++; + else + data16++; num--; } =20 @@ -128,7 +169,7 @@ static irqreturn_t ad7606_trigger_handler(int irq, void= *p) if (ret) goto error_ret; =20 - iio_push_to_buffers_with_timestamp(indio_dev, st->data, + iio_push_to_buffers_with_timestamp(indio_dev, st->data.d16, iio_get_time_ns(indio_dev)); error_ret: iio_trigger_notify_done(indio_dev->trig); @@ -142,6 +183,7 @@ static int ad7606_scan_direct(struct iio_dev *indio_dev= , unsigned int ch, int *val) { struct ad7606_state *st =3D iio_priv(indio_dev); + unsigned int storagebits =3D st->chip_info->channels[1].scan_type.storage= bits; int ret; =20 gpiod_set_value(st->gpio_convst, 1); @@ -153,8 +195,12 @@ static int ad7606_scan_direct(struct iio_dev *indio_de= v, unsigned int ch, } =20 ret =3D ad7606_read_samples(st); - if (ret =3D=3D 0) - *val =3D sign_extend32(st->data[ch], 15); + if (ret =3D=3D 0) { + if (storagebits > 16) + *val =3D sign_extend32(st->data.d32[ch], 17); + else + *val =3D sign_extend32(st->data.d16[ch], 15); + } =20 error_ret: gpiod_set_value(st->gpio_convst, 0); @@ -267,7 +313,7 @@ static int ad7606_write_raw(struct iio_dev *indio_dev, ch =3D chan->address; cs =3D &st->chan_scales[ch]; i =3D find_closest(val2, cs->scale_avail, cs->num_scales); - ret =3D st->write_scale(indio_dev, ch, i); + ret =3D st->write_scale(indio_dev, ch, i + cs->reg_offset); if (ret < 0) return ret; cs->range =3D i; @@ -350,6 +396,18 @@ static const struct iio_chan_spec ad7606_channels_16bi= t[] =3D { AD7606_CHANNEL(7, 16), }; =20 +static const struct iio_chan_spec ad7606_channels_18bit[] =3D { + IIO_CHAN_SOFT_TIMESTAMP(8), + AD7606_CHANNEL(0, 18), + AD7606_CHANNEL(1, 18), + AD7606_CHANNEL(2, 18), + AD7606_CHANNEL(3, 18), + AD7606_CHANNEL(4, 18), + AD7606_CHANNEL(5, 18), + AD7606_CHANNEL(6, 18), + AD7606_CHANNEL(7, 18), +}; + /* * The current assumption that this driver makes for AD7616, is that it's * working in Hardware Mode with Serial, Burst and Sequencer modes activat= ed. @@ -410,6 +468,18 @@ static const struct ad7606_chip_info ad7606_chip_info_= tbl[] =3D { .oversampling_avail =3D ad7606_oversampling_avail, .oversampling_num =3D ARRAY_SIZE(ad7606_oversampling_avail), }, + [ID_AD7606C_16] =3D { + .channels =3D ad7606_channels_16bit, + .num_channels =3D 9, + .oversampling_avail =3D ad7606_oversampling_avail, + .oversampling_num =3D ARRAY_SIZE(ad7606_oversampling_avail), + }, + [ID_AD7606C_18] =3D { + .channels =3D ad7606_channels_18bit, + .num_channels =3D 9, + .oversampling_avail =3D ad7606_oversampling_avail, + .oversampling_num =3D ARRAY_SIZE(ad7606_oversampling_avail), + }, [ID_AD7616] =3D { .channels =3D ad7616_channels, .num_channels =3D 17, @@ -563,6 +633,14 @@ static const struct iio_info ad7606_info_sw_mode =3D { .validate_trigger =3D &ad7606_validate_trigger, }; =20 +static const struct iio_info ad7606c_info_sw_mode =3D { + .read_raw =3D &ad7606_read_raw, + .write_raw =3D &ad7606_write_raw, + .read_avail =3D &ad7606_read_avail, + .debugfs_reg_access =3D &ad7606_reg_access, + .validate_trigger =3D &ad7606_validate_trigger, +}; + static const struct iio_info ad7606_info_os =3D { .read_raw =3D &ad7606_read_raw, .write_raw =3D &ad7606_write_raw, @@ -581,7 +659,136 @@ static const struct iio_trigger_ops ad7606_trigger_op= s =3D { .validate_device =3D iio_trigger_validate_own_device, }; =20 -static int ad7606_sw_mode_setup(struct iio_dev *indio_dev) +static void ad7606c_18_chan_setup(struct ad7606_state *st, int ch, + bool bipolar, bool differential) +{ + struct ad7606_chan_scale *cs =3D &st->chan_scales[ch]; + + if (differential) { + cs->scale_avail =3D + ad7606c_18_scale_differential_bipolar_avail; + cs->num_scales =3D + ARRAY_SIZE(ad7606c_18_scale_differential_bipolar_avail); + /* Bipolar differential ranges start at 8 (b1000) */ + cs->reg_offset =3D 8; + cs->range =3D 1; + } else if (bipolar) { + cs->scale_avail =3D + ad7606c_18_scale_single_ended_bipolar_avail; + cs->num_scales =3D + ARRAY_SIZE(ad7606c_18_scale_single_ended_bipolar_avail); + cs->range =3D 3; + } else { + cs->scale_avail =3D + ad7606c_18_scale_single_ended_unipolar_avail; + cs->num_scales =3D + ARRAY_SIZE(ad7606c_18_scale_single_ended_unipolar_avail); + /* Unipolar single-ended ranges start at 5 (b0101) */ + cs->reg_offset =3D 5; + cs->range =3D 1; + } +} + +static void ad7606c_16_chan_setup(struct ad7606_state *st, int ch, + bool bipolar, bool differential) +{ + struct ad7606_chan_scale *cs =3D &st->chan_scales[ch]; + + if (differential) { + cs->scale_avail =3D + ad7606c_16_scale_differential_bipolar_avail; + cs->num_scales =3D + ARRAY_SIZE(ad7606c_16_scale_differential_bipolar_avail); + /* Bipolar differential ranges start at 8 (b1000) */ + cs->reg_offset =3D 8; + cs->range =3D 1; + } else if (bipolar) { + cs->scale_avail =3D + ad7606c_16_scale_single_ended_bipolar_avail; + cs->num_scales =3D + ARRAY_SIZE(ad7606c_16_scale_single_ended_bipolar_avail); + cs->range =3D 3; + } else { + cs->scale_avail =3D + ad7606c_16_scale_single_ended_unipolar_avail; + cs->num_scales =3D + ARRAY_SIZE(ad7606c_16_scale_single_ended_unipolar_avail); + /* Unipolar single-ended ranges start at 5 (b0101) */ + cs->reg_offset =3D 5; + cs->range =3D 1; + } +} + +static int ad7606c_sw_mode_setup_channels(struct iio_dev *indio_dev, + ad7606c_chan_setup_cb_t chan_setup_cb) +{ + unsigned int num_channels =3D indio_dev->num_channels - 1; + struct ad7606_state *st =3D iio_priv(indio_dev); + bool chan_configured[AD760X_MAX_CHANNELS]; + struct device *dev =3D st->dev; + int ret; + u32 ch; + + /* We need to hook this first */ + ret =3D st->bops->sw_mode_config(indio_dev); + if (ret) + return ret; + + indio_dev->info =3D &ad7606c_info_sw_mode; + + memset(chan_configured, 0, sizeof(chan_configured)); + + device_for_each_child_node_scoped(dev, child) { + bool bipolar, differential; + + ret =3D fwnode_property_read_u32(child, "reg", &ch); + if (ret) + continue; + + if (ch >=3D num_channels) { + dev_warn(st->dev, + "Invalid channel number (ignoring): %d\n", ch); + continue; + } + + bipolar =3D fwnode_property_present(child, "bipolar"); + differential =3D fwnode_property_present(child, "diff-channel"); + + chan_setup_cb(st, ch, bipolar, differential); + chan_configured[ch] =3D true; + } + + /* Apply default configuration to unconfigured (via DT) channels */ + for (ch =3D 0; ch < num_channels; ch++) { + struct ad7606_chan_scale *cs; + unsigned int *scale_avail_show; + int i; + + if (!chan_configured[ch]) + chan_setup_cb(st, ch, false, false); + + /* AD7606C supports different scales per channel */ + cs =3D &st->chan_scales[ch]; + + scale_avail_show =3D devm_kcalloc(st->dev, cs->num_scales * 2, + sizeof(*scale_avail_show), + GFP_KERNEL); + if (!scale_avail_show) + return -ENOMEM; + + /* Generate a scale_avail list for showing to userspace */ + for (i =3D 0; i < cs->num_scales; i++) { + scale_avail_show[i * 2] =3D 0; + scale_avail_show[i * 2 + 1] =3D cs->scale_avail[i]; + } + + cs->scale_avail_show =3D scale_avail_show; + } + + return 0; +} + +static int ad7606_sw_mode_setup(struct iio_dev *indio_dev, unsigned int id) { unsigned int num_channels =3D indio_dev->num_channels - 1; struct ad7606_state *st =3D iio_priv(indio_dev); @@ -597,21 +804,33 @@ static int ad7606_sw_mode_setup(struct iio_dev *indio= _dev) =20 indio_dev->info =3D &ad7606_info_sw_mode; =20 - /* Scale of 0.076293 is only available in sw mode */ - /* After reset, in software mode, =C2=B110 V is set by default */ - for (ch =3D 0; ch < num_channels; ch++) { - struct ad7606_chan_scale *cs =3D &st->chan_scales[ch]; + switch (id) { + case ID_AD7606C_18: + num_scales_avail_show =3D num_channels; + ret =3D ad7606c_sw_mode_setup_channels(indio_dev, + ad7606c_18_chan_setup); + break; + case ID_AD7606C_16: + num_scales_avail_show =3D num_channels; + ret =3D ad7606c_sw_mode_setup_channels(indio_dev, + ad7606c_16_chan_setup); + break; + default: + num_scales_avail_show =3D 1; =20 - cs->scale_avail =3D ad7616_sw_scale_avail; - cs->num_scales =3D ARRAY_SIZE(ad7616_sw_scale_avail); - cs->range =3D 2; - } + /* Scale of 0.076293 is only available in sw mode */ + /* After reset, in software mode, =C2=B110 V is set by default */ + for (ch =3D 0; ch < num_channels; ch++) { + struct ad7606_chan_scale *cs =3D &st->chan_scales[ch]; =20 - ret =3D st->bops->sw_mode_config(indio_dev); - if (ret) - return ret; + cs->scale_avail =3D ad7616_sw_scale_avail; + cs->num_scales =3D ARRAY_SIZE(ad7616_sw_scale_avail); + cs->range =3D 2; + } =20 - num_scales_avail_show =3D 1; + ret =3D st->bops->sw_mode_config(indio_dev); + break; + } =20 for (ch =3D 0; ch < num_channels; ch++) { struct ad7606_chan_scale *cs; @@ -667,9 +886,16 @@ int ad7606_probe(struct device *dev, int irq, void __i= omem *base_address, st->oversampling =3D 1; =20 cs =3D &st->chan_scales[0]; - cs->range =3D 0; - cs->scale_avail =3D ad7606_scale_avail; - cs->num_scales =3D ARRAY_SIZE(ad7606_scale_avail); + switch (id) { + case ID_AD7606C_18: + cs->scale_avail =3D ad7606_18bit_hw_scale_avail; + cs->num_scales =3D ARRAY_SIZE(ad7606_18bit_hw_scale_avail); + break; + default: + cs->scale_avail =3D ad7606_16bit_hw_scale_avail; + cs->num_scales =3D ARRAY_SIZE(ad7606_16bit_hw_scale_avail); + break; + } =20 ret =3D devm_regulator_get_enable(dev, "avcc"); if (ret) @@ -718,7 +944,7 @@ int ad7606_probe(struct device *dev, int irq, void __io= mem *base_address, st->write_scale =3D ad7606_write_scale_hw; st->write_os =3D ad7606_write_os_hw; =20 - ret =3D ad7606_sw_mode_setup(indio_dev); + ret =3D ad7606_sw_mode_setup(indio_dev, id); if (ret) return ret; =20 diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index d71a843a5de5..fa9305923a72 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -22,7 +22,7 @@ .scan_type =3D { \ .sign =3D 's', \ .realbits =3D (bits), \ - .storagebits =3D (bits), \ + .storagebits =3D (bits) > 16 ? 32 : 16, \ .endianness =3D IIO_CPU, \ }, \ } @@ -45,7 +45,7 @@ .scan_type =3D { \ .sign =3D 's', \ .realbits =3D (bits), \ - .storagebits =3D (bits), \ + .storagebits =3D (bits) > 16 ? 32 : 16, \ .endianness =3D IIO_CPU, \ }, \ } @@ -88,12 +88,15 @@ struct ad7606_chip_info { * such that it can be read via the 'read_avail' hook * @num_scales number of elements stored in the scale_avail array * @range voltage range selection, selects which scale to apply + * @reg_offset offset for the register value, to be applied when + * writing the value of 'range' to the register value */ struct ad7606_chan_scale { const unsigned int *scale_avail; const unsigned int *scale_avail_show; unsigned int num_scales; unsigned int range; + unsigned int reg_offset; }; =20 /** @@ -150,9 +153,13 @@ struct ad7606_state { /* * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. - * 16 * 16-bit samples + 64-bit timestamp + * 16 * 16-bit samples + 64-bit timestamp - for AD7616 + * 8 * 32-bit samples + 64-bit timestamp - for AD7616C-18 (and similar) */ - unsigned short data[20] __aligned(IIO_DMA_MINALIGN); + union { + unsigned short d16[20]; + unsigned int d32[10]; + } data __aligned(IIO_DMA_MINALIGN); __be16 d16[2]; }; =20 @@ -191,6 +198,8 @@ enum ad7606_supported_device_ids { ID_AD7606_6, ID_AD7606_4, ID_AD7606B, + ID_AD7606C_16, + ID_AD7606C_18, ID_AD7616, }; =20 diff --git a/drivers/iio/adc/ad7606_spi.c b/drivers/iio/adc/ad7606_spi.c index dd0075c97c24..73a7b0007bf8 100644 --- a/drivers/iio/adc/ad7606_spi.c +++ b/drivers/iio/adc/ad7606_spi.c @@ -45,6 +45,8 @@ #define AD7606_RANGE_CH_ADDR(ch) (0x03 + ((ch) >> 1)) #define AD7606_OS_MODE 0x08 =20 +#define AD7606C_18_SAMPLE_MASK GENMASK(17, 0) + static const struct iio_chan_spec ad7616_sw_channels[] =3D { IIO_CHAN_SOFT_TIMESTAMP(16), AD7616_CHANNEL(0), @@ -77,6 +79,18 @@ static const struct iio_chan_spec ad7606b_sw_channels[] = =3D { AD7606_SW_CHANNEL(7, 16), }; =20 +static const struct iio_chan_spec ad7606c_18_sw_channels[] =3D { + IIO_CHAN_SOFT_TIMESTAMP(8), + AD7606_SW_CHANNEL(0, 18), + AD7606_SW_CHANNEL(1, 18), + AD7606_SW_CHANNEL(2, 18), + AD7606_SW_CHANNEL(3, 18), + AD7606_SW_CHANNEL(4, 18), + AD7606_SW_CHANNEL(5, 18), + AD7606_SW_CHANNEL(6, 18), + AD7606_SW_CHANNEL(7, 18), +}; + static const unsigned int ad7606B_oversampling_avail[9] =3D { 1, 2, 4, 8, 16, 32, 64, 128, 256 }; @@ -120,6 +134,56 @@ static int ad7606_spi_read_block(struct device *dev, return 0; } =20 +static int ad7606_spi_read_block18to32(struct device *dev, + int count, void *buf) +{ + struct spi_device *spi =3D to_spi_device(dev); + u32 i, bit_buffer, buf_size, bit_buf_size; + u32 *data =3D buf; + u8 *bdata =3D buf; + int j, ret; + + /** + * With the 18 bit ADC variants (here) is that we can't assume that all + * SPI controllers will pad 18-bit sequences into 32-bit arrays, + * so we need to do a bit of buffer magic here. + * Alternatively, we can have a variant of this function that works + * for SPI controllers that can pad 18-bit samples into 32-bit arrays. + */ + + /* Write 'count' bytes to the right, to not overwrite samples */ + bdata +=3D count; + + /* Read 24 bits only, as we'll only get samples of 18 bits each */ + buf_size =3D count * 3; + ret =3D spi_read(spi, bdata, buf_size); + if (ret < 0) { + dev_err(&spi->dev, "SPI read error\n"); + return ret; + } + + bit_buffer =3D 0; + bit_buf_size =3D 0; + for (j =3D 0, i =3D 0; i < buf_size; i++) { + u32 sample; + + bit_buffer =3D (bit_buffer << 8) | bdata[i]; + bit_buf_size +=3D 8; + + if (bit_buf_size < 18) + continue; + + bit_buf_size -=3D 18; + sample =3D (bit_buffer >> bit_buf_size) & AD7606C_18_SAMPLE_MASK; + data[j++] =3D sign_extend32(sample, 17); + + if (j =3D=3D count) + break; + } + + return 0; +} + static int ad7606_spi_reg_read(struct ad7606_state *st, unsigned int addr) { struct spi_device *spi =3D to_spi_device(st->dev); @@ -283,6 +347,19 @@ static int ad7606B_sw_mode_config(struct iio_dev *indi= o_dev) return 0; } =20 +static int ad7606c_18_sw_mode_config(struct iio_dev *indio_dev) +{ + int ret; + + ret =3D ad7606B_sw_mode_config(indio_dev); + if (ret) + return ret; + + indio_dev->channels =3D ad7606c_18_sw_channels; + + return 0; +} + static const struct ad7606_bus_ops ad7606_spi_bops =3D { .read_block =3D ad7606_spi_read_block, }; @@ -305,6 +382,15 @@ static const struct ad7606_bus_ops ad7606B_spi_bops = =3D { .sw_mode_config =3D ad7606B_sw_mode_config, }; =20 +static const struct ad7606_bus_ops ad7606c_18_spi_bops =3D { + .read_block =3D ad7606_spi_read_block18to32, + .reg_read =3D ad7606_spi_reg_read, + .reg_write =3D ad7606_spi_reg_write, + .write_mask =3D ad7606_spi_write_mask, + .rd_wr_cmd =3D ad7606B_spi_rd_wr_cmd, + .sw_mode_config =3D ad7606c_18_sw_mode_config, +}; + static int ad7606_spi_probe(struct spi_device *spi) { const struct spi_device_id *id =3D spi_get_device_id(spi); @@ -315,8 +401,12 @@ static int ad7606_spi_probe(struct spi_device *spi) bops =3D &ad7616_spi_bops; break; case ID_AD7606B: + case ID_AD7606C_16: bops =3D &ad7606B_spi_bops; break; + case ID_AD7606C_18: + bops =3D &ad7606c_18_spi_bops; + break; default: bops =3D &ad7606_spi_bops; break; @@ -333,6 +423,8 @@ static const struct spi_device_id ad7606_id_table[] =3D= { { "ad7606-6", ID_AD7606_6 }, { "ad7606-8", ID_AD7606_8 }, { "ad7606b", ID_AD7606B }, + { "ad7606c-16", ID_AD7606C_16 }, + { "ad7606c-18", ID_AD7606C_18 }, { "ad7616", ID_AD7616 }, {} }; @@ -344,6 +436,8 @@ static const struct of_device_id ad7606_of_match[] =3D { { .compatible =3D "adi,ad7606-6" }, { .compatible =3D "adi,ad7606-8" }, { .compatible =3D "adi,ad7606b" }, + { .compatible =3D "adi,ad7606c-16" }, + { .compatible =3D "adi,ad7606c-18" }, { .compatible =3D "adi,ad7616" }, { }, }; --=20 2.46.0