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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-201f0375649sm55784435ad.124.2024.08.18.20.56.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Aug 2024 20:56:56 -0700 (PDT) From: Jacky Huang To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, soc@kernel.org, schung@nuvoton.com, ychuang3@nuvoton.com Subject: [PATCH 2/3] arm64: dts: nuvoton: ma35d1: Add pinctrl and gpio nodes Date: Mon, 19 Aug 2024 03:56:46 +0000 Message-Id: <20240819035647.306-3-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240819035647.306-1-ychuang570808@gmail.com> References: <20240819035647.306-1-ychuang570808@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jacky Huang Added the pinctrl node and its subnodes, the gpioa through gpion nodes, to the MA35D1 device tree. Signed-off-by: Jacky Huang --- arch/arm64/boot/dts/nuvoton/ma35d1.dtsi | 149 ++++++++++++++++++++++++ 1 file changed, 149 insertions(+) diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi b/arch/arm64/boot/dts/= nuvoton/ma35d1.dtsi index a6b34e3e8b10..e51b98f5bdce 100644 --- a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi +++ b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi @@ -95,6 +95,155 @@ clk: clock-controller@40460200 { clocks =3D <&clk_hxt>; }; =20 + pinctrl: pinctrl@40040000 { + compatible =3D "nuvoton,ma35d1-pinctrl"; + reg =3D <0x0 0x40040000 0x0 0xc00>; + #address-cells =3D <1>; + #size-cells =3D <1>; + nuvoton,sys =3D <&sys>; + ranges =3D <0x0 0x0 0x40040000 0x400>; + + gpioa: gpio@0 { + reg =3D <0x0 0x40>; + interrupts =3D ; + clocks =3D <&clk GPA_GATE>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpiob: gpio@40 { + reg =3D <0x40 0x40>; + interrupts =3D ; + clocks =3D <&clk GPB_GATE>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpioc: gpio@80 { + reg =3D <0x80 0x40>; + interrupts =3D ; + clocks =3D <&clk GPC_GATE>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpiod: gpio@c0 { + reg =3D <0xc0 0x40>; + interrupts =3D ; + clocks =3D <&clk GPD_GATE>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpioe: gpio@100 { + reg =3D <0x100 0x40>; + interrupts =3D ; + clocks =3D <&clk GPE_GATE>; + #gpio-cells =3D <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpiof: gpio@140 { + reg =3D <0x140 0x40>; + interrupts =3D ; + clocks =3D <&clk GPF_GATE>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpiog: gpio@180 { + reg =3D <0x180 0x40>; + interrupts =3D ; + clocks =3D <&clk GPG_GATE>; + #gpio-cells =3D <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpioh: gpio@1c0 { + reg =3D <0x1c0 0x40>; + interrupts =3D ; + clocks =3D <&clk GPH_GATE>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpioi: gpio@200 { + reg =3D <0x200 0x40>; + interrupts =3D ; + clocks =3D <&clk GPI_GATE>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpioj: gpio@240 { + reg =3D <0x240 0x40>; + interrupts =3D ; + clocks =3D <&clk GPJ_GATE>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpiok: gpio@280 { + reg =3D <0x280 0x40>; + interrupts =3D ; + clocks =3D <&clk GPK_GATE>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpiol: gpio@2c0 { + reg =3D <0x2c0 0x40>; + interrupts =3D ; + clocks =3D <&clk GPL_GATE>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpiom: gpio@300 { + reg =3D <0x300 0x40>; + interrupts =3D ; + clocks =3D <&clk GPM_GATE>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpion: gpio@340 { + reg =3D <0x340 0x40>; + interrupts =3D ; + clocks =3D <&clk GPN_GATE>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + uart0: serial@40700000 { compatible =3D "nuvoton,ma35d1-uart"; reg =3D <0x0 0x40700000 0x0 0x100>; --=20 2.34.1