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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Aug 2024 03:01:36.3367 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a941a374-ccf0-4b2f-7f6d-08dcbffb3d3b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8152 Content-Type: text/plain; charset="utf-8" AMD-Xilinx zynqmp platform contains on-chip sram memory (OCM). R5 cores can access OCM and access is faster than DDR memory but slower than TCM memories available. Sram region can have optional multiple power-domains. Platform management firmware is responsible to operate these power-domains. Signed-off-by: Tanmay Shah --- Changes in v2: - Expand commit message with power-domains related information. Changes in v3: - make @sram an array rather than an array of pointers - fix of_node_put usage to maintain proper refcount of node - s/proprty/property - Use gen pool framework for mapping sram address space. drivers/remoteproc/xlnx_r5_remoteproc.c | 155 ++++++++++++++++++++++++ 1 file changed, 155 insertions(+) diff --git a/drivers/remoteproc/xlnx_r5_remoteproc.c b/drivers/remoteproc/x= lnx_r5_remoteproc.c index 2cea97c746fd..1f704b99a67d 100644 --- a/drivers/remoteproc/xlnx_r5_remoteproc.c +++ b/drivers/remoteproc/xlnx_r5_remoteproc.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -56,6 +57,21 @@ struct mem_bank_data { char *bank_name; }; =20 +/** + * struct zynqmp_sram_bank - sram bank description + * + * @sram_pool: gen pool for his sram + * @sram_res: sram address region information + * @va: virtual address of allocated genpool + * @da: device address of sram + */ +struct zynqmp_sram_bank { + struct gen_pool *sram_pool; + struct resource sram_res; + void __iomem *va; + u32 da; +}; + /** * struct mbox_info * @@ -120,6 +136,8 @@ static const struct mem_bank_data zynqmp_tcm_banks_lock= step[] =3D { * struct zynqmp_r5_core * * @rsc_tbl_va: resource table virtual address + * @sram: Array of sram memories assigned to this core + * @num_sram: number of sram for this core * @dev: device of RPU instance * @np: device node of RPU instance * @tcm_bank_count: number TCM banks accessible to this RPU @@ -131,6 +149,8 @@ static const struct mem_bank_data zynqmp_tcm_banks_lock= step[] =3D { */ struct zynqmp_r5_core { void __iomem *rsc_tbl_va; + struct zynqmp_sram_bank *sram; + int num_sram; struct device *dev; struct device_node *np; int tcm_bank_count; @@ -494,6 +514,46 @@ static int add_mem_regions_carveout(struct rproc *rpro= c) return 0; } =20 +static int add_sram_carveouts(struct rproc *rproc) +{ + struct zynqmp_r5_core *r5_core =3D rproc->priv; + struct rproc_mem_entry *rproc_mem; + struct zynqmp_sram_bank *sram; + size_t len, pool_size; + dma_addr_t dma_addr; + int da, i; + + for (i =3D 0; i < r5_core->num_sram; i++) { + sram =3D &r5_core->sram[i]; + + dma_addr =3D (dma_addr_t)sram->sram_res.start; + len =3D resource_size(&sram->sram_res); + da =3D sram->da; + + pool_size =3D gen_pool_size(sram[i].sram_pool); + sram->va =3D (void __iomem *)gen_pool_alloc(sram->sram_pool, pool_size); + if (!sram->va) { + dev_err(r5_core->dev, "failed to alloc sram idx %d pool\n", i); + return -ENOMEM; + } + + /* Register associated reserved memory regions */ + rproc_mem =3D rproc_mem_entry_init(&rproc->dev, sram->va, + (dma_addr_t)dma_addr, + len, da, + NULL, NULL, + sram->sram_res.name); + + rproc_add_carveout(rproc, rproc_mem); + rproc_coredump_add_segment(rproc, da, len); + + dev_dbg(&rproc->dev, "sram carveout %s addr=3D%llx, da=3D0x%x, size=3D0x= %lx", + sram->sram_res.name, dma_addr, da, len); + } + + return 0; +} + /* * tcm_mem_unmap() * @rproc: single R5 core's corresponding rproc instance @@ -669,6 +729,12 @@ static int zynqmp_r5_rproc_prepare(struct rproc *rproc) return ret; } =20 + ret =3D add_sram_carveouts(rproc); + if (ret) { + dev_err(&rproc->dev, "failed to get sram carveout %d\n", ret); + return ret; + } + return 0; } =20 @@ -695,6 +761,12 @@ static int zynqmp_r5_rproc_unprepare(struct rproc *rpr= oc) "can't turn off TCM bank 0x%x", pm_domain_id); } =20 + for (i =3D 0; i < r5_core->num_sram; i++) { + gen_pool_free(r5_core->sram[i].sram_pool, + (unsigned long)r5_core->sram[i].va, + gen_pool_size(r5_core->sram[i].sram_pool)); + } + return 0; } =20 @@ -881,6 +953,85 @@ static struct zynqmp_r5_core *zynqmp_r5_add_rproc_core= (struct device *cdev) return ERR_PTR(ret); } =20 +static int zynqmp_r5_get_sram_banks(struct zynqmp_r5_core *r5_core) +{ + struct device_node *np =3D r5_core->np; + struct device *dev =3D r5_core->dev; + struct zynqmp_sram_bank *sram; + struct device_node *sram_np; + int num_sram, i, ret; + u64 abs_addr, size; + + /* "sram" is optional property. Do not fail, if unavailable. */ + if (!of_property_present(r5_core->np, "sram")) + return 0; + + num_sram =3D of_property_count_elems_of_size(np, "sram", sizeof(phandle)); + if (num_sram <=3D 0) { + dev_err(dev, "Invalid sram property, ret =3D %d\n", + num_sram); + return -EINVAL; + } + + sram =3D devm_kcalloc(dev, num_sram, + sizeof(struct zynqmp_sram_bank), GFP_KERNEL); + if (!sram) + return -ENOMEM; + + for (i =3D 0; i < num_sram; i++) { + sram_np =3D of_parse_phandle(np, "sram", i); + if (!sram_np) { + dev_err(dev, "failed to get sram %d phandle\n", i); + ret =3D -EINVAL; + goto fail_sram_get; + } + + if (!of_device_is_available(sram_np)) { + dev_err(dev, "sram device not available\n"); + ret =3D -EINVAL; + goto fail_sram_get; + } + + ret =3D of_address_to_resource(sram_np, 0, &sram[i].sram_res); + if (ret) { + dev_err(dev, "addr to res failed\n"); + goto fail_sram_get; + } + + sram[i].sram_pool =3D of_gen_pool_get(np, "sram", i); + if (!sram[i].sram_pool) { + dev_err(dev, "failed to get sram idx %d gen pool\n", i); + ret =3D -ENOMEM; + goto fail_sram_get; + } + + /* Get SRAM device address */ + ret =3D of_property_read_reg(sram_np, i, &abs_addr, &size); + if (ret) { + dev_err(dev, "failed to get reg property\n"); + goto fail_sram_get; + } + + sram[i].da =3D (u32)abs_addr; + + of_node_put(sram_np); + + dev_dbg(dev, "sram %d: name=3D%s, addr=3D0x%llx, da=3D0x%x, size=3D0x%ll= x\n", + i, sram[i].sram_res.name, sram[i].sram_res.start, + sram[i].da, resource_size(&sram[i].sram_res)); + } + + r5_core->sram =3D sram; + r5_core->num_sram =3D num_sram; + + return 0; + +fail_sram_get: + of_node_put(sram_np); + + return ret; +} + static int zynqmp_r5_get_tcm_node_from_dt(struct zynqmp_r5_cluster *cluste= r) { int i, j, tcm_bank_count, ret, tcm_pd_idx, pd_count; @@ -1095,6 +1246,10 @@ static int zynqmp_r5_core_init(struct zynqmp_r5_clus= ter *cluster, return ret; } } + + ret =3D zynqmp_r5_get_sram_banks(r5_core); + if (ret) + return ret; } =20 return 0; base-commit: 1a491aaf1d1ce3a1cf5190394c36f21d805c7e96 --=20 2.25.1