From nobody Tue Feb 10 15:46:05 2026 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2578C15CD41; Mon, 19 Aug 2024 09:40:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724060404; cv=none; b=RwvXGBtkcKtiFqck8xOYbBg6nbUH6HLj9UXuspO6F3CfGN/z5zcetmC6UpHa7tjp1KsW/8gUgyaIkN79HWd/kBPYQirxNwSUSmtHEsMQy330n36nAqpkjXzryx2E3Nr06k3+PQFun0l0HYGejqVdsq6ix/6q8fJq1OJmHGTES2E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724060404; c=relaxed/simple; bh=NYkzJQFNrxEM89Zg9cwYhxYE7jFflIwQivm6XHVAguc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=gxcyQKHUSmY+CWrenjAKD+s31z0gylmOiWlGcA5w05ILRGfthIvdPwxqPNHtgOPDvu+t1OBwjGX0MTm/gOxXfTfU5onQoNqqcOKLelc93F0NwHxOSMvWi1DBhG2p6gaa8WsDzPI50xoystZl/yGrV1nddf2xfrkY5kp2CVB5NQI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=mqpoGZNd; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="mqpoGZNd" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 47J9dvtW054545; Mon, 19 Aug 2024 04:39:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1724060397; bh=Z/zN362q/sO5MiSJOk8sunZ8wzfq36d5Mj7oOoto6Iw=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=mqpoGZNddJskl8/7G4xbWRJ9u7A1S28+QfOj5+7uzkVDb/uYBlKh0RY7TYXJvK7Iu NZrR30kgsg/7aaTnRiRw5e+koOgNBld5Sebp6VYv3zvg5kRRR6/ABji9VBuUB8iJtV yr2S11KVBcDisksf+LoM/3pLJGsPM0Y2ZvrPyUIg= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 47J9dvrE130699 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 19 Aug 2024 04:39:57 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 19 Aug 2024 04:39:56 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 19 Aug 2024 04:39:56 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 47J9daOG082967; Mon, 19 Aug 2024 04:39:53 -0500 From: Manorit Chawdhry Date: Mon, 19 Aug 2024 15:09:38 +0530 Subject: [PATCH v4 4/5] arm64: dts: ti: Introduce J742S2 SoC family Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240819-b4-upstream-j742s2-v4-4-f2284f6f771d@ti.com> References: <20240819-b4-upstream-j742s2-v4-0-f2284f6f771d@ti.com> In-Reply-To: <20240819-b4-upstream-j742s2-v4-0-f2284f6f771d@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Udit Kumar , Neha Malcom Francis , Aniket Limaye , Beleswar Padhi , Manorit Chawdhry X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1724060376; l=5503; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=NYkzJQFNrxEM89Zg9cwYhxYE7jFflIwQivm6XHVAguc=; b=2s0Lovl7Fc2eyR5K9wfls79Gnr55l9k/FulJZeBTGFSQCH0+fR3VcWQTencWcH9gU+FQY4VHS 6/gyjSZFoDxB1nTZrmmHGnqN+xj1Wgb5+0TqPqAWuMmRt9p704yVuv+ X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 This device is a subset of J784S4 and shares the same memory map and thus the nodes are being reused from J784S4 to avoid duplication. Here are some of the salient features of the J742S2 automotive grade application processor: The J742S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive, ADAS and industrial applications requiring AI at the network edge. This SoC extends the K3 Jacinto 7 family of SoCs with focus on raising performance and integration while providing interfaces, memory architecture and compute performance for multi-sensor, high concurrency applications. Some changes that this devices has from J784S4 are: * 4x Cortex-A72 vs 8x Cortex-A72 * 3x C7x DSP vs 4x C7x DSP * 4 port ethernet switch vs 8 port ethernet switch ( Refer Table 2-1 for Device comparison with J7AHP ) Link: https://www.ti.com/lit/pdf/spruje3 (TRM) Reviewed-by: Beleswar Padhi Signed-off-by: Manorit Chawdhry --- arch/arm64/boot/dts/ti/k3-j742s2-main.dtsi | 45 ++++++++++ arch/arm64/boot/dts/ti/k3-j742s2.dtsi | 98 ++++++++++++++++++= ++++ .../arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi | 5 +- 3 files changed, 146 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j742s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j742s2-main.dtsi new file mode 100644 index 000000000000..b320c27f7afe --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j742s2-main.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree Source for J742S2 SoC Family + * + * TRM: https://www.ti.com/lit/pdf/spruje3 + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +&c71_0 { + firmware-name =3D "j742s2-c71_0-fw"; +}; + +&c71_1 { + firmware-name =3D "j742s2-c71_1-fw"; +}; + +&c71_2 { + firmware-name =3D "j742s2-c71_2-fw"; +}; + +&main_r5fss0_core0 { + firmware-name =3D "j742s2-main-r5f0_0-fw"; +}; + +&main_r5fss0_core1 { + firmware-name =3D "j742s2-main-r5f0_1-fw"; +}; + +&main_r5fss1_core0 { + firmware-name =3D "j742s2-main-r5f1_0-fw"; +}; + +&main_r5fss1_core1 { + firmware-name =3D "j742s2-main-r5f1_1-fw"; +}; + +&main_r5fss2_core0 { + firmware-name =3D "j742s2-main-r5f2_0-fw"; +}; + +&main_r5fss2_core1 { + firmware-name =3D "j742s2-main-r5f2_1-fw"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j742s2.dtsi b/arch/arm64/boot/dts/ti= /k3-j742s2.dtsi new file mode 100644 index 000000000000..7a72f82f56d6 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j742s2.dtsi @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree Source for J742S2 SoC Family + * + * TRM: https://www.ti.com/lit/pdf/spruje3 + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * + */ +#include "k3-j784s4-j742s2-common.dtsi" + +/ { + model =3D "Texas Instruments K3 J742S2 SoC"; + compatible =3D "ti,j742s2"; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a72"; + reg =3D <0x000>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&L2_0>; + }; + + cpu1: cpu@1 { + compatible =3D "arm,cortex-a72"; + reg =3D <0x001>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&L2_0>; + }; + + cpu2: cpu@2 { + compatible =3D "arm,cortex-a72"; + reg =3D <0x002>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&L2_0>; + }; + + cpu3: cpu@3 { + compatible =3D "arm,cortex-a72"; + reg =3D <0x003>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&L2_0>; + }; + }; +}; + +#include "k3-j742s2-main.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi b/arch/arm= 64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi index 958054ab1018..43fee57f0926 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Device Tree Source for J784S4 SoC Family + * Device Tree Source for J784S4 and J742S2 SoC Family * - * TRM (SPRUJ43 JULY 2022): https://www.ti.com/lit/zip/spruj52 + * TRM (j784s4) (SPRUJ43 JULY 2022): https://www.ti.com/lit/zip/spruj52 + * TRM (j742s2): https://www.ti.com/lit/pdf/spruje3 * * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti= .com/ * --=20 2.46.0