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Fri, 16 Aug 2024 06:14:52 -0700 From: Shanker Donthineni To: James Morse CC: Catalin Marinas , Shanker Donthineni , Rohit Mathew , , , Subject: [PATCH] arm_mpam: Add workaround for T241-MPAM-6 Date: Fri, 16 Aug 2024 08:14:32 -0500 Message-ID: <20240816131432.993859-1-sdonthineni@nvidia.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075F0:EE_|IA1PR12MB8359:EE_ X-MS-Office365-Filtering-Correlation-Id: 642b96cc-db51-48f0-0e4e-08dcbdf5707a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?U3Z5u3lBucu9o2RRTluDKGD1Pm5BJeZMQeBYXOOU28hKu/QsbgMgi4A9Wxzj?= =?us-ascii?Q?PBivWkH+ixdLcKUVEe1O1QDnQI/V0xlzA0iAfgnSM0IIgmh8Eghtya2pZICN?= =?us-ascii?Q?IwUO2meIxV6w4zcqmzkUiNyCBIllE2vcHALogRFToNg+X0jzEygtEMFCuLVZ?= =?us-ascii?Q?4P7BQQgKaZSwx2oH+wZJuINv8FtU6+XECzSF5pJRuRln5QxG+VKH+9aT4wtj?= =?us-ascii?Q?8H+u7lAqK3lBeSLkLQp1pmYDhpRW84T4dSxK8aE7aHcbEB+tVWEA18u62PId?= =?us-ascii?Q?ffEqk193ZJs3+x0yNcHQFWrSx6nXEU1pI3VO2xykTFgDB4ULREbWS7gXl9ua?= =?us-ascii?Q?dipW3vY5qi1RI166ydpwnxPiEsmvEXpSuPNDlKTAGPD1a8XTzHqvjd61K4yY?= =?us-ascii?Q?/e+kElxmHkC9ysxJQm2RIhjbfHLSGfy7IY/u+kA4XBv3D21PbeoZFW4HwoLh?= =?us-ascii?Q?sgBSMUBqIa00gUgevb04838yqY8wrsOhkPSb8T/l7smIl0kEy6kPzLt6ow1k?= =?us-ascii?Q?RruqedssVaUU/vb/XLRm/+6M890nHDv0IejQ6CGBmWQQjtAaj2dFYkIgfqjY?= =?us-ascii?Q?4ObBnFI5yZMl+3XMrFgKIObloMco5GJeI7sTJPC2b7VpiixqKCuAC3cOVuyM?= =?us-ascii?Q?LfvnwBtiUEvuJxHwVs42kRKVLvyU4skbl9WvTsvzamkPQ8Ww64h3p98NZ+ID?= =?us-ascii?Q?QbtwI/w3DzxjSd4S1mWtc2vBJ6D0PNSeJ9NZzUwr7P8mD0aiw18PnwMd7cf3?= =?us-ascii?Q?G1P9Buy7g0MoZG/GPqHFvcH8zpJlL7ILOK4kzXhNpaksYevvkGZWRRvOB0C9?= =?us-ascii?Q?WWyQIe4fCETkGadNRqiAaCpbRAZPGfHK+/VaqCvrnprmq5u8k5vUe6PNRDVh?= =?us-ascii?Q?+smUR4dlnB1yYxUnm/1c6eLsATx0ZSHnzvUs/60TrI4TOq4gixKvOPu/yYTp?= =?us-ascii?Q?7A0LhdHqDkAYD2IDmWUZkJItXj6CYD5DvPv0m/m4oMPXE4uNr1HglbxkaftP?= =?us-ascii?Q?QjsRQLY8EJabELghcdG1TC2uB7+5nnoykbkkTvK7rARcEx8FAqneu7nZ07O5?= =?us-ascii?Q?tWOsnDEa1dElBtOkg8b79Z++COmyZgR1tU0IScsJZ2voJNul9FuzbZyYv+at?= =?us-ascii?Q?qCt4N9vO/bA+RCaaXwupU+Wsht8OxjzHF9tGTRyqRpd4XFwSl6wPUZaTVrT5?= =?us-ascii?Q?1jMNsbskQuyOdg0QV8QnmGXGr3IoemYZV9vq98dT1gJ4aGPlP2JCQDpbr4e8?= =?us-ascii?Q?cOeRLpPtesRTWN142lwr9F4Gh8I33AWs0P7DSyjSveX4K7ppWv4CY+X+jTFe?= =?us-ascii?Q?jAK4qgZC5kLsMYB+bifrAJgeMDIaGucTOjaUjfya3sa5KRRiXUMR/vpX/1zd?= =?us-ascii?Q?b1wxKKr1Mc9gCtxLTiwOZ2oEhDus3bAVlbjTbC1WMVRLHqwOqy2VUemwyZUC?= =?us-ascii?Q?lZaR613ow/Rw7X0JsZ+3hMvhy2P06CEv?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Aug 2024 13:15:03.0514 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 642b96cc-db51-48f0-0e4e-08dcbdf5707a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075F0.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8359 Content-Type: text/plain; charset="utf-8" The registers MSMON_MBWU_L and MSMON_MBWU return the number of requests rather than the number of bytes transferred. Bandwidth resource monitoring is performed at the last level cache, where each request arrive in 64Byte granularity. The current implementation returns the number of transactions received at the last level cache but does not provide the value in bytes. Scaling by 64 gives an accurate byte count to match the MPAM specification for the MSMON_MBWU and MSMON_MBWU_L registers. This patch fixes the issue by reporting the actual number of bytes instead of the number of transactions from __ris_msmon_read(). Signed-off-by: Shanker Donthineni --- Documentation/arch/arm64/silicon-errata.rst | 2 ++ drivers/platform/arm64/mpam/mpam_devices.c | 17 +++++++++++++++-- drivers/platform/arm64/mpam/mpam_internal.h | 1 + 3 files changed, 18 insertions(+), 2 deletions(-) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/ar= ch/arm64/silicon-errata.rst index 1959013447ee1..1733875f41cd2 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -239,6 +239,8 @@ stable kernels. +----------------+-----------------+-----------------+--------------------= ---------+ | NVIDIA | T241 MPAM | T241-MPAM-4 | N/A = | +----------------+-----------------+-----------------+--------------------= ---------+ +| NVIDIA | T241 MPAM | T241-MPAM-6 | N/A = | ++----------------+-----------------+-----------------+--------------------= ---------+ +----------------+-----------------+-----------------+--------------------= ---------+ | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585= | +----------------+-----------------+-----------------+--------------------= ---------+ diff --git a/drivers/platform/arm64/mpam/mpam_devices.c b/drivers/platform/= arm64/mpam/mpam_devices.c index d0b787dc4de12..cedf2c896ef5b 100644 --- a/drivers/platform/arm64/mpam/mpam_devices.c +++ b/drivers/platform/arm64/mpam/mpam_devices.c @@ -759,6 +759,12 @@ static const struct mpam_quirk mpam_quirks[] =3D { .iidr_mask =3D IIDR_MATCH_ONE, .workaround =3D T241_FORCE_MBW_MIN_TO_ONE, }, + { + /* NVIDIA t241 erratum T241-MPAM-6 */ + .iidr =3D IIDR_PROD(0x241) | IIDR_VAR(0) | IIDR_REV(0) | IIDR_IMP(0= x36b), + .iidr_mask =3D IIDR_MATCH_ONE, + .workaround =3D T241_MBW_COUNTER_SCALE_64, + }, { NULL }, /* Sentinel */ }; =20 @@ -1262,6 +1268,9 @@ static void __ris_msmon_read(void *arg) now =3D FIELD_GET(MSMON___VALUE, now); } =20 + if (mpam_has_quirk(T241_MBW_COUNTER_SCALE_64, msc)) + now *=3D 64; + if (nrdy) break; =20 @@ -1269,8 +1278,12 @@ static void __ris_msmon_read(void *arg) break; =20 /* Add any pre-overflow value to the mbwu_state->val */ - if (mbwu_state->prev_val > now) - overflow_val =3D mpam_msmon_overflow_val(ris) - mbwu_state->prev_val; + if (mbwu_state->prev_val > now) { + overflow_val =3D mpam_msmon_overflow_val(ris); + if (mpam_has_quirk(T241_MBW_COUNTER_SCALE_64, msc)) + overflow_val *=3D 64; + overflow_val -=3D mbwu_state->prev_val; + } =20 mbwu_state->prev_val =3D now; mbwu_state->correction +=3D overflow_val; diff --git a/drivers/platform/arm64/mpam/mpam_internal.h b/drivers/platform= /arm64/mpam/mpam_internal.h index 6e43acabdcaa2..266d8a4e91905 100644 --- a/drivers/platform/arm64/mpam/mpam_internal.h +++ b/drivers/platform/arm64/mpam/mpam_internal.h @@ -237,6 +237,7 @@ static inline void mpam_clear_feature(enum mpam_device_= features feat, enum mpam_device_quirks { T241_SCRUB_SHADOW_REGS, T241_FORCE_MBW_MIN_TO_ONE, + T241_MBW_COUNTER_SCALE_64, MPAM_QUIRK_LAST, }; =20 --=20 2.25.1