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(unknown [10.28.34.254]) by maili.marvell.com (Postfix) with ESMTP id 0A9173F707D; Fri, 16 Aug 2024 03:38:24 -0700 (PDT) From: Bharat Bhushan To: , , , , , , , , , , , , , , Subject: [net PATCH] octeontx2-af: Fix CPT AF register offset calculation Date: Fri, 16 Aug 2024 16:08:22 +0530 Message-ID: <20240816103822.2091922-1-bbhushan2@marvell.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: 1KMMMTTxdoC4jnZ9SpzwfoYUgd_MxwOB X-Proofpoint-ORIG-GUID: 1KMMMTTxdoC4jnZ9SpzwfoYUgd_MxwOB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-16_02,2024-08-15_01,2024-05-17_01 Content-Type: text/plain; charset="utf-8" Some CPT AF registers are per LF and others are global. Translation of PF/VF local LF slot number to actual LF slot number is required only for accessing perf LF registers. CPT AF global registers access does not requires any LF slot number. Also there is no reason CPT PF/VF to know actual lf's register offset. Fixes: bc35e28af789 ("octeontx2-af: replace cpt slot with lf id on reg writ= e") Signed-off-by: Bharat Bhushan Reviewed-by: Simon Horman --- .../ethernet/marvell/octeontx2/af/rvu_cpt.c | 23 +++++++++---------- 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_cpt.c index 3e09d2285814..daf4b951e905 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c @@ -632,7 +632,9 @@ int rvu_mbox_handler_cpt_inline_ipsec_cfg(struct rvu *r= vu, return ret; } =20 -static bool is_valid_offset(struct rvu *rvu, struct cpt_rd_wr_reg_msg *req) +static bool validate_and_update_reg_offset(struct rvu *rvu, + struct cpt_rd_wr_reg_msg *req, + u64 *reg_offset) { u64 offset =3D req->reg_offset; int blkaddr, num_lfs, lf; @@ -663,6 +665,11 @@ static bool is_valid_offset(struct rvu *rvu, struct cp= t_rd_wr_reg_msg *req) if (lf < 0) return false; =20 + /* Translate local LF's offset to global CPT LF's offset to + * access LFX register. + */ + *reg_offset =3D (req->reg_offset & 0xFF000) + (lf << 3); + return true; } else if (!(req->hdr.pcifunc & RVU_PFVF_FUNC_MASK)) { /* Registers that can be accessed from PF */ @@ -697,7 +704,7 @@ int rvu_mbox_handler_cpt_rd_wr_register(struct rvu *rvu, struct cpt_rd_wr_reg_msg *rsp) { u64 offset =3D req->reg_offset; - int blkaddr, lf; + int blkaddr; =20 blkaddr =3D validate_and_get_cpt_blkaddr(req->blkaddr); if (blkaddr < 0) @@ -708,18 +715,10 @@ int rvu_mbox_handler_cpt_rd_wr_register(struct rvu *r= vu, !is_cpt_vf(rvu, req->hdr.pcifunc)) return CPT_AF_ERR_ACCESS_DENIED; =20 - if (!is_valid_offset(rvu, req)) + if (!validate_and_update_reg_offset(rvu, req, &offset)) return CPT_AF_ERR_ACCESS_DENIED; =20 - /* Translate local LF used by VFs to global CPT LF */ - lf =3D rvu_get_lf(rvu, &rvu->hw->block[blkaddr], req->hdr.pcifunc, - (offset & 0xFFF) >> 3); - - /* Translate local LF's offset to global CPT LF's offset */ - offset &=3D 0xFF000; - offset +=3D lf << 3; - - rsp->reg_offset =3D offset; + rsp->reg_offset =3D req->reg_offset; rsp->ret_val =3D req->ret_val; rsp->is_write =3D req->is_write; =20 --=20 2.34.1