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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240816-kvm_pmu_fixes-v1-2-cdfce386dd93@rivosinc.com> References: <20240816-kvm_pmu_fixes-v1-0-cdfce386dd93@rivosinc.com> In-Reply-To: <20240816-kvm_pmu_fixes-v1-0-cdfce386dd93@rivosinc.com> To: Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , Andrew Jones Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 The csr_fun defines a count parameter which defines the total number CSRs emulated in KVM starting from the base. This value should be equal to total number of counters possible for trap/emulation (32). Fixes: a9ac6c37521f ("RISC-V: KVM: Implement trap & emulate for hpmcounters= ") Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_vcpu_pmu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm= /kvm_vcpu_pmu.h index c309daa2d75a..1d85b6617508 100644 --- a/arch/riscv/include/asm/kvm_vcpu_pmu.h +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h @@ -65,11 +65,11 @@ struct kvm_pmu { =20 #if defined(CONFIG_32BIT) #define KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS \ -{.base =3D CSR_CYCLEH, .count =3D 31, .func =3D kvm_riscv_vcpu_pmu_read_hp= m }, \ -{.base =3D CSR_CYCLE, .count =3D 31, .func =3D kvm_riscv_vcpu_pmu_read_hpm= }, +{.base =3D CSR_CYCLEH, .count =3D 32, .func =3D kvm_riscv_vcpu_pmu_read_hp= m }, \ +{.base =3D CSR_CYCLE, .count =3D 32, .func =3D kvm_riscv_vcpu_pmu_read_hpm= }, #else #define KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS \ -{.base =3D CSR_CYCLE, .count =3D 31, .func =3D kvm_riscv_vcpu_pmu_read_hpm= }, +{.base =3D CSR_CYCLE, .count =3D 32, .func =3D kvm_riscv_vcpu_pmu_read_hpm= }, #endif =20 int kvm_riscv_vcpu_pmu_incr_fw(struct kvm_vcpu *vcpu, unsigned long fid); --=20 2.34.1