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charset="utf-8" Change maintainer: Nicolas has not been active for a while. It also makes sense for a Broadcom employee to be the maintainer as many of the details are privy to Broadcom. Also, alphabetize the compatible strings. Signed-off-by: Jim Quinlan Reviewed-by tag(s) you had gotten previously. Reviewed-by: Florian Fainelli Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Doc= umentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index 11f8ea33240c..a95760357335 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Brcmstb PCIe Host Controller =20 maintainers: - - Nicolas Saenz Julienne + - Jim Quinlan =20 properties: compatible: @@ -16,11 +16,11 @@ properties: - brcm,bcm2711-pcie # The Raspberry Pi 4 - brcm,bcm4908-pcie - brcm,bcm7211-pcie # Broadcom STB version of RPi4 - - brcm,bcm7278-pcie # Broadcom 7278 Arm - brcm,bcm7216-pcie # Broadcom 7216 Arm - - brcm,bcm7445-pcie # Broadcom 7445 Arm + - brcm,bcm7278-pcie # Broadcom 7278 Arm - brcm,bcm7425-pcie # Broadcom 7425 MIPs - brcm,bcm7435-pcie # Broadcom 7435 MIPs + - brcm,bcm7445-pcie # Broadcom 7445 Arm =20 reg: maxItems: 1 --=20 2.17.1 From nobody Fri Dec 19 16:05:41 2025 Received: from mail-pj1-f53.google.com (mail-pj1-f53.google.com [209.85.216.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5FEB1156F2B for ; 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Thu, 15 Aug 2024 15:57:47 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2d3e2e6b2d1sm373997a91.18.2024.08.15.15.57.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Aug 2024 15:57:47 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE), linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v6 02/13] dt-bindings: PCI: Use maxItems for reset controllers Date: Thu, 15 Aug 2024 18:57:15 -0400 Message-Id: <20240815225731.40276-3-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240815225731.40276-1-james.quinlan@broadcom.com> References: <20240815225731.40276-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Provide the maxItem property for the reset controllers and drop their superfluous descriptions. Signed-off-by: Jim Quinlan Reviewed-by tag(s) you had gotten previously. Reviewed-by: Florian Fainelli Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/pci/brcm,stb-pcie.yaml | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Doc= umentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index a95760357335..7d2552192153 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -95,6 +95,12 @@ properties: minItems: 1 maxItems: 3 =20 + resets: + maxItems: 1 + + reset-names: + maxItems: 1 + required: - compatible - reg @@ -118,8 +124,7 @@ allOf: then: properties: resets: - items: - - description: reset controller handling the PERST# signal + maxItems: 1 =20 reset-names: items: @@ -136,8 +141,7 @@ allOf: then: properties: resets: - items: - - description: phandle pointing to the RESCAL reset controller + maxItems: 1 =20 reset-names: items: --=20 2.17.1 From nobody Fri Dec 19 16:05:41 2025 Received: from mail-pg1-f177.google.com (mail-pg1-f177.google.com [209.85.215.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 748EB155744 for ; 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charset="utf-8" Add description for the 7712 SoC, a Broadcom STB sibling chip of the RPi 5. The 7712 uses three reset controllers: rescal, for phy reset calibration; bridge, for the bridge between the PCIe bus and the memory bus; and swinit, which is a "soft" initialization of the PCIe HW. Signed-off-by: Jim Quinlan Reviewed-by: Florian Fainelli Reviewed-by: Krzysztof Kozlowski Reviewed-by tag(s) you had gotten previously. --- .../bindings/pci/brcm,stb-pcie.yaml | 28 +++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Doc= umentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index 7d2552192153..0925c520195a 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -21,6 +21,7 @@ properties: - brcm,bcm7425-pcie # Broadcom 7425 MIPs - brcm,bcm7435-pcie # Broadcom 7435 MIPs - brcm,bcm7445-pcie # Broadcom 7445 Arm + - brcm,bcm7712-pcie # Broadcom STB sibling of Rpi 5 =20 reg: maxItems: 1 @@ -96,10 +97,12 @@ properties: maxItems: 3 =20 resets: - maxItems: 1 + minItems: 1 + maxItems: 3 =20 reset-names: - maxItems: 1 + minItems: 1 + maxItems: 3 =20 required: - compatible @@ -151,6 +154,27 @@ allOf: - resets - reset-names =20 + - if: + properties: + compatible: + contains: + const: brcm,bcm7712-pcie + then: + properties: + resets: + minItems: 3 + maxItems: 3 + + reset-names: + items: + - const: rescal + - const: bridge + - const: swinit + + required: + - resets + - reset-names + unevaluatedProperties: false =20 examples: --=20 2.17.1 From nobody Fri Dec 19 16:05:41 2025 Received: from mail-pj1-f48.google.com (mail-pj1-f48.google.com [209.85.216.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0148159571 for ; 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Thu, 15 Aug 2024 15:57:55 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2d3e2e6b2d1sm373997a91.18.2024.08.15.15.57.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Aug 2024 15:57:54 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Philipp Zabel , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v6 04/13] PCI: brcmstb: Use common error handling code in brcm_pcie_probe() Date: Thu, 15 Aug 2024 18:57:17 -0400 Message-Id: <20240815225731.40276-5-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240815225731.40276-1-james.quinlan@broadcom.com> References: <20240815225731.40276-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Refactor the error handling in the bottom half of the probe function for readability. The invocation of clk_prepare_enable() is moved lower in the function and this simplifies a couple of return paths. dev_err_probe() is also used when it is apt. Signed-off-by: Jim Quinlan Reviewed-by tag(s) you had gotten previously. Reviewed-by: Florian Fainelli Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/pcie-brcmstb.c | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index c08683febdd4..790a149f6581 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -1613,25 +1613,23 @@ static int brcm_pcie_probe(struct platform_device *= pdev) =20 pcie->ssc =3D of_property_read_bool(np, "brcm,enable-ssc"); =20 - ret =3D clk_prepare_enable(pcie->clk); - if (ret) { - dev_err(&pdev->dev, "could not enable clock\n"); - return ret; - } pcie->rescal =3D devm_reset_control_get_optional_shared(&pdev->dev, "resc= al"); - if (IS_ERR(pcie->rescal)) { - clk_disable_unprepare(pcie->clk); + if (IS_ERR(pcie->rescal)) return PTR_ERR(pcie->rescal); - } + pcie->perst_reset =3D devm_reset_control_get_optional_exclusive(&pdev->de= v, "perst"); - if (IS_ERR(pcie->perst_reset)) { - clk_disable_unprepare(pcie->clk); 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Thu, 15 Aug 2024 15:57:58 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Philipp Zabel , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v6 05/13] PCI: brcmstb: Use bridge reset if available Date: Thu, 15 Aug 2024 18:57:18 -0400 Message-Id: <20240815225731.40276-6-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240815225731.40276-1-james.quinlan@broadcom.com> References: <20240815225731.40276-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The 7712 SOC has a bridge reset which can be described in the device tree. Use it if present. Otherwise, continue to use the legacy method to reset the bridge. Signed-off-by: Jim Quinlan Reviewed-by tag(s) you had gotten previously. Reviewed-by: Florian Fainelli Reviewed-by: Manivannan Sadhasivam Reviewed-by: Stanimir Varbanov --- drivers/pci/controller/pcie-brcmstb.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index 790a149f6581..af14debd81d0 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -265,6 +265,7 @@ struct brcm_pcie { enum pcie_type type; struct reset_control *rescal; struct reset_control *perst_reset; + struct reset_control *bridge_reset; int num_memc; u64 memc_size[PCIE_BRCM_MAX_MEMC]; u32 hw_rev; @@ -732,12 +733,19 @@ static void __iomem *brcm7425_pcie_map_bus(struct pci= _bus *bus, =20 static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u= 32 val) { - u32 tmp, mask =3D RGR1_SW_INIT_1_INIT_GENERIC_MASK; - u32 shift =3D RGR1_SW_INIT_1_INIT_GENERIC_SHIFT; + if (val) + reset_control_assert(pcie->bridge_reset); + else + reset_control_deassert(pcie->bridge_reset); =20 - tmp =3D readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); - tmp =3D (tmp & ~mask) | ((val << shift) & mask); - writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); + if (!pcie->bridge_reset) { + u32 tmp, mask =3D RGR1_SW_INIT_1_INIT_GENERIC_MASK; + u32 shift =3D RGR1_SW_INIT_1_INIT_GENERIC_SHIFT; + + tmp =3D readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); + tmp =3D (tmp & ~mask) | ((val << shift) & mask); + writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); + } } =20 static void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 = val) @@ -1621,10 +1629,16 @@ static int brcm_pcie_probe(struct platform_device *= pdev) if (IS_ERR(pcie->perst_reset)) return PTR_ERR(pcie->perst_reset); =20 + pcie->bridge_reset =3D devm_reset_control_get_optional_exclusive(&pdev->d= ev, "bridge"); + if (IS_ERR(pcie->bridge_reset)) + return PTR_ERR(pcie->bridge_reset); + ret =3D clk_prepare_enable(pcie->clk); if (ret) return dev_err_probe(&pdev->dev, ret, "could not enable clock\n"); =20 + pcie->bridge_sw_init_set(pcie, 0); + ret =3D reset_control_reset(pcie->rescal); if (ret) { clk_disable_unprepare(pcie->clk); --=20 2.17.1 From nobody Fri Dec 19 16:05:41 2025 Received: from mail-pj1-f47.google.com (mail-pj1-f47.google.com [209.85.216.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B214F15B0EE for ; Thu, 15 Aug 2024 22:58:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723762684; cv=none; b=L5CwcOwXDLzc9RqVcJZY2Zan4lLzX7WE8CYYh/pjQOb6Geq40QRSdKmO7vOvERT0bYZI24MR7jM1WlJrXrrZXMRvEcEHI/8aHqOTCT1TxfU7f3DV5OCA4CHSM1JwZ6obzXkFX+VqQA4bhM1EaujZwFqSpxdogBd5+PLFLHGDaKs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723762684; c=relaxed/simple; bh=Y+MjKmHp5mUh5aY4SnwaOPwQvDeezXwzT1w3bwpZJIw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; 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charset="utf-8" The 7712 SOC adds a software init reset device for the PCIe HW. If found in the DT node, use it. Signed-off-by: Jim Quinlan Reviewed-by tag(s) you had gotten previously. Reviewed-by: Florian Fainelli Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/pcie-brcmstb.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index af14debd81d0..aa21c4c7b7f7 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -266,6 +266,7 @@ struct brcm_pcie { struct reset_control *rescal; struct reset_control *perst_reset; struct reset_control *bridge_reset; + struct reset_control *swinit_reset; int num_memc; u64 memc_size[PCIE_BRCM_MAX_MEMC]; u32 hw_rev; @@ -1633,12 +1634,35 @@ static int brcm_pcie_probe(struct platform_device *= pdev) if (IS_ERR(pcie->bridge_reset)) return PTR_ERR(pcie->bridge_reset); =20 + pcie->swinit_reset =3D devm_reset_control_get_optional_exclusive(&pdev->d= ev, "swinit"); + if (IS_ERR(pcie->swinit_reset)) + return PTR_ERR(pcie->swinit_reset); + ret =3D clk_prepare_enable(pcie->clk); if (ret) return dev_err_probe(&pdev->dev, ret, "could not enable clock\n"); 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Thu, 15 Aug 2024 15:58:05 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v6 07/13] PCI: brcmstb: PCI: brcmstb: Make HARD_DEBUG, INTR2_CPU_BASE offsets SoC-specific Date: Thu, 15 Aug 2024 18:57:20 -0400 Message-Id: <20240815225731.40276-8-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240815225731.40276-1-james.quinlan@broadcom.com> References: <20240815225731.40276-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Do prepatory work for the 7712 SoC, which is introduced in a future commit. Our HW design has changed two register offsets for the 7712, where previously it was a common value for all Broadcom SOCs with PCIe cores. Specifically, the two offsets are to the registers HARD_DEBUG and INTR2_CPU_BASE. Signed-off-by: Jim Quinlan Reviewed-by: Stanimir Varbanov Reviewed-by: Florian Fainelli Reviewed-by: Manivannan Sadhasivam Reviewed-by tag(s) you had gotten previously. --- drivers/pci/controller/pcie-brcmstb.c | 39 ++++++++++++++++----------- 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index aa21c4c7b7f7..1444f2a9c21e 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -122,7 +122,6 @@ #define PCIE_MEM_WIN0_LIMIT_HI(win) \ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8) =20 -#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK 0x200000 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 @@ -131,9 +130,9 @@ (PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK | \ PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK) =20 -#define PCIE_INTR2_CPU_BASE 0x4300 #define PCIE_MSI_INTR2_BASE 0x4500 -/* Offsets from PCIE_INTR2_CPU_BASE and PCIE_MSI_INTR2_BASE */ + +/* Offsets from INTR2_CPU and MSI_INTR2 BASE offsets */ #define MSI_INT_STATUS 0x0 #define MSI_INT_CLR 0x8 #define MSI_INT_MASK_SET 0x10 @@ -184,9 +183,11 @@ #define SSC_STATUS_PLL_LOCK_MASK 0x800 #define PCIE_BRCM_MAX_MEMC 3 =20 -#define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX]) -#define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA]) -#define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1]) +#define IDX_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_INDEX]) +#define DATA_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_DATA]) +#define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->reg_offsets[RGR1_SW_INIT_1]) +#define HARD_DEBUG(pcie) ((pcie)->reg_offsets[PCIE_HARD_DEBUG]) +#define INTR2_CPU_BASE(pcie) ((pcie)->reg_offsets[PCIE_INTR2_CPU_BASE]) =20 /* Rescal registers */ #define PCIE_DVT_PMU_PCIE_PHY_CTRL 0xc700 @@ -205,6 +206,8 @@ enum { RGR1_SW_INIT_1, EXT_CFG_INDEX, EXT_CFG_DATA, + PCIE_HARD_DEBUG, + PCIE_INTR2_CPU_BASE, }; =20 enum { @@ -651,7 +654,7 @@ static int brcm_pcie_enable_msi(struct brcm_pcie *pcie) BUILD_BUG_ON(BRCM_INT_PCI_MSI_LEGACY_NR > BRCM_INT_PCI_MSI_NR); =20 if (msi->legacy) { - msi->intr_base =3D msi->base + PCIE_INTR2_CPU_BASE; + msi->intr_base =3D msi->base + INTR2_CPU_BASE(pcie); msi->nr =3D BRCM_INT_PCI_MSI_LEGACY_NR; msi->legacy_shift =3D 24; } else { @@ -898,12 +901,12 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) /* Take the bridge out of reset */ pcie->bridge_sw_init_set(pcie, 0); =20 - tmp =3D readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + tmp =3D readl(base + HARD_DEBUG(pcie)); if (is_bmips(pcie)) tmp &=3D ~PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK; else tmp &=3D ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK; - writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + writel(tmp, base + HARD_DEBUG(pcie)); /* Wait for SerDes to be stable */ usleep_range(100, 200); =20 @@ -1072,7 +1075,7 @@ static void brcm_config_clkreq(struct brcm_pcie *pcie) } =20 /* Start out assuming safe mode (both mode bits cleared) */ - clkreq_cntl =3D readl(pcie->base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + clkreq_cntl =3D readl(pcie->base + HARD_DEBUG(pcie)); clkreq_cntl &=3D ~PCIE_CLKREQ_MASK; =20 if (strcmp(mode, "no-l1ss") =3D=3D 0) { @@ -1115,7 +1118,7 @@ static void brcm_config_clkreq(struct brcm_pcie *pcie) dev_err(pcie->dev, err_msg); mode =3D "safe"; } - writel(clkreq_cntl, pcie->base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + writel(clkreq_cntl, pcie->base + HARD_DEBUG(pcie)); =20 dev_info(pcie->dev, "clkreq-mode set to %s\n", mode); } @@ -1337,9 +1340,9 @@ static void brcm_pcie_turn_off(struct brcm_pcie *pcie) writel(tmp, base + PCIE_MISC_PCIE_CTRL); =20 /* Turn off SerDes */ - tmp =3D readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + tmp =3D readl(base + HARD_DEBUG(pcie)); u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MAS= K); - writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + writel(tmp, base + HARD_DEBUG(pcie)); =20 /* Shutdown PCIe bridge */ pcie->bridge_sw_init_set(pcie, 1); @@ -1425,9 +1428,9 @@ static int brcm_pcie_resume_noirq(struct device *dev) pcie->bridge_sw_init_set(pcie, 0); =20 /* SERDES_IDDQ =3D 0 */ - tmp =3D readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + tmp =3D readl(base + HARD_DEBUG(pcie)); u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MAS= K); - writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + writel(tmp, base + HARD_DEBUG(pcie)); =20 /* wait for serdes to be stable */ udelay(100); @@ -1499,12 +1502,16 @@ static const int pcie_offsets[] =3D { [RGR1_SW_INIT_1] =3D 0x9210, [EXT_CFG_INDEX] =3D 0x9000, [EXT_CFG_DATA] =3D 0x9004, + [PCIE_HARD_DEBUG] =3D 0x4204, + [PCIE_INTR2_CPU_BASE] =3D 0x4300, }; =20 static const int pcie_offsets_bmips_7425[] =3D { [RGR1_SW_INIT_1] =3D 0x8010, [EXT_CFG_INDEX] =3D 0x8300, [EXT_CFG_DATA] =3D 0x8304, + [PCIE_HARD_DEBUG] =3D 0x4204, + [PCIE_INTR2_CPU_BASE] =3D 0x4300, }; =20 static const struct pcie_cfg_data generic_cfg =3D { @@ -1539,6 +1546,8 @@ static const int pcie_offset_bcm7278[] =3D { [RGR1_SW_INIT_1] =3D 0xc010, [EXT_CFG_INDEX] =3D 0x9000, [EXT_CFG_DATA] =3D 0x9004, + [PCIE_HARD_DEBUG] =3D 0x4204, + [PCIE_INTR2_CPU_BASE] =3D 0x4300, }; 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charset="utf-8" Remove two constants in the driver which are no longer used: RGR1_SW_INIT_1_INIT_MASK and RGR1_SW_INIT_1_INIT_SHIFT. Signed-off-by: Jim Quinlan Reviewed-by: Stanimir Varbanov Reviewed-by: Florian Fainelli Reviewed-by: Manivannan Sadhasivam Reviewed-by tag(s) you had gotten previously. --- drivers/pci/controller/pcie-brcmstb.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index 1444f2a9c21e..51b715fbf3a9 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -210,11 +210,6 @@ enum { PCIE_INTR2_CPU_BASE, }; =20 -enum { - RGR1_SW_INIT_1_INIT_MASK, - RGR1_SW_INIT_1_INIT_SHIFT, -}; - enum pcie_type { GENERIC, BCM7425, --=20 2.17.1 From nobody Fri Dec 19 16:05:41 2025 Received: from mail-pg1-f171.google.com (mail-pg1-f171.google.com [209.85.215.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92DDB15B995 for ; Thu, 15 Aug 2024 22:58:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 15 Aug 2024 15:58:12 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v6 09/13] PCI: brcmstb: Don't conflate the reset rescal with phy ctrl Date: Thu, 15 Aug 2024 18:57:22 -0400 Message-Id: <20240815225731.40276-10-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240815225731.40276-1-james.quinlan@broadcom.com> References: <20240815225731.40276-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add a "has_phy" field indicating that the internal phy has SW control that requires configuration. Some previous chips only required the firing of the "rescal" reset controller. This change requires us to give the 7216 SoC its own cfg_data structure. Signed-off-by: Jim Quinlan Reviewed-by: Stanimir Varbanov Reviewed-by: Florian Fainelli Reviewed-by: Manivannan Sadhasivam Reviewed-by tag(s) you had gotten previously. --- drivers/pci/controller/pcie-brcmstb.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index 51b715fbf3a9..2431c5a75cde 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -222,6 +222,7 @@ enum pcie_type { struct pcie_cfg_data { const int *offsets; const enum pcie_type type; + const bool has_phy; void (*perst_set)(struct brcm_pcie *pcie, u32 val); void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); }; @@ -272,6 +273,7 @@ struct brcm_pcie { void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); struct subdev_regulators *sr; bool ep_wakeup_capable; + bool has_phy; }; =20 static inline bool is_bmips(const struct brcm_pcie *pcie) @@ -1311,12 +1313,12 @@ static int brcm_phy_cntl(struct brcm_pcie *pcie, co= nst int start) =20 static inline int brcm_phy_start(struct brcm_pcie *pcie) { - return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0; + return pcie->has_phy ? brcm_phy_cntl(pcie, 1) : 0; } =20 static inline int brcm_phy_stop(struct brcm_pcie *pcie) { - return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0; + return pcie->has_phy ? brcm_phy_cntl(pcie, 0) : 0; } =20 static void brcm_pcie_turn_off(struct brcm_pcie *pcie) @@ -1559,12 +1561,20 @@ static const struct pcie_cfg_data bcm2711_cfg =3D { .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, }; =20 +static const struct pcie_cfg_data bcm7216_cfg =3D { + .offsets =3D pcie_offset_bcm7278, + .type =3D BCM7278, + .perst_set =3D brcm_pcie_perst_set_7278, + .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_7278, + .has_phy =3D true, +}; + static const struct of_device_id brcm_pcie_match[] =3D { { .compatible =3D "brcm,bcm2711-pcie", .data =3D &bcm2711_cfg }, { .compatible =3D "brcm,bcm4908-pcie", .data =3D &bcm4908_cfg }, { .compatible =3D "brcm,bcm7211-pcie", .data =3D &generic_cfg }, { .compatible =3D "brcm,bcm7278-pcie", .data =3D &bcm7278_cfg }, - { .compatible =3D "brcm,bcm7216-pcie", .data =3D &bcm7278_cfg }, + { .compatible =3D "brcm,bcm7216-pcie", .data =3D &bcm7216_cfg }, { .compatible =3D "brcm,bcm7445-pcie", .data =3D &generic_cfg }, { .compatible =3D "brcm,bcm7435-pcie", .data =3D &bcm7435_cfg }, { .compatible =3D "brcm,bcm7425-pcie", .data =3D &bcm7425_cfg }, @@ -1612,6 +1622,7 @@ static int brcm_pcie_probe(struct platform_device *pd= ev) pcie->type =3D data->type; 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charset="utf-8" Provide support for new chips with multiple inbound windows while keeping the legacy support for the older chips. In existing chips there are three inbound windows with fixed purposes: the first was for mapping SoC internal registers, the second was for memory, and the third was for memory but with the endian swapped. Typically, only one window was used. Complicating the inbound window usage was the fact that the PCIe HW would do a baroque internal mapping of system memory, and concatenate the regions of multiple memory controllers. Newer chips such as the 7712 and Cable Modem SOCs take a step forward and drop the internal mapping while providing for multiple inbound windows. This works in concert with the dma-ranges property, where each provided range becomes an inbound window. Signed-off-by: Jim Quinlan Acked-by: Manivannan Sadhasivam Reviewed-by tag(s) you had gotten previously. Reviewed-by: Florian Fainelli Reviewed-by: Stanimir Varbanov --- drivers/pci/controller/pcie-brcmstb.c | 235 ++++++++++++++++++++------ 1 file changed, 181 insertions(+), 54 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index 2431c5a75cde..c5d3a5e9e0fc 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -75,15 +75,19 @@ #define PCIE_MEM_WIN0_HI(win) \ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 8) =20 +/* + * NOTE: You may see the term "BAR" in a number of register names used by + * this driver. The term is an artifact of when the HW core was an + * endpoint device (EP). Now it is a root complex (RC) and anywhere a + * register has the term "BAR" it is related to an inbound window. + */ + +#define PCIE_BRCM_MAX_INBOUND_WINS 16 #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c #define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f =20 -#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034 -#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f -#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038 +#define PCIE_MISC_RC_BAR4_CONFIG_LO 0x40d4 =20 -#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c -#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f =20 #define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044 #define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048 @@ -130,6 +134,10 @@ (PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK | \ PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK) =20 +#define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP 0x40ac +#define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_MASK BIT(0) +#define PCIE_MISC_UBUS_BAR4_CONFIG_REMAP 0x410c + #define PCIE_MSI_INTR2_BASE 0x4500 =20 /* Offsets from INTR2_CPU and MSI_INTR2 BASE offsets */ @@ -217,12 +225,20 @@ enum pcie_type { BCM4908, BCM7278, BCM2711, + BCM7712, +}; + +struct inbound_win { + u64 size; + u64 pci_offset; + u64 cpu_addr; }; =20 struct pcie_cfg_data { const int *offsets; const enum pcie_type type; const bool has_phy; + u8 num_inbound_wins; void (*perst_set)(struct brcm_pcie *pcie, u32 val); void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); }; @@ -274,6 +290,7 @@ struct brcm_pcie { struct subdev_regulators *sr; bool ep_wakeup_capable; bool has_phy; + u8 num_inbound_wins; }; =20 static inline bool is_bmips(const struct brcm_pcie *pcie) @@ -396,7 +413,7 @@ static void brcm_pcie_set_gen(struct brcm_pcie *pcie, i= nt gen) } =20 static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, - unsigned int win, u64 cpu_addr, + u8 win, u64 cpu_addr, u64 pcie_addr, u64 size) { u32 cpu_addr_mb_high, limit_addr_mb_high; @@ -789,23 +806,62 @@ static void brcm_pcie_perst_set_generic(struct brcm_p= cie *pcie, u32 val) writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); } =20 -static int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie, - u64 *rc_bar2_size, - u64 *rc_bar2_offset) +static void add_inbound_win(struct inbound_win *b, u8 *count, u64 size, + u64 cpu_addr, u64 pci_offset) +{ + b->size =3D size; + b->cpu_addr =3D cpu_addr; + b->pci_offset =3D pci_offset; + (*count)++; +} + +static int brcm_pcie_get_inbound_wins(struct brcm_pcie *pcie, + struct inbound_win inbound_wins[]) { struct pci_host_bridge *bridge =3D pci_host_bridge_from_priv(pcie); + u64 pci_offset, cpu_addr, size =3D 0, tot_size =3D 0; struct resource_entry *entry; struct device *dev =3D pcie->dev; u64 lowest_pcie_addr =3D ~(u64)0; int ret, i =3D 0; - u64 size =3D 0; + u8 n =3D 0; + + /* + * The HW registers (and PCIe) use order-1 numbering for BARs. As + * such, we have inbound_wins[0] unused and BAR1 starts at inbound_wins[1= ]. + */ + struct inbound_win *b_begin =3D &inbound_wins[1]; + struct inbound_win *b =3D b_begin; + + /* + * STB chips beside 7712 disable the first inbound window default. + * Rather being mapped to system memory it is mapped to the + * internal registers of the SoC. This feature is deprecated, has + * security considerations, and is not implemented in our modern + * SoCs. + */ + if (pcie->type !=3D BCM7712) + add_inbound_win(b++, &n, 0, 0, 0); =20 resource_list_for_each_entry(entry, &bridge->dma_ranges) { - u64 pcie_beg =3D entry->res->start - entry->offset; + u64 pcie_start =3D entry->res->start - entry->offset; + u64 cpu_start =3D entry->res->start; =20 - size +=3D entry->res->end - entry->res->start + 1; - if (pcie_beg < lowest_pcie_addr) - lowest_pcie_addr =3D pcie_beg; + size =3D resource_size(entry->res); + tot_size +=3D size; + if (pcie_start < lowest_pcie_addr) + lowest_pcie_addr =3D pcie_start; + /* + * 7712 and newer chips may have many BARs, with each + * offering a non-overlapping viewport to system memory. + * That being said, each BARs size must still be a power of + * two. + */ + if (pcie->type =3D=3D BCM7712) + add_inbound_win(b++, &n, size, cpu_start, pcie_start); + + if (n > pcie->num_inbound_wins) + break; } =20 if (lowest_pcie_addr =3D=3D ~(u64)0) { @@ -813,13 +869,20 @@ static int brcm_pcie_get_rc_bar2_size_and_offset(stru= ct brcm_pcie *pcie, return -EINVAL; } =20 + /* + * 7712 and newer chips do not have an internal memory mapping system + * that enables multiple memory controllers. As such, it can return + * now w/o doing special configuration. + */ + if (pcie->type =3D=3D BCM7712) + return n; + ret =3D of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", p= cie->memc_size, 1, PCIE_BRCM_MAX_MEMC); - if (ret <=3D 0) { /* Make an educated guess */ pcie->num_memc =3D 1; - pcie->memc_size[0] =3D 1ULL << fls64(size - 1); + pcie->memc_size[0] =3D 1ULL << fls64(tot_size - 1); } else { pcie->num_memc =3D ret; } @@ -828,10 +891,15 @@ static int brcm_pcie_get_rc_bar2_size_and_offset(stru= ct brcm_pcie *pcie, for (i =3D 0, size =3D 0; i < pcie->num_memc; i++) size +=3D pcie->memc_size[i]; =20 - /* System memory starts at this address in PCIe-space */ - *rc_bar2_offset =3D lowest_pcie_addr; - /* The sum of all memc views must also be a power of 2 */ - *rc_bar2_size =3D 1ULL << fls64(size - 1); + /* Our HW mandates that the window size must be a power of 2 */ + size =3D 1ULL << fls64(size - 1); + + /* + * For STB chips, the BAR2 cpu_addr is hardwired to the start + * of system memory, so we set it to 0. + */ + cpu_addr =3D 0; + pci_offset =3D lowest_pcie_addr; =20 /* * We validate the inbound memory view even though we should trust @@ -866,25 +934,90 @@ static int brcm_pcie_get_rc_bar2_size_and_offset(stru= ct brcm_pcie *pcie, * outbound memory @ 3GB). So instead it will start at the 1x * multiple of its size */ - if (!*rc_bar2_size || (*rc_bar2_offset & (*rc_bar2_size - 1)) || - (*rc_bar2_offset < SZ_4G && *rc_bar2_offset > SZ_2G)) { - dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx\n", - *rc_bar2_size, *rc_bar2_offset); + if (!size || (pci_offset & (size - 1)) || + (pci_offset < SZ_4G && pci_offset > SZ_2G)) { + dev_err(dev, "Invalid inbound_win2_offset/size: size 0x%llx, off 0x%llx\= n", + size, pci_offset); return -EINVAL; } =20 - return 0; + /* Enable inbound window 2, the main inbound window for STB chips */ + add_inbound_win(b++, &n, size, cpu_addr, pci_offset); + + /* + * Disable inbound window 3. On some chips presents the same + * window as #2 but the data appears in a settable endianness. + */ + add_inbound_win(b++, &n, 0, 0, 0); + + return n; +} + +static u32 brcm_bar_reg_offset(int bar) +{ + if (bar <=3D 3) + return PCIE_MISC_RC_BAR1_CONFIG_LO + 8 * (bar - 1); + else + return PCIE_MISC_RC_BAR4_CONFIG_LO + 8 * (bar - 4); +} + +static u32 brcm_ubus_reg_offset(int bar) +{ + if (bar <=3D 3) + return PCIE_MISC_UBUS_BAR1_CONFIG_REMAP + 8 * (bar - 1); + else + return PCIE_MISC_UBUS_BAR4_CONFIG_REMAP + 8 * (bar - 4); +} + +static void set_inbound_win_registers(struct brcm_pcie *pcie, + const struct inbound_win *inbound_wins, + u8 num_inbound_wins) +{ + void __iomem *base =3D pcie->base; + int i; + + for (i =3D 1; i <=3D num_inbound_wins; i++) { + u64 pci_offset =3D inbound_wins[i].pci_offset; + u64 cpu_addr =3D inbound_wins[i].cpu_addr; + u64 size =3D inbound_wins[i].size; + u32 reg_offset =3D brcm_bar_reg_offset(i); + u32 tmp =3D lower_32_bits(pci_offset); + + u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(size), + PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK); + + /* Write low */ + writel_relaxed(tmp, base + reg_offset); + /* Write high */ + writel_relaxed(upper_32_bits(pci_offset), base + reg_offset + 4); + + /* + * Most STB chips: + * Do nothing. + * 7712: + * All of their BARs need to be set. + */ + if (pcie->type =3D=3D BCM7712) { + /* BUS remap register settings */ + reg_offset =3D brcm_ubus_reg_offset(i); + tmp =3D lower_32_bits(cpu_addr) & ~0xfff; + tmp |=3D PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_MASK; + writel_relaxed(tmp, base + reg_offset); + tmp =3D upper_32_bits(cpu_addr); + writel_relaxed(tmp, base + reg_offset + 4); + } + } } =20 static int brcm_pcie_setup(struct brcm_pcie *pcie) { - u64 rc_bar2_offset, rc_bar2_size; + struct inbound_win inbound_wins[PCIE_BRCM_MAX_INBOUND_WINS]; void __iomem *base =3D pcie->base; struct pci_host_bridge *bridge; struct resource_entry *entry; u32 tmp, burst, aspm_support; - int num_out_wins =3D 0; - int ret, memc; + u8 num_out_wins =3D 0, num_inbound_wins =3D 0; + int memc; =20 /* Reset the bridge */ pcie->bridge_sw_init_set(pcie, 1); @@ -933,17 +1066,16 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK); writel(tmp, base + PCIE_MISC_MISC_CTRL); =20 - ret =3D brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size, - &rc_bar2_offset); - if (ret) - return ret; + num_inbound_wins =3D brcm_pcie_get_inbound_wins(pcie, inbound_wins); + if (num_inbound_wins < 0) + return num_inbound_wins; + + set_inbound_win_registers(pcie, inbound_wins, num_inbound_wins); =20 - tmp =3D lower_32_bits(rc_bar2_offset); - u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size), - PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK); - writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO); - writel(upper_32_bits(rc_bar2_offset), - base + PCIE_MISC_RC_BAR2_CONFIG_HI); + if (!brcm_pcie_rc_mode(pcie)) { + dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n"); + return -EINVAL; + } =20 tmp =3D readl(base + PCIE_MISC_MISC_CTRL); for (memc =3D 0; memc < pcie->num_memc; memc++) { @@ -965,25 +1097,12 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) * 4GB or when the inbound area is smaller than 4GB (taking into * account the rounding-up we're forced to perform). */ - if (rc_bar2_offset >=3D SZ_4G || (rc_bar2_size + rc_bar2_offset) < SZ_4G) + if (inbound_wins[2].pci_offset >=3D SZ_4G || + (inbound_wins[2].size + inbound_wins[2].pci_offset) < SZ_4G) pcie->msi_target_addr =3D BRCM_MSI_TARGET_ADDR_LT_4GB; else pcie->msi_target_addr =3D BRCM_MSI_TARGET_ADDR_GT_4GB; =20 - if (!brcm_pcie_rc_mode(pcie)) { - dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n"); - return -EINVAL; - } - - /* disable the PCIe->GISB memory window (RC_BAR1) */ - tmp =3D readl(base + PCIE_MISC_RC_BAR1_CONFIG_LO); - tmp &=3D ~PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK; - writel(tmp, base + PCIE_MISC_RC_BAR1_CONFIG_LO); - - /* disable the PCIe->SCB memory window (RC_BAR3) */ - tmp =3D readl(base + PCIE_MISC_RC_BAR3_CONFIG_LO); - tmp &=3D ~PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK; - writel(tmp, base + PCIE_MISC_RC_BAR3_CONFIG_LO); =20 /* Don't advertise L0s capability if 'aspm-no-l0s' */ aspm_support =3D PCIE_LINK_STATE_L1; @@ -1034,7 +1153,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) num_out_wins++; } =20 - /* PCIe->SCB endian mode for BAR */ + /* PCIe->SCB endian mode for inbound window */ tmp =3D readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1); u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN, PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK); @@ -1516,6 +1635,7 @@ static const struct pcie_cfg_data generic_cfg =3D { .type =3D GENERIC, .perst_set =3D brcm_pcie_perst_set_generic, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, + .num_inbound_wins =3D 3, }; =20 static const struct pcie_cfg_data bcm7425_cfg =3D { @@ -1523,6 +1643,7 @@ static const struct pcie_cfg_data bcm7425_cfg =3D { .type =3D BCM7425, .perst_set =3D brcm_pcie_perst_set_generic, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, + .num_inbound_wins =3D 3, }; =20 static const struct pcie_cfg_data bcm7435_cfg =3D { @@ -1530,6 +1651,7 @@ static const struct pcie_cfg_data bcm7435_cfg =3D { .type =3D BCM7435, .perst_set =3D brcm_pcie_perst_set_generic, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, + .num_inbound_wins =3D 3, }; =20 static const struct pcie_cfg_data bcm4908_cfg =3D { @@ -1537,6 +1659,7 @@ static const struct pcie_cfg_data bcm4908_cfg =3D { .type =3D BCM4908, .perst_set =3D brcm_pcie_perst_set_4908, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, + .num_inbound_wins =3D 3, }; =20 static const int pcie_offset_bcm7278[] =3D { @@ -1552,6 +1675,7 @@ static const struct pcie_cfg_data bcm7278_cfg =3D { .type =3D BCM7278, .perst_set =3D brcm_pcie_perst_set_7278, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_7278, + .num_inbound_wins =3D 3, }; =20 static const struct pcie_cfg_data bcm2711_cfg =3D { @@ -1559,6 +1683,7 @@ static const struct pcie_cfg_data bcm2711_cfg =3D { .type =3D BCM2711, .perst_set =3D brcm_pcie_perst_set_generic, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, + .num_inbound_wins =3D 3, }; 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Thu, 15 Aug 2024 15:58:19 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Philipp Zabel , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v6 11/13] PCI: brcmstb: Check return value of all reset_control_xxx calls Date: Thu, 15 Aug 2024 18:57:24 -0400 Message-Id: <20240815225731.40276-12-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240815225731.40276-1-james.quinlan@broadcom.com> References: <20240815225731.40276-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Always check the return value for invocations of reset_control_xxx() and propagate the error to the next level. Although the current functions in reset-brcmstb.c cannot fail, this may someday change. Signed-off-by: Jim Quinlan Reviewed-by: Stanimir Varbanov Reviewed-by: Florian Fainelli Reviewed-by tag(s) you had gotten previously. Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/pcie-brcmstb.c | 102 ++++++++++++++++++-------- 1 file changed, 73 insertions(+), 29 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index c5d3a5e9e0fc..d19eeeed623b 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -239,8 +239,8 @@ struct pcie_cfg_data { const enum pcie_type type; const bool has_phy; u8 num_inbound_wins; - void (*perst_set)(struct brcm_pcie *pcie, u32 val); - void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); + int (*perst_set)(struct brcm_pcie *pcie, u32 val); + int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); }; =20 struct subdev_regulators { @@ -285,8 +285,8 @@ struct brcm_pcie { int num_memc; u64 memc_size[PCIE_BRCM_MAX_MEMC]; u32 hw_rev; - void (*perst_set)(struct brcm_pcie *pcie, u32 val); - void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); + int (*perst_set)(struct brcm_pcie *pcie, u32 val); + int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); struct subdev_regulators *sr; bool ep_wakeup_capable; bool has_phy; @@ -749,12 +749,18 @@ static void __iomem *brcm7425_pcie_map_bus(struct pci= _bus *bus, return base + DATA_ADDR(pcie); } =20 -static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u= 32 val) +static int brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u3= 2 val) { + int ret =3D 0; + if (val) - reset_control_assert(pcie->bridge_reset); + ret =3D reset_control_assert(pcie->bridge_reset); else - reset_control_deassert(pcie->bridge_reset); + ret =3D reset_control_deassert(pcie->bridge_reset); + + if (ret) + dev_err(pcie->dev, "failed to %s 'bridge' reset, err=3D%d\n", + val ? "assert" : "deassert", ret); =20 if (!pcie->bridge_reset) { u32 tmp, mask =3D RGR1_SW_INIT_1_INIT_GENERIC_MASK; @@ -764,9 +770,11 @@ static void brcm_pcie_bridge_sw_init_set_generic(struc= t brcm_pcie *pcie, u32 val tmp =3D (tmp & ~mask) | ((val << shift) & mask); writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); } + + return ret; } =20 -static void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 = val) +static int brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 v= al) { u32 tmp, mask =3D RGR1_SW_INIT_1_INIT_7278_MASK; u32 shift =3D RGR1_SW_INIT_1_INIT_7278_SHIFT; @@ -774,20 +782,29 @@ static void brcm_pcie_bridge_sw_init_set_7278(struct = brcm_pcie *pcie, u32 val) tmp =3D readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); tmp =3D (tmp & ~mask) | ((val << shift) & mask); writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); + + return 0; } =20 -static void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val) +static int brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val) { + int ret; + if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n")) - return; + return -EINVAL; =20 if (val) - reset_control_assert(pcie->perst_reset); + ret =3D reset_control_assert(pcie->perst_reset); else - reset_control_deassert(pcie->perst_reset); + ret =3D reset_control_deassert(pcie->perst_reset); + + if (ret) + dev_err(pcie->dev, "failed to %s 'perst' reset, err=3D%d\n", + val ? "assert" : "deassert", ret); + return ret; } =20 -static void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val) +static int brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val) { u32 tmp; =20 @@ -795,15 +812,19 @@ static void brcm_pcie_perst_set_7278(struct brcm_pcie= *pcie, u32 val) tmp =3D readl(pcie->base + PCIE_MISC_PCIE_CTRL); u32p_replace_bits(&tmp, !val, PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK); writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); + + return 0; } =20 -static void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) +static int brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) { u32 tmp; =20 tmp =3D readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_PERST_MASK); writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); + + return 0; } =20 static void add_inbound_win(struct inbound_win *b, u8 *count, u64 size, @@ -1017,19 +1038,28 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) struct resource_entry *entry; u32 tmp, burst, aspm_support; u8 num_out_wins =3D 0, num_inbound_wins =3D 0; - int memc; + int memc, ret; =20 /* Reset the bridge */ - pcie->bridge_sw_init_set(pcie, 1); + ret =3D pcie->bridge_sw_init_set(pcie, 1); + if (ret) + return ret; =20 /* Ensure that PERST# is asserted; some bootloaders may deassert it. */ - if (pcie->type =3D=3D BCM2711) - pcie->perst_set(pcie, 1); + if (pcie->type =3D=3D BCM2711) { + ret =3D pcie->perst_set(pcie, 1); + if (ret) { + pcie->bridge_sw_init_set(pcie, 0); + return ret; + } + } =20 usleep_range(100, 200); =20 /* Take the bridge out of reset */ - pcie->bridge_sw_init_set(pcie, 0); + ret =3D pcie->bridge_sw_init_set(pcie, 0); + if (ret) + return ret; =20 tmp =3D readl(base + HARD_DEBUG(pcie)); if (is_bmips(pcie)) @@ -1248,7 +1278,9 @@ static int brcm_pcie_start_link(struct brcm_pcie *pci= e) int ret, i; =20 /* Unassert the fundamental reset */ - pcie->perst_set(pcie, 0); + ret =3D pcie->perst_set(pcie, 0); + if (ret) + return ret; =20 /* * Wait for 100ms after PERST# deassertion; see PCIe CEM specification @@ -1440,15 +1472,17 @@ static inline int brcm_phy_stop(struct brcm_pcie *p= cie) return pcie->has_phy ? brcm_phy_cntl(pcie, 0) : 0; } =20 -static void brcm_pcie_turn_off(struct brcm_pcie *pcie) +static int brcm_pcie_turn_off(struct brcm_pcie *pcie) { void __iomem *base =3D pcie->base; - int tmp; + int tmp, ret; =20 if (brcm_pcie_link_up(pcie)) brcm_pcie_enter_l23(pcie); /* Assert fundamental reset */ - pcie->perst_set(pcie, 1); + ret =3D pcie->perst_set(pcie, 1); + if (ret) + return ret; =20 /* Deassert request for L23 in case it was asserted */ tmp =3D readl(base + PCIE_MISC_PCIE_CTRL); @@ -1461,7 +1495,9 @@ static void brcm_pcie_turn_off(struct brcm_pcie *pcie) writel(tmp, base + HARD_DEBUG(pcie)); =20 /* Shutdown PCIe bridge */ - pcie->bridge_sw_init_set(pcie, 1); + ret =3D pcie->bridge_sw_init_set(pcie, 1); + + return ret; } =20 static int pci_dev_may_wakeup(struct pci_dev *dev, void *data) @@ -1479,9 +1515,12 @@ static int brcm_pcie_suspend_noirq(struct device *de= v) { struct brcm_pcie *pcie =3D dev_get_drvdata(dev); struct pci_host_bridge *bridge =3D pci_host_bridge_from_priv(pcie); - int ret; + int ret, rret; + + ret =3D brcm_pcie_turn_off(pcie); + if (ret) + return ret; =20 - brcm_pcie_turn_off(pcie); /* * If brcm_phy_stop() returns an error, just dev_err(). If we * return the error it will cause the suspend to fail and this is a @@ -1510,7 +1549,10 @@ static int brcm_pcie_suspend_noirq(struct device *de= v) pcie->sr->supplies); if (ret) { dev_err(dev, "Could not turn off regulators\n"); - reset_control_reset(pcie->rescal); + rret =3D reset_control_reset(pcie->rescal); + if (rret) + dev_err(dev, "failed to reset 'rascal' controller ret=3D%d\n", + rret); return ret; } } @@ -1525,7 +1567,7 @@ static int brcm_pcie_resume_noirq(struct device *dev) struct brcm_pcie *pcie =3D dev_get_drvdata(dev); void __iomem *base; u32 tmp; - int ret; + int ret, rret; =20 base =3D pcie->base; ret =3D clk_prepare_enable(pcie->clk); @@ -1587,7 +1629,9 @@ static int brcm_pcie_resume_noirq(struct device *dev) if (pcie->sr) regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies); err_reset: - reset_control_rearm(pcie->rescal); + rret =3D reset_control_rearm(pcie->rescal); + if (rret) + dev_err(pcie->dev, "failed to rearm 'rescal' reset, err=3D%d\n", rret); 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Thu, 15 Aug 2024 15:58:23 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2d3e2e6b2d1sm373997a91.18.2024.08.15.15.58.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Aug 2024 15:58:23 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v6 12/13] PCI: brcmstb: Change field name from 'type' to 'soc_base' Date: Thu, 15 Aug 2024 18:57:25 -0400 Message-Id: <20240815225731.40276-13-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240815225731.40276-1-james.quinlan@broadcom.com> References: <20240815225731.40276-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The 'type' field used in the driver to discern SoC differences is confusing; change it to the more apt 'soc_base'. The 'base' is because some SoCs have the same characteristics as previous SoCs so it is convenient to classify them in the same group. Signed-off-by: Jim Quinlan Reviewed-by tag(s) you had gotten previously. Reviewed-by: Florian Fainelli Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/pcie-brcmstb.c | 42 +++++++++++++-------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index d19eeeed623b..26e8f544da4c 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -218,7 +218,7 @@ enum { PCIE_INTR2_CPU_BASE, }; =20 -enum pcie_type { +enum pcie_soc_base { GENERIC, BCM7425, BCM7435, @@ -236,7 +236,7 @@ struct inbound_win { =20 struct pcie_cfg_data { const int *offsets; - const enum pcie_type type; + const enum pcie_soc_base soc_base; const bool has_phy; u8 num_inbound_wins; int (*perst_set)(struct brcm_pcie *pcie, u32 val); @@ -277,7 +277,7 @@ struct brcm_pcie { u64 msi_target_addr; struct brcm_msi *msi; const int *reg_offsets; - enum pcie_type type; + enum pcie_soc_base soc_base; struct reset_control *rescal; struct reset_control *perst_reset; struct reset_control *bridge_reset; @@ -295,7 +295,7 @@ struct brcm_pcie { =20 static inline bool is_bmips(const struct brcm_pcie *pcie) { - return pcie->type =3D=3D BCM7435 || pcie->type =3D=3D BCM7425; + return pcie->soc_base =3D=3D BCM7435 || pcie->soc_base =3D=3D BCM7425; } =20 /* @@ -861,7 +861,7 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pcie = *pcie, * security considerations, and is not implemented in our modern * SoCs. */ - if (pcie->type !=3D BCM7712) + if (pcie->soc_base !=3D BCM7712) add_inbound_win(b++, &n, 0, 0, 0); =20 resource_list_for_each_entry(entry, &bridge->dma_ranges) { @@ -878,7 +878,7 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pcie = *pcie, * That being said, each BARs size must still be a power of * two. */ - if (pcie->type =3D=3D BCM7712) + if (pcie->soc_base =3D=3D BCM7712) add_inbound_win(b++, &n, size, cpu_start, pcie_start); =20 if (n > pcie->num_inbound_wins) @@ -895,7 +895,7 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pcie = *pcie, * that enables multiple memory controllers. As such, it can return * now w/o doing special configuration. */ - if (pcie->type =3D=3D BCM7712) + if (pcie->soc_base =3D=3D BCM7712) return n; =20 ret =3D of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", p= cie->memc_size, 1, @@ -1018,7 +1018,7 @@ static void set_inbound_win_registers(struct brcm_pci= e *pcie, * 7712: * All of their BARs need to be set. */ - if (pcie->type =3D=3D BCM7712) { + if (pcie->soc_base =3D=3D BCM7712) { /* BUS remap register settings */ reg_offset =3D brcm_ubus_reg_offset(i); tmp =3D lower_32_bits(cpu_addr) & ~0xfff; @@ -1046,7 +1046,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) return ret; =20 /* Ensure that PERST# is asserted; some bootloaders may deassert it. */ - if (pcie->type =3D=3D BCM2711) { + if (pcie->soc_base =3D=3D BCM2711) { ret =3D pcie->perst_set(pcie, 1); if (ret) { pcie->bridge_sw_init_set(pcie, 0); @@ -1077,9 +1077,9 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) */ if (is_bmips(pcie)) burst =3D 0x1; /* 256 bytes */ - else if (pcie->type =3D=3D BCM2711) + else if (pcie->soc_base =3D=3D BCM2711) burst =3D 0x0; /* 128 bytes */ - else if (pcie->type =3D=3D BCM7278) + else if (pcie->soc_base =3D=3D BCM7278) burst =3D 0x3; /* 512 bytes */ else burst =3D 0x2; /* 512 bytes */ @@ -1676,7 +1676,7 @@ static const int pcie_offsets_bmips_7425[] =3D { =20 static const struct pcie_cfg_data generic_cfg =3D { .offsets =3D pcie_offsets, - .type =3D GENERIC, + .soc_base =3D GENERIC, .perst_set =3D brcm_pcie_perst_set_generic, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, .num_inbound_wins =3D 3, @@ -1684,7 +1684,7 @@ static const struct pcie_cfg_data generic_cfg =3D { =20 static const struct pcie_cfg_data bcm7425_cfg =3D { .offsets =3D pcie_offsets_bmips_7425, - .type =3D BCM7425, + .soc_base =3D BCM7425, .perst_set =3D brcm_pcie_perst_set_generic, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, .num_inbound_wins =3D 3, @@ -1692,7 +1692,7 @@ static const struct pcie_cfg_data bcm7425_cfg =3D { =20 static const struct pcie_cfg_data bcm7435_cfg =3D { .offsets =3D pcie_offsets, - .type =3D BCM7435, + .soc_base =3D BCM7435, .perst_set =3D brcm_pcie_perst_set_generic, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, .num_inbound_wins =3D 3, @@ -1700,7 +1700,7 @@ static const struct pcie_cfg_data bcm7435_cfg =3D { =20 static const struct pcie_cfg_data bcm4908_cfg =3D { .offsets =3D pcie_offsets, - .type =3D BCM4908, + .soc_base =3D BCM4908, .perst_set =3D brcm_pcie_perst_set_4908, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, .num_inbound_wins =3D 3, @@ -1716,7 +1716,7 @@ static const int pcie_offset_bcm7278[] =3D { =20 static const struct pcie_cfg_data bcm7278_cfg =3D { .offsets =3D pcie_offset_bcm7278, - .type =3D BCM7278, + .soc_base =3D BCM7278, .perst_set =3D brcm_pcie_perst_set_7278, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_7278, .num_inbound_wins =3D 3, @@ -1724,7 +1724,7 @@ static const struct pcie_cfg_data bcm7278_cfg =3D { =20 static const struct pcie_cfg_data bcm2711_cfg =3D { .offsets =3D pcie_offsets, - .type =3D BCM2711, + .soc_base =3D BCM2711, .perst_set =3D brcm_pcie_perst_set_generic, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, .num_inbound_wins =3D 3, @@ -1732,7 +1732,7 @@ static const struct pcie_cfg_data bcm2711_cfg =3D { =20 static const struct pcie_cfg_data bcm7216_cfg =3D { .offsets =3D pcie_offset_bcm7278, - .type =3D BCM7278, + .soc_base =3D BCM7278, .perst_set =3D brcm_pcie_perst_set_7278, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_7278, .has_phy =3D true, @@ -1789,7 +1789,7 @@ static int brcm_pcie_probe(struct platform_device *pd= ev) pcie->dev =3D &pdev->dev; pcie->np =3D np; pcie->reg_offsets =3D data->offsets; - pcie->type =3D data->type; + pcie->soc_base =3D data->soc_base; pcie->perst_set =3D data->perst_set; pcie->bridge_sw_init_set =3D data->bridge_sw_init_set; pcie->has_phy =3D data->has_phy; @@ -1867,7 +1867,7 @@ static int brcm_pcie_probe(struct platform_device *pd= ev) goto fail; =20 pcie->hw_rev =3D readl(pcie->base + PCIE_MISC_REVISION); - if (pcie->type =3D=3D BCM4908 && pcie->hw_rev >=3D BRCM_PCIE_HW_REV_3_20)= { + if (pcie->soc_base =3D=3D BCM4908 && pcie->hw_rev >=3D BRCM_PCIE_HW_REV_3= _20) { dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n"); ret =3D -ENODEV; goto fail; @@ -1882,7 +1882,7 @@ static int brcm_pcie_probe(struct platform_device *pd= ev) } } =20 - bridge->ops =3D pcie->type =3D=3D BCM7425 ? &brcm7425_pcie_ops : &brcm_pc= ie_ops; + bridge->ops =3D pcie->soc_base =3D=3D BCM7425 ? &brcm7425_pcie_ops : &brc= m_pcie_ops; bridge->sysdata =3D pcie; =20 platform_set_drvdata(pdev, pcie); --=20 2.17.1 From nobody Fri Dec 19 16:05:41 2025 Received: from mail-pg1-f172.google.com (mail-pg1-f172.google.com [209.85.215.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A97CB15E5DC for ; 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Thu, 15 Aug 2024 15:58:26 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2d3e2e6b2d1sm373997a91.18.2024.08.15.15.58.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Aug 2024 15:58:26 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v6 13/13] PCI: brcmstb: Enable 7712 SOCs Date: Thu, 15 Aug 2024 18:57:26 -0400 Message-Id: <20240815225731.40276-14-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240815225731.40276-1-james.quinlan@broadcom.com> References: <20240815225731.40276-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The Broadcom STB 7712 is the sibling chip of the RPi 5 (2712). It has one PCIe controller with a single port, supports gen2 and one lane only. The current revision of the chip is "C0" or "C1". Signed-off-by: Jim Quinlan Reviewed-by: Stanimir Varbanov Reviewed-by: Florian Fainelli Reviewed-by: Manivannan Sadhasivam Reviewed-by tag(s) you had gotten previously. --- drivers/pci/controller/pcie-brcmstb.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index 26e8f544da4c..21e692a57882 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -1203,6 +1203,10 @@ static void brcm_extend_rbus_timeout(struct brcm_pci= e *pcie) const unsigned int REG_OFFSET =3D PCIE_RGR1_SW_INIT_1(pcie) - 8; u32 timeout_us =3D 4000000; /* 4 seconds, our setting for L1SS */ =20 + /* 7712 does not have this (RGR1) timer */ + if (pcie->soc_base =3D=3D BCM7712) + return; + /* Each unit in timeout register is 1/216,000,000 seconds */ writel(216 * timeout_us, pcie->base + REG_OFFSET); } @@ -1674,6 +1678,13 @@ static const int pcie_offsets_bmips_7425[] =3D { [PCIE_INTR2_CPU_BASE] =3D 0x4300, }; =20 +static const int pcie_offset_bcm7712[] =3D { + [EXT_CFG_INDEX] =3D 0x9000, + [EXT_CFG_DATA] =3D 0x9004, + [PCIE_HARD_DEBUG] =3D 0x4304, + [PCIE_INTR2_CPU_BASE] =3D 0x4400, +}; + static const struct pcie_cfg_data generic_cfg =3D { .offsets =3D pcie_offsets, .soc_base =3D GENERIC, @@ -1739,6 +1750,14 @@ static const struct pcie_cfg_data bcm7216_cfg =3D { .num_inbound_wins =3D 3, }; =20 +static const struct pcie_cfg_data bcm7712_cfg =3D { + .offsets =3D pcie_offset_bcm7712, + .perst_set =3D brcm_pcie_perst_set_7278, + .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, + .soc_base =3D BCM7712, + .num_inbound_wins =3D 10, +}; + static const struct of_device_id brcm_pcie_match[] =3D { { .compatible =3D "brcm,bcm2711-pcie", .data =3D &bcm2711_cfg }, { .compatible =3D "brcm,bcm4908-pcie", .data =3D &bcm4908_cfg }, @@ -1748,6 +1767,7 @@ static const struct of_device_id brcm_pcie_match[] = =3D { { .compatible =3D "brcm,bcm7445-pcie", .data =3D &generic_cfg }, { .compatible =3D "brcm,bcm7435-pcie", .data =3D &bcm7435_cfg }, { .compatible =3D "brcm,bcm7425-pcie", .data =3D &bcm7425_cfg }, + { .compatible =3D "brcm,bcm7712-pcie", .data =3D &bcm7712_cfg }, {}, }; =20 --=20 2.17.1