From nobody Fri Dec 19 17:36:43 2025 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9FAA11509B3; Thu, 15 Aug 2024 20:48:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723754929; cv=none; b=UGNapMuayekyoJ9yecccS+Q2pxCiZxGLDcoYn25rZjwTRPUtHvIq0o2jt38rd0sMXXrEynPDjpyjVFy0VQH0pxYP9hYdPcc+fzlnu3OYfAqlvHc+kP6mI2InizIcWdKTHozENfr3mlCrt2FaseWzuavaQXgJBG8UyUH3GMbJ500= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723754929; c=relaxed/simple; bh=DjvcODVa36PD5tIpejpyd0j3hTPNkkdJi8wm0TBF3sY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=AR/0eHQ3bhu33N8m6mDekGFjo2uylEeuVZq38zp7dUll+QsCYAuB4HHijyyyuqWO6cwVNdtnoxqz03NkI4RJc7rFsITqJcuoHdPv2emx2ZigJlhtwgM2gUfSUG7+MfpNEPZuY/ETkmER/A4ad9CUNh1Dm9OXrPP7FOwpOQtu4MM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=ytGYOxCR; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="ytGYOxCR" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 47FKmaL4003236; Thu, 15 Aug 2024 15:48:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1723754916; bh=3vcli9GYNl3poZfw8KxDHbq0ijONEPHH3B2yuubFTvQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ytGYOxCRBjtsTRqU332yLHZ14TKzts4fresJaySBT4gS+GXzfRoWpxAHgoxhBdnLs AYmWkrlUmK7BTFy2hDaeUJflD+hA8mZEJHpmLNNYQ4jBRrzvtM5wxcu/O7D3pNbEpl 2xt7tn4Tn+mJrI68EF4jt80qPIkGfUmKyVEnl0ns= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 47FKmakS059136 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 15 Aug 2024 15:48:36 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 15 Aug 2024 15:48:36 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 15 Aug 2024 15:48:36 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 47FKmYNt052918; Thu, 15 Aug 2024 15:48:36 -0500 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon CC: Vignesh Raghavendra , , , Jan Kiszka , , Judith Mendez Subject: [PATCH v3 1/6] arm64: dts: ti: k3-am62a: Add ESM nodes Date: Thu, 15 Aug 2024 15:48:28 -0500 Message-ID: <20240815204833.452132-2-jm@ti.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240815204833.452132-1-jm@ti.com> References: <20240815204833.452132-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" Add Error Signaling Module (ESM) instances in MCU and MAIN domains, set ESM interrupt sources for rti as per TRM [0] 10.4 Interrupt Sources. Add comments to describe what interrupt sources are routed to ESM modules. [0] https://www.ti.com/lit/ug/spruj16b/spruj16b.pdf Signed-off-by: Judith Mendez Reviewed-by: Bryan Brattlof --- Changes since v2: - No change --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 8 ++++++++ arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-am62a-main.dtsi index 916fcf3cc57d1..8c35293c3d2b0 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -265,6 +265,14 @@ main_pmx0: pinctrl@f4000 { pinctrl-single,function-mask =3D <0xffffffff>; }; =20 + main_esm: esm@420000 { + compatible =3D "ti,j721e-esm"; + reg =3D <0x0 0x420000 0x0 0x1000>; + /* Interrupt sources: rti0, rti1, wrti0, rti4, rti2, rti3 */ + ti,esm-pins =3D <192>, <193>, <195>, <204>, <209>, <210>; + bootph-pre-ram; + }; + main_timer0: timer@2400000 { compatible =3D "ti,am654-timer"; reg =3D <0x00 0x2400000 0x00 0x400>; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts= /ti/k3-am62a-mcu.dtsi index 8c36e56f41388..a5ca4ce523a46 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi @@ -15,6 +15,14 @@ mcu_pmx0: pinctrl@4084000 { status =3D "disabled"; }; =20 + mcu_esm: esm@4100000 { + compatible =3D "ti,j721e-esm"; + reg =3D <0x0 0x4100000 0x0 0x1000>; + /* Interrupt sources: esm0_cfg, esm0_hi, esm0_low, mrti0 */ + ti,esm-pins =3D <0>, <1>, <2>, <85>; + bootph-pre-ram; + }; + /* * The MCU domain timer interrupts are routed only to the ESM module, * and not currently available for Linux. The MCU domain timers are --=20 2.46.0 From nobody Fri Dec 19 17:36:43 2025 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78B9D158D8D; Thu, 15 Aug 2024 20:48:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723754937; cv=none; b=F5PKOmVagMXjl/9ghHOAE6dXxGvaNCl8SjBJeanvSDcgUJ/QPpAnlhxdWJnWjli0+Q81MbhZA/gKEElOjYlPCUbyIYPlaELb0WdKJl2ANLD7XuGsJ18oj7T4A0FF/etIgg/9dezeYAgeBi0Yix/G7i+REQJVH8XQirJDMCv7AM8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723754937; c=relaxed/simple; bh=zOBYgcs2EVfcecneLisIk22+4KskCx2srflsyjtoMnA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ZDb9jy89XqFzTvIeD8HKHZttj+iJLIdnuw3FS2OafQ9ROiVaGep7jXuVECaVqYGIOH3jY25pDXcPq7qZxzZ6+wzTSkfx9HiTbhbvm8leBqUok76GWeKxWK6Yx4d1vEBMrLL8W2aEHfI5ZMSx0atVvQ/U3KMuxmY3wE91ADYxvdM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=XjOUe1i1; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="XjOUe1i1" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 47FKmbKA122614; Thu, 15 Aug 2024 15:48:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1723754917; bh=uINUYXIuZ/Fint00oG+vQ2OvoBRG3vBZRTLyRqn2Hak=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=XjOUe1i16S0CIJNfPoL2frimmOxJ424HbHXFv9ABGT/ePa8rBYjSsWQtfOElYkKuk zVc2vZ8EooS2Yhl4kQEay46CVvCyQAszpf/Yh4+9sKoEN1KYHQwjwDzDst4aGDbLI9 bck0/IlkPDqBoF0FdevqfY6BC/H13qP2NIz6T5Bw= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 47FKmb3Y005545 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 15 Aug 2024 15:48:37 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 15 Aug 2024 15:48:36 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 15 Aug 2024 15:48:36 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 47FKmYNu052918; Thu, 15 Aug 2024 15:48:36 -0500 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon CC: Vignesh Raghavendra , , , Jan Kiszka , , Judith Mendez Subject: [PATCH v3 2/6] arm64: dts: ti: k3-am62p: Fix ESM interrupt sources Date: Thu, 15 Aug 2024 15:48:29 -0500 Message-ID: <20240815204833.452132-3-jm@ti.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240815204833.452132-1-jm@ti.com> References: <20240815204833.452132-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" Fix interrupt sources for rti routed to the ESM0 as per [0], in 10.4 Interrupt Sources Add comments to describe what interrupt sources are routed to ESM modules. [0] https://www.ti.com/lit/ug/spruj83/spruj83.pdf Fixes: b5080c7c1f7e ("arm64: dts: ti: k3-am62p: Add nodes for more IPs") Signed-off-by: Judith Mendez Reviewed-by: Bryan Brattlof --- Changes since v2: - No change --- arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 3 ++- arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi | 5 +++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/= arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi index 9701fc69aed94..7941aab09cf72 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi @@ -260,7 +260,8 @@ main_pmx0: pinctrl@f4000 { main_esm: esm@420000 { compatible =3D "ti,j721e-esm"; reg =3D <0x00 0x420000 0x00 0x1000>; - ti,esm-pins =3D <160>, <161>, <162>, <163>, <177>, <178>; + /* Interrupt sources: rti0, rti1, wrti0 rti2, rti3, rti15 */ + ti,esm-pins =3D <224>, <225>, <227>, <241>, <242>, <248>; bootph-pre-ram; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi b/arch/a= rm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi index df7945156397b..49dda340752aa 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi @@ -26,9 +26,10 @@ mcu_pmx_range: gpio-range { mcu_esm: esm@4100000 { compatible =3D "ti,j721e-esm"; reg =3D <0x00 0x4100000 0x00 0x1000>; - ti,esm-pins =3D <0>, <1>, <2>, <85>; - status =3D "reserved"; + /* Interrupt sources: esm0_cfg, esm0_hi, esm0_low, mrti0, wrti0 */ + ti,esm-pins =3D <0>, <1>, <2>, <85>, <86>; bootph-pre-ram; + status =3D "reserved"; }; =20 /* --=20 2.46.0 From nobody Fri Dec 19 17:36:43 2025 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A509158A04; Thu, 15 Aug 2024 20:48:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" From: Santhosh Kumar K Remove 'reserved' status for MCU ESM node. Watchdog reset is propagated through ESM0 to MCU ESM to reset the CPU, so enable MCU ESM to reset the CPU with watchdog timeout. Signed-off-by: Santhosh Kumar K [Judith: Fix commit message] Signed-off-by: Judith Mendez Reviewed-by: Bryan Brattlof --- Changes since v2: - No change --- arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi b/arch/a= rm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi index 49dda340752aa..625d353b97600 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi @@ -29,7 +29,6 @@ mcu_esm: esm@4100000 { /* Interrupt sources: esm0_cfg, esm0_hi, esm0_low, mrti0, wrti0 */ ti,esm-pins =3D <0>, <1>, <2>, <85>, <86>; bootph-pre-ram; - status =3D "reserved"; }; =20 /* --=20 2.46.0 From nobody Fri Dec 19 17:36:43 2025 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A60D11509B4; Thu, 15 Aug 2024 20:48:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723754930; cv=none; b=Xs3qZ4g/5he1yrBPr+ikYixPk3TgoaO+e4/39p4bP9/IFoo3iHajzty+xMIK7d06DdLmF1zgXPexsZcXuwv7wffsr704j9E3WVMjRIcFnsnrIwnxhqo3NIcDvnU1dcc68+ys1lyhbDBb/HR0klkbS3X07Kcyr5gTCLTuckt2Bbw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723754930; c=relaxed/simple; bh=oofLex9rJdW6vnZOOwntax3i7fEbiuwRzCu5H1eKyLI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mW6S/i7fShmh4W2EOAOhGWxGxdEe4AnF1LbUmj2I9FIEdrtZCnrcN65j6V+OwgPa+R+kXTUlaXtO3ENzh3jDuF//zy7ea2bzI6lygiDzZEawdU0KiLxPb6VAKyWFYtLjrnExbBvijHI4nv1FpHz3F9t7pZweyZma8frcHPCA89s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=c9vYpOEw; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="c9vYpOEw" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 47FKmcVa003241; Thu, 15 Aug 2024 15:48:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1723754918; bh=87JlDhGfQUoLEZskO1JKgmyxXqWPGSlk8GWSd1u5cLY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=c9vYpOEwrn4VLf21aj1vbo6gXaGnupViMvHvSq56/p4XIwW4zOZxUhtS/zsuLLEvz xR+WgXpXnwPfw1mdWu50tMFWvvnIrWLzCC86VZ5kDjg98avVZKD2ReRcPjz8QCT97G s0ANSjFx24Ue+rgoq0iEDiAO2cQdN4dgCEW2+dPM= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 47FKmcNS011977 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 15 Aug 2024 15:48:38 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 15 Aug 2024 15:48:38 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 15 Aug 2024 15:48:37 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 47FKmYNw052918; Thu, 15 Aug 2024 15:48:38 -0500 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon CC: Vignesh Raghavendra , , , Jan Kiszka , , Judith Mendez Subject: [PATCH v3 4/6] arm64: dts: ti: k3-am62: Add comments to ESM nodes Date: Thu, 15 Aug 2024 15:48:31 -0500 Message-ID: <20240815204833.452132-5-jm@ti.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240815204833.452132-1-jm@ti.com> References: <20240815204833.452132-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" Add comments to describe what interrupt sources are routed to ESM modules. There is no functional change. Signed-off-by: Judith Mendez Reviewed-by: Bryan Brattlof --- Changes since v2: - No change --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am62-main.dtsi index 328929c740dc0..5b92aef5b284b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -241,6 +241,7 @@ main_esm: esm@420000 { bootph-pre-ram; compatible =3D "ti,j721e-esm"; reg =3D <0x00 0x420000 0x00 0x1000>; + /* Interrupt sources: rti0, rti1, rti15, wrti0, rti2, rti3 */ ti,esm-pins =3D <160>, <161>, <162>, <163>, <177>, <178>; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi b/arch/arm64/boot/dts/= ti/k3-am62-mcu.dtsi index e66d486ef1f21..bb43a411f59b2 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi @@ -19,6 +19,7 @@ mcu_esm: esm@4100000 { bootph-pre-ram; compatible =3D "ti,j721e-esm"; reg =3D <0x00 0x4100000 0x00 0x1000>; + /* Interrupt sources: esm0_cfg, esm0_hi, esm0_low, mrti0 */ ti,esm-pins =3D <0>, <1>, <2>, <85>; }; =20 --=20 2.46.0 From nobody Fri Dec 19 17:36:43 2025 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16CCE155730; Thu, 15 Aug 2024 20:48:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723754931; cv=none; b=fg2RMwRio85iM/WBlk1x+HkflS0PQ2HpUoOg+tnzukvKntzIYvkLkDnZxBoxEm+Zuw5Jl4umk2gl13hSdRyXkSLQR6Nquumz8nYXtj/kJfkEmZob243t3jRZP8Au/D7ixGhvgVHNKoFj83cn+yWh+/xGrbrcGbXLTG2zCNqdlT0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723754931; c=relaxed/simple; bh=rZAiY+7ECZqrw/h0erS+9Q2CWbK+GcwYrv18F5uxbBA=; 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Thu, 15 Aug 2024 15:48:38 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 47FKmYNx052918; Thu, 15 Aug 2024 15:48:38 -0500 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon CC: Vignesh Raghavendra , , , Jan Kiszka , , Judith Mendez Subject: [PATCH v3 5/6] arm64: dts: ti: k3-am64: Add more ESM interrupt sources Date: Thu, 15 Aug 2024 15:48:32 -0500 Message-ID: <20240815204833.452132-6-jm@ti.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240815204833.452132-1-jm@ti.com> References: <20240815204833.452132-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" Add ESM interrupt sources for rti as per TRM [0] in 9.4 Interrupt Sources. [0] https://www.ti.com/lit/ug/spruim2h/spruim2h.pdf Signed-off-by: Judith Mendez Reviewed-by: Bryan Brattlof --- Changes since v2: - No change --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 3 ++- arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am64-main.dtsi index f8370dd033502..652653bb24f26 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -389,7 +389,8 @@ main_esm: esm@420000 { bootph-pre-ram; compatible =3D "ti,j721e-esm"; reg =3D <0x00 0x420000 0x00 0x1000>; - ti,esm-pins =3D <160>, <161>; + /* Interrupt sources: rti0, rti1, rti8, rti9, rti10, rti11 */ + ti,esm-pins =3D <160>, <161>, <162>, <163>, <164>, <165>; }; =20 main_uart0: serial@2800000 { diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/= ti/k3-am64-mcu.dtsi index ec17285869da6..ad4bed5d3f9eb 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi @@ -158,6 +158,7 @@ mcu_esm: esm@4100000 { bootph-pre-ram; compatible =3D "ti,j721e-esm"; reg =3D <0x00 0x4100000 0x00 0x1000>; - ti,esm-pins =3D <0>, <1>; + /* Interrupt sources: esm0_cfg, esm0_hi, esm0_low, mrti0 */ + ti,esm-pins =3D <0>, <1>, <2>, <85>; }; }; --=20 2.46.0 From nobody Fri Dec 19 17:36:43 2025 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00545155A30; Thu, 15 Aug 2024 20:48:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723754932; cv=none; b=ht3rGso33yms0y0dXDYnxhOUTRNIdCg+KatRwY6T37fGZzyapz5JzVanEENOQ3thHtMUxcQhYs1ZxwS85Hkchvz5R30oZKa6wtDys08teogp9q5+52QFLoZr/G26cAZfg0605YMsfVUiGuGB5Nwcb5gekVZxEBeN1b3NR+DLSxE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723754932; c=relaxed/simple; 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Thu, 15 Aug 2024 15:48:40 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 47FKmYO0052918; Thu, 15 Aug 2024 15:48:40 -0500 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon CC: Vignesh Raghavendra , , , Jan Kiszka , , Judith Mendez Subject: [PATCH v3 6/6] arm64: dts: ti: k3-am65: Add ESM nodes Date: Thu, 15 Aug 2024 15:48:33 -0500 Message-ID: <20240815204833.452132-7-jm@ti.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240815204833.452132-1-jm@ti.com> References: <20240815204833.452132-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" Add Error Signaling Module (ESM) instances in MCU and MAIN domains, set ESM interrupt sources for rti as per TRM [0] 9.4 Interrupt Sources. There are no ESM0_ESM_INT* events routed to MCU ESM, so it is not possible to reset the CPU using watchdog and ESM0 configuration. However add ESM instances for device completion. Add comments to describe what interrupt sources are routed to ESM modules. [0] https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf Signed-off-by: Judith Mendez Reviewed-by: Bryan Brattlof --- Changes since v2: - Fix commit message for patch 6/6 --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 8 ++++++++ arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am65-main.dtsi index 1af3dedde1f67..07c9f043dac0b 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -54,6 +54,14 @@ gic_its: msi-controller@1820000 { }; }; =20 + main_esm: esm@700000 { + compatible =3D "ti,j721e-esm"; + reg =3D <0x00 0x700000 0x00 0x1000>; + /* Interrupt sources: rti0, rti1, rti2, rti3 */ + ti,esm-pins =3D <224>, <225>, <226>, <227>; + bootph-pre-ram; + }; + serdes0: serdes@900000 { compatible =3D "ti,phy-am654-serdes"; reg =3D <0x0 0x900000 0x0 0x2000>; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/= ti/k3-am65-mcu.dtsi index 43c6118d2bf0f..e10cb9f483698 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -440,6 +440,14 @@ mcu_r5fss0_core1: r5f@41400000 { }; }; =20 + mcu_esm: esm@40800000 { + compatible =3D "ti,j721e-esm"; + reg =3D <0x00 0x40800000 0x00 0x1000>; + /* Interrupt sources: mrti0, mrti1 */ + ti,esm-pins =3D <104>, <105>; + bootph-pre-ram; + }; + mcu_rti1: watchdog@40610000 { compatible =3D "ti,j7-rti-wdt"; reg =3D <0x0 0x40610000 0x0 0x100>; --=20 2.46.0