From nobody Sat Feb 7 05:49:31 2026 Received: from mickerik.phytec.de (mickerik.phytec.de [91.26.50.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5CF151714C0 for ; Thu, 15 Aug 2024 11:32:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.26.50.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723721565; cv=none; b=G18Yvnt7Sivjb/yUTyq9nQUttJAXLBUSr7uBNBOySdsj49B2OCDVrmcutC3bzH7hbFFtOWcs727GvTIL9PP7bxyFG+3QpUzHY1NcRnLC/HBgERKNnRV0LIx0GXNUeyaspWIazCOFV5QIF2CZ8AD/z4iWm0IwQVwVCQRe55AezhA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723721565; c=relaxed/simple; bh=pCAr7LzPRJpBSpOND0OK/TVOvncaQwCo+as3ES+VTmA=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=ZRSwK0gZlxZ3YTqZi+RaE1wAH5MWRA7gkhT+6lFcQbk+Ug9GRorM5YP6sOE2Jf9SPbrJmKIdqjmfO9uxYeJTf57zw/82TO73ZPWihmVuTRHZF5rfrsv9/Ko9gkrk8fy+WTzRftrlOOKWrW9oIW/Nf3KSgO7a5BsiPwx6HTW9Q1E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=phytec.de; spf=pass smtp.mailfrom=phytec.de; dkim=pass (1024-bit key) header.d=phytec.de header.i=@phytec.de header.b=ZVUEjPTI; arc=none smtp.client-ip=91.26.50.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=phytec.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=phytec.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=phytec.de header.i=@phytec.de header.b="ZVUEjPTI" DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a4; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1723721551; x=1726313551; h=From:Sender:Reply-To:Subject:Date:Message-ID:To:CC:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=pCAr7LzPRJpBSpOND0OK/TVOvncaQwCo+as3ES+VTmA=; b=ZVUEjPTINfR8y68X6TG8UQmN1pe2t0EZAM/Gh1ZP9XsvsO8fGSk7RfmTlznco0rv 0/34k7d+wpRxxmrwBsS2zoyG4iWw1F0Fjz2RDlnmVsBfrgyOgk0fCLXsCNsIvO/F JgcRzXX4Fb81YxTfkyNd1QRX62OEpfD9EBxCFLmpHe4=; X-AuditID: ac14000a-03e52700000021bc-dd-66bde74fd287 Received: from berlix.phytec.de (Unknown_Domain [172.25.0.12]) (using TLS with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client did not present a certificate) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id 7C.2B.08636.F47EDB66; Thu, 15 Aug 2024 13:32:31 +0200 (CEST) Received: from augenblix2.phytec.de (172.25.0.11) by Berlix.phytec.de (172.25.0.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.6; Thu, 15 Aug 2024 13:32:31 +0200 From: Wadim Egorov To: , , , CC: , , , , , Subject: [PATCH v2] arm64: dts: ti: am642-phyboard-electra: Add PRU-ICSSG nodes Date: Thu, 15 Aug 2024 13:32:11 +0200 Message-ID: <20240815113212.3720403-1-w.egorov@phytec.de> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: Berlix.phytec.de (172.25.0.12) To Berlix.phytec.de (172.25.0.12) X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrBLMWRmVeSWpSXmKPExsWyRpKBR9f/+d40g8WfJC3W7D3HZDH/yDlW i+WfZ7NbvJx1j81i0+NrrBaXd81hs3jz4yyTxf89O9gtut+pW/w/+4Hdgctj06pONo/NS+o9 +rtbWD2O39jO5PF5k1wAaxSXTUpqTmZZapG+XQJXRsOaI0wFK2wr1p6NaWB8Y9jFyMkhIWAi ce7FW8YuRi4OIYElTBIvZ11ng3AeM0q8nP2VHaSKTUBd4s6Gb6wgCRGBNkaJWWuusYAkmAUq JaZ0XwErEhbwl2jue8AIYrMIqEqcatzHCmLzClhKTL8+jRlinbzEzEvf2SHighInZz6BmiMv 0bx1NjOELSFx8MULMFsIKP7i0nIWmN5p515DzQmV2PplO9MERoFZSEbNQjJqFpJRCxiZVzEK 5WYmZ6cWZWbrFWRUlqQm66WkbmIEhb4IA9cOxr45HocYmTgYDzFKcDArifAGmuxKE+JNSays Si3Kjy8qzUktPsQozcGiJM67uiM4VUggPbEkNTs1tSC1CCbLxMEp1cC4n1P2kOuO7w13nMvt kldfuHfXT2Tejy67m31680QrjCtmFsWvu7Ci9YuVjRBvxJLngle3zjrHtvrO1R91/yrlmOR7 NnZaLfNfbpn0NeQi+/QpE193fU4NWP7y/4dfoXUPN9tnp6/9FJZf8XX/oUfi3sFBujXZZuyC L//92lyTrbZoFpvn2ndrlFiKMxINtZiLihMB49p4jWsCAAA= Content-Type: text/plain; charset="utf-8" The phyBOARD-Electra implements two Ethernet ports utilizing PRUs. Add configuration for both mac ports & PHYs. Signed-off-by: Wadim Egorov --- v2:=20 - Style fixes according to dts-coding-style - Moved vendor-specific properties & status to the end - Separated pinctrl array of phandles using <> --- .../dts/ti/k3-am642-phyboard-electra-rdk.dts | 146 ++++++++++++++++++ 1 file changed, 146 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arc= h/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts index 30729b49dd69..60285d736e07 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts @@ -28,6 +28,8 @@ / { model =3D "PHYTEC phyBOARD-Electra-AM64x RDK"; =20 aliases { + ethernet1 =3D &icssg0_emac0; + ethernet2 =3D &icssg0_emac1; mmc1 =3D &sdhci1; serial2 =3D &main_uart0; serial3 =3D &main_uart1; @@ -55,6 +57,73 @@ can_tc2: can-phy1 { standby-gpios =3D <&main_gpio0 35 GPIO_ACTIVE_HIGH>; }; =20 + /* Dual Ethernet application node on PRU-ICSSG0 */ + ethernet { + compatible =3D "ti,am642-icssg-prueth"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&icssg0_rgmii1_pins_default>, <&icssg0_rgmii2_pins_defaul= t>; + + interrupt-parent =3D <&icssg0_intc>; + interrupts =3D <24 0 2>, <25 1 3>; + interrupt-names =3D "tx_ts0", "tx_ts1"; + + sram =3D <&oc_sram>; + firmware-name =3D "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; + + dmas =3D <&main_pktdma 0xc100 15>, /* egress slice 0 */ + <&main_pktdma 0xc101 15>, /* egress slice 0 */ + <&main_pktdma 0xc102 15>, /* egress slice 0 */ + <&main_pktdma 0xc103 15>, /* egress slice 0 */ + <&main_pktdma 0xc104 15>, /* egress slice 1 */ + <&main_pktdma 0xc105 15>, /* egress slice 1 */ + <&main_pktdma 0xc106 15>, /* egress slice 1 */ + <&main_pktdma 0xc107 15>, /* egress slice 1 */ + <&main_pktdma 0x4100 15>, /* ingress slice 0 */ + <&main_pktdma 0x4101 15>; /* ingress slice 1 */ + dma-names =3D "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1"; + + ti,prus =3D <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>, <&rtu0_1>, <&= tx_pru0_1>; + ti,pruss-gp-mux-sel =3D <2>, /* MII mode */ + <2>, + <2>, + <2>, /* MII mode */ + <2>, + <2>; + + ti,mii-g-rt =3D <&icssg0_mii_g_rt>; + ti,mii-rt =3D <&icssg0_mii_rt>; + ti,iep =3D <&icssg0_iep0>, <&icssg0_iep1>; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + icssg0_emac0: port@0 { + reg =3D <0>; + phy-handle =3D <&icssg0_phy1>; + phy-mode =3D "rgmii-id"; + /* Filled in by bootloader */ + local-mac-address =3D [00 00 00 00 00 00]; + ti,syscon-rgmii-delay =3D <&main_conf 0x4100>; + }; + + icssg0_emac1: port@1 { + reg =3D <1>; + phy-handle =3D <&icssg0_phy2>; + phy-mode =3D "rgmii-id"; + /* Filled in by bootloader */ + local-mac-address =3D [00 00 00 00 00 00]; + ti,syscon-rgmii-delay =3D <&main_conf 0x4104>; + }; + }; + }; + keys { compatible =3D "gpio-keys"; autorepeat; @@ -118,6 +187,12 @@ AM64X_IOPAD(0x0090, PIN_OUTPUT, 7) /* (P17) GPMC0_BE0n= _CLE.GPIO0_35 */ >; }; =20 + clkout0_pins_default: clkout0-default-pins { + pinctrl-single,pins =3D < + AM64X_IOPAD(0x0274, PIN_OUTPUT, 5) /* (A19) EXT_REFCLK1.CLKOUT0 */ + >; + }; + gpio_keys_pins_default: gpio-keys-default-pins { pinctrl-single,pins =3D < AM64X_IOPAD(0x0044, PIN_INPUT, 7) /* (T18) GPMC0_AD2.GPIO0_17 */ @@ -125,6 +200,49 @@ AM64X_IOPAD(0x0054, PIN_INPUT, 7) /* (V20) GPMC0_AD6.G= PIO0_21 */ >; }; =20 + icssg0_mdio_pins_default: icssg0-mdio-default-pins { + pinctrl-single,pins =3D < + AM64X_IOPAD(0x0200, PIN_INPUT, 0) /* (P2) PRG0_MDIO0_MDIO */ + AM64X_IOPAD(0x0204, PIN_OUTPUT, 0) /* (P3) PRG0_MDIO0_MDC */ + AM64X_IOPAD(0x01A8, PIN_OUTPUT, 7) /* (V1) PRG0_PRU0_GPO18.GPIO1_18 */ + AM64X_IOPAD(0x01AC, PIN_OUTPUT, 7) /* (W1) PRG0_PRU0_GPO19.GPIO1_19 */ + >; + }; + + icssg0_rgmii1_pins_default: icssg0-rgmii1-default-pins { + pinctrl-single,pins =3D < + AM64X_IOPAD(0x0160, PIN_INPUT, 2) /* (Y1) PRG0_PRU0_GPO0.PRG0_RGMII1_RD= 0 */ + AM64X_IOPAD(0x0164, PIN_INPUT, 2) /* (R4) PRG0_PRU0_GPO1.PRG0_RGMII1_RD= 1 */ + AM64X_IOPAD(0x0168, PIN_INPUT, 2) /* (U2) PRG0_PRU0_GPO2.PRG0_RGMII1_RD= 2 */ + AM64X_IOPAD(0x016c, PIN_INPUT, 2) /* (V2) PRG0_PRU0_GPO3.PRG0_RGMII1_RD= 3 */ + AM64X_IOPAD(0x0170, PIN_INPUT, 2) /* (AA2) PRG0_PRU0_GPO4.PRG0_RGMII1_R= X_CTL */ + AM64X_IOPAD(0x0178, PIN_INPUT, 2) /* (T3) PRG0_PRU0_GPO6.PRG0_RGMII1_RX= C */ + AM64X_IOPAD(0x018c, PIN_OUTPUT, 2) /* (Y3) PRG0_PRU0_GPO11.PRG0_RGMII1_= TD0 */ + AM64X_IOPAD(0x0190, PIN_OUTPUT, 2) /* (AA3) PRG0_PRU0_GPO12.PRG0_RGMII1= _TD1 */ + AM64X_IOPAD(0x0194, PIN_OUTPUT, 2) /* (R6) PRG0_PRU0_GPO13.PRG0_RGMII1_= TD2 */ + AM64X_IOPAD(0x0198, PIN_OUTPUT, 2) /* (V4) PRG0_PRU0_GPO14.PRG0_RGMII1_= TD3 */ + AM64X_IOPAD(0x019c, PIN_OUTPUT, 2) /* (T5) PRG0_PRU0_GPO15.PRG0_RGMII1_= TX_CTL */ + AM64X_IOPAD(0x01a0, PIN_OUTPUT, 2) /* (U4) PRG0_PRU0_GPO16.PRG0_RGMII1_= TXC */ + >; + }; + + icssg0_rgmii2_pins_default: icssg0-rgmii2-default-pins { + pinctrl-single,pins =3D < + AM64X_IOPAD(0x01b0, PIN_INPUT, 2) /* (Y2) PRG0_PRU1_GPO0.PRG0_RGMII2_RD= 0 */ + AM64X_IOPAD(0x01b4, PIN_INPUT, 2) /* (W2) PRG0_PRU1_GPO1.PRG0_RGMII2_RD= 1 */ + AM64X_IOPAD(0x01b8, PIN_INPUT, 2) /* (V3) PRG0_PRU1_GPO2.PRG0_RGMII2_RD= 2 */ + AM64X_IOPAD(0x01bc, PIN_INPUT, 2) /* (T4) PRG0_PRU1_GPO3.PRG0_RGMII2_RD= 3 */ + AM64X_IOPAD(0x01c0, PIN_INPUT, 2) /* (W3) PRG0_PRU1_GPO4.PRG0_RGMII2_RX= _CTL */ + AM64X_IOPAD(0x01c8, PIN_INPUT, 2) /* (R5) PRG0_PRU1_GPO6.PRG0_RGMII2_RX= C */ + AM64X_IOPAD(0x01dc, PIN_OUTPUT, 2) /* (W4) PRG0_PRU1_GPO11.PRG0_RGMII2_= TD0 */ + AM64X_IOPAD(0x01e0, PIN_OUTPUT, 2) /* (Y4) PRG0_PRU1_GPO12.PRG0_RGMII2_= TD1 */ + AM64X_IOPAD(0x01e4, PIN_OUTPUT, 2) /* (T6) PRG0_PRU1_GPO13.PRG0_RGMII2_= TD2 */ + AM64X_IOPAD(0x01e8, PIN_OUTPUT, 2) /* (U6) PRG0_PRU1_GPO14.PRG0_RGMII2_= TD3 */ + AM64X_IOPAD(0x01ec, PIN_OUTPUT, 2) /* (U5) PRG0_PRU1_GPO15.PRG0_RGMII2_= TX_CTL */ + AM64X_IOPAD(0x01f0, PIN_OUTPUT, 2) /* (AA4) PRG0_PRU1_GPO16.PRG0_RGMII2= _TXC */ + >; + }; + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins =3D < AM64X_IOPAD(0x0268, PIN_INPUT, 0) /* (C18) I2C1_SCL */ @@ -198,6 +316,34 @@ AM64X_IOPAD(0x0040, PIN_OUTPUT, 7) /* (U21) GPMC0_AD1.= GPIO0_16 */ }; }; =20 +&icssg0_mdio { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&icssg0_mdio_pins_default &clkout0_pins_default>; + status =3D "okay"; + + icssg0_phy1: ethernet-phy@1 { + compatible =3D "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; + reg =3D <0x1>; + tx-fifo-depth =3D ; + rx-fifo-depth =3D ; + reset-gpios =3D <&main_gpio1 18 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <1000>; + reset-deassert-us =3D <1000>; + ti,rx-internal-delay =3D ; + }; + + icssg0_phy2: ethernet-phy@2 { + compatible =3D "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; + reg =3D <0x2>; + tx-fifo-depth =3D ; + rx-fifo-depth =3D ; + reset-gpios =3D <&main_gpio1 19 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <1000>; + reset-deassert-us =3D <1000>; + ti,rx-internal-delay =3D ; + }; +}; + &main_i2c1 { status =3D "okay"; pinctrl-names =3D "default"; --=20 2.34.1