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(unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTPA id B983A7E04A3; Thu, 15 Aug 2024 15:17:24 +0800 (CST) From: Ye Zhang To: linus.walleij@linaro.org, brgl@bgdev.pl, heiko@sntech.de, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, tao.huang@rock-chips.com, finley.xiao@rock-chips.com, tim.chen@rock-chips.com, elaine.zhang@rock-chips.com, Ye Zhang Subject: [PATCH v1 5/5] rockchip: gpio: fix debounce config error Date: Thu, 15 Aug 2024 15:16:51 +0800 Message-Id: <20240815071651.3645949-6-ye.zhang@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240815071651.3645949-1-ye.zhang@rock-chips.com> References: <20240815071651.3645949-1-ye.zhang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGkhNGFZOTR5PQ04eSB1NThlWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCSE NVSktLVUpCS0tZBg++ X-HM-Tid: 0a9154e600ff09cfkunmb983a7e04a3 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6N1E6ESo*HjI2SEMrDigaKFYO KU8wCjpVSlVKTElITEtNSU9OQ09DVTMWGhIXVQIeVQETGhUcOwkUGBBWGBMSCwhVGBQWRVlXWRIL WUFZTkNVSUlVTFVKSk9ZV1kIAVlBTUhMTzcG Content-Type: text/plain; charset="utf-8" 1. Prevent data from crossing boundaries 2. Support GPIO_TYPE_V2_2 debounce config 3. fix rockchip_gpio_set_config Signed-off-by: Ye Zhang --- drivers/gpio/gpio-rockchip.c | 42 ++++++++++++++++++++++-------------- 1 file changed, 26 insertions(+), 16 deletions(-) diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c index 03e949b0a344..186d8c750fce 100644 --- a/drivers/gpio/gpio-rockchip.c +++ b/drivers/gpio/gpio-rockchip.c @@ -84,7 +84,7 @@ static inline void rockchip_gpio_writel(struct rockchip_p= in_bank *bank, { void __iomem *reg =3D bank->reg_base + offset; =20 - if (bank->gpio_type =3D=3D GPIO_TYPE_V2) + if (bank->gpio_type >=3D GPIO_TYPE_V2) gpio_writel_v2(value, reg); else writel(value, reg); @@ -96,7 +96,7 @@ static inline u32 rockchip_gpio_readl(struct rockchip_pin= _bank *bank, void __iomem *reg =3D bank->reg_base + offset; u32 value; =20 - if (bank->gpio_type =3D=3D GPIO_TYPE_V2) + if (bank->gpio_type >=3D GPIO_TYPE_V2) value =3D gpio_readl_v2(reg); else value =3D readl(reg); @@ -111,7 +111,7 @@ static inline void rockchip_gpio_writel_bit(struct rock= chip_pin_bank *bank, void __iomem *reg =3D bank->reg_base + offset; u32 data; =20 - if (bank->gpio_type =3D=3D GPIO_TYPE_V2) { + if (bank->gpio_type >=3D GPIO_TYPE_V2) { if (value) data =3D BIT(bit % 16) | BIT(bit % 16 + 16); else @@ -132,7 +132,7 @@ static inline u32 rockchip_gpio_readl_bit(struct rockch= ip_pin_bank *bank, void __iomem *reg =3D bank->reg_base + offset; u32 data; =20 - if (bank->gpio_type =3D=3D GPIO_TYPE_V2) { + if (bank->gpio_type >=3D GPIO_TYPE_V2) { data =3D readl(bit >=3D 16 ? reg + 0x4 : reg); data >>=3D bit % 16; } else { @@ -209,19 +209,25 @@ static int rockchip_gpio_set_debounce(struct gpio_chi= p *gc, unsigned int cur_div_reg; u64 div; =20 - if (bank->gpio_type =3D=3D GPIO_TYPE_V2 && !IS_ERR(bank->db_clk)) { - div_debounce_support =3D true; + div_debounce_support =3D (bank->gpio_type >=3D GPIO_TYPE_V2) && !IS_ERR(b= ank->db_clk); + if (debounce && div_debounce_support) { freq =3D clk_get_rate(bank->db_clk); if (!freq) return -EINVAL; - max_debounce =3D (GENMASK(23, 0) + 1) * 2 * 1000000 / freq; + + div =3D (u64)(GENMASK(23, 0) + 1) * 1000000; + if (bank->gpio_type =3D=3D GPIO_TYPE_V2) + max_debounce =3D DIV_ROUND_CLOSEST_ULL(div, freq); + else + max_debounce =3D DIV_ROUND_CLOSEST_ULL(div, 2 * freq); if ((unsigned long)debounce > max_debounce) return -EINVAL; =20 - div =3D debounce * freq; - div_reg =3D DIV_ROUND_CLOSEST_ULL(div, 2 * USEC_PER_SEC) - 1; - } else { - div_debounce_support =3D false; + div =3D (u64)debounce * freq; + if (bank->gpio_type =3D=3D GPIO_TYPE_V2) + div_reg =3D DIV_ROUND_CLOSEST_ULL(div, USEC_PER_SEC) - 1; + else + div_reg =3D DIV_ROUND_CLOSEST_ULL(div, USEC_PER_SEC / 2) - 1; } =20 raw_spin_lock_irqsave(&bank->slock, flags); @@ -284,10 +290,11 @@ static int rockchip_gpio_set_config(struct gpio_chip = *gc, unsigned int offset, unsigned long config) { enum pin_config_param param =3D pinconf_to_config_param(config); + unsigned int debounce =3D pinconf_to_config_argument(config); =20 switch (param) { case PIN_CONFIG_INPUT_DEBOUNCE: - rockchip_gpio_set_debounce(gc, offset, true); + rockchip_gpio_set_debounce(gc, offset, debounce); /* * Rockchip's gpio could only support up to one period * of the debounce clock(pclk), which is far away from @@ -416,7 +423,7 @@ static int rockchip_irq_set_type(struct irq_data *d, un= signed int type) polarity =3D rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity); =20 if (type =3D=3D IRQ_TYPE_EDGE_BOTH) { - if (bank->gpio_type =3D=3D GPIO_TYPE_V2) { + if (bank->gpio_type >=3D GPIO_TYPE_V2) { rockchip_gpio_writel_bit(bank, d->hwirq, 1, bank->gpio_regs->int_bothedge); goto out; @@ -435,7 +442,7 @@ static int rockchip_irq_set_type(struct irq_data *d, un= signed int type) polarity |=3D mask; } } else { - if (bank->gpio_type =3D=3D GPIO_TYPE_V2) { + if (bank->gpio_type >=3D GPIO_TYPE_V2) { rockchip_gpio_writel_bit(bank, d->hwirq, 0, bank->gpio_regs->int_bothedge); } else { @@ -543,7 +550,7 @@ static int rockchip_interrupts_register(struct rockchip= _pin_bank *bank) } =20 gc =3D irq_get_domain_generic_chip(bank->domain, 0); - if (bank->gpio_type =3D=3D GPIO_TYPE_V2) { + if (bank->gpio_type >=3D GPIO_TYPE_V2) { gc->reg_writel =3D gpio_writel_v2; gc->reg_readl =3D gpio_readl_v2; } @@ -632,10 +639,13 @@ static void rockchip_gpio_get_ver(struct rockchip_pin= _bank *bank) switch (id) { case GPIO_TYPE_V2: case GPIO_TYPE_V2_1: - case GPIO_TYPE_V2_2: bank->gpio_regs =3D &gpio_regs_v2; bank->gpio_type =3D GPIO_TYPE_V2; break; + case GPIO_TYPE_V2_2: + bank->gpio_regs =3D &gpio_regs_v2; + bank->gpio_type =3D GPIO_TYPE_V2_2; + break; default: bank->gpio_regs =3D &gpio_regs_v1; bank->gpio_type =3D GPIO_TYPE_V1; --=20 2.34.1