From nobody Sun Feb 8 19:59:36 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD9E81A4F1C; Thu, 15 Aug 2024 14:01:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723730492; cv=none; b=AESIYeAKxqsr4db9RYIh6y0zkxTq3bDJttq4zSXwy3pXwDyhFZI3L0dbn+8dABAv9KR9Ksv7rpFSfDg984u0jv8Kexba+0l7kWKAnPLu7HcO0VEU3Uv1gzfQd/av6pnJRE7XSUV60caULwtRz4+5zapTqsi+81dB/haEG3uxLos= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723730492; c=relaxed/simple; bh=R98AF+O5bdBgSMjboAKPR/52YCoaa6Qj8a/0Ad8DcEU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SPzz6TDxaCNyi7D+T1m4exmAl/CAvUs674fER5ksbyVBRl50nUO0zEisFWy4PliY/L46rdgkeCDhLdu/ErkoS7tXbeQ8/Ji/OFXil+jkGG+MyAQctEpdEhV9J30/W+rJB5skE62QZ9sppUREWRCbrixhGOYMeEGi6DHIBAEYzGY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hXN5gDEv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hXN5gDEv" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CD57BC4AF0A; Thu, 15 Aug 2024 14:01:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723730492; bh=R98AF+O5bdBgSMjboAKPR/52YCoaa6Qj8a/0Ad8DcEU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hXN5gDEvHt36mHKhS605FWzDh1m2kJqZMfr9sWkWT5Vd8HM1PWKOcBVBa6rtUJNQc MN8pNtngGErguro7AoZTRvJAHuz8Mcgizs9NLUtZccRrgdLhxRRru1B8TTjFmz/H62 neMQUbLYAZOBH4vHdJE7EWEgH/pdXJt1XN5ZF9Bx8RZqPeBHqCJhakl9Ry93zNdYTp GZ7FaT10nPWHFAIjRwh7LBoJ5NW+816HWhVyI4qz1Hz6YOPYI2mlxpJRog+US0VHbz uWzlTs0A1/O3TRqBWCnanmhIbn3mtXtQWcr1nEoZn+/RYMB+UIZIRq9iKeHfyWqOOs +iT+qujgmLFHw== From: Conor Dooley To: devicetree@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-kernel@vger.kernel.org Subject: [RFC PATCH 01/11] dt-bindings: mailbox: mpfs: fix reg properties Date: Thu, 15 Aug 2024 15:01:03 +0100 Message-ID: <20240815-premiere-given-1dab82e67eba@spud> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240815-shindig-bunny-fd42792d638a@spud> References: <20240815-shindig-bunny-fd42792d638a@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2460; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=XNHaAfGhWICPeOWwwDbdps/abFlbrTVfGKjKGH4+NlY=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGn7uLQbko7+usq5dNfyvrg7fMlO2zhmbSpwlrmwXTfQe cqtRQ5PO0pYGMQ4GGTFFFkSb/e1SK3/47LDuectzBxWJpAhDFycAjCRphiGn4zvHZ6fnCLHesgg foJDU9dOo8PGjdfvr6lZ/jPEpdZl+gSGH19vvD3x4FfEJv3tVUsCMlr9qhbrzfUI+Gye+2+5Yv8 RFgA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley When the binding for this was originally written, and later modified, mistakes were made - and the precise nature of the later modification should have been a giveaway, but alas I was naive at the time. A more correct modelling of the hardware is to use two syscons and have a single reg entry for the mailbox, containing the mailbox region. The two syscons contain the general control/status registers for the mailbox and the interrupt related registers respectively. The reason for two syscons is that the same mailbox is present on the non-SoC version of the FPGA, which has no interrupt controller, and the shared part of the rtl was unchanged between devices. This is now coming to a head, because the control/status registers share a register region with the "tvs" (temperature & voltage sensors) registers and, as it turns out, people do want to monitor temperatures and voltages... Signed-off-by: Conor Dooley --- .../bindings/mailbox/microchip,mpfs-mailbox.yaml | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailb= ox.yaml b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.= yaml index 404477910f02..3af599efd359 100644 --- a/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml @@ -15,6 +15,8 @@ properties: =20 reg: oneOf: + - items: + - description: mailbox data registers - items: - description: mailbox control & data registers - description: mailbox interrupt registers @@ -23,6 +25,7 @@ properties: - description: mailbox control registers - description: mailbox interrupt registers - description: mailbox data registers + deprecated: true =20 interrupts: maxItems: 1 @@ -41,12 +44,9 @@ additionalProperties: false examples: - | soc { - #address-cells =3D <2>; - #size-cells =3D <2>; - mbox: mailbox@37020000 { + mailbox@37020800 { compatible =3D "microchip,mpfs-mailbox"; - reg =3D <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>, - <0x0 0x37020800 0x0 0x100>; + reg =3D <0x37020800 0x100>; interrupt-parent =3D <&L1>; interrupts =3D <96>; #mbox-cells =3D <1>; --=20 2.43.0 From nobody Sun Feb 8 19:59:36 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16A7B1AC8BB; Thu, 15 Aug 2024 14:01:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723730510; cv=none; b=mX7TzrH6Zozu8YEvZqOBaM0UUkzvNNAze03XeVfiz35rIDVM61c6R5uH7aT7YmlPqdIyMlttF5NBToRl8K5gGsOxW8aIW+Gwh6Jzj7cfWOXgysLxdiXpbrbMtCeQmVRY6w/x8nzDhWyybxAeDCZKbVZX+89sqNKDQgyBNlKRKRI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723730510; c=relaxed/simple; bh=jEMtHxNfXR0nXSRDo6ecNWjuNaFwaoL99JGk8ZNp/Qg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bqZO8u8DFjSzguQkpFyeIhYvEOdOgjyuiarY/T+zbopDRACfjog6mfABu6I9kPDgBvqSQ7zqXiy9JS4dgTB4GLIomGHAOmO3Ksp/L5Bw6+W7SrpgCGt4InklshioPnu8E+xCEysZvPMWKOkP4As8bc7NmSeChvqPte5+SpxVEg0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZgsEmYFF; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZgsEmYFF" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0097CC32786; Thu, 15 Aug 2024 14:01:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723730509; bh=jEMtHxNfXR0nXSRDo6ecNWjuNaFwaoL99JGk8ZNp/Qg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZgsEmYFFulP8x/t9dLYlSykTfiVJ5Jn1hZ7B8xgYxb4c1pbQ8gEY54ge3G80EuUBl Vlr/cwn40zJ/l7ZOQonKRCWvftY5qn3M0bLPx76Ea4CoitZr0/9H0FIUe/bBMNdC8P 2DM+3qL1lfDTFBYbAR3g4pjaZ9F9vh92vKT9hc+DAIkUqEMN91ufpS+HCg6MA2B+Zm nXy3XX/YT9WFYemBG51qozSVHQQ36abWMBYEAATVG30HuLtLwTZPJzjPuEgIp5BZzq AqPO7/yN8Ep6s7YtRtIpNwwoKDCbAC3bE7V3dOBhwMnFwyFd0+p/F3X5ma7DNTaV4C xATztTk36O5jA== From: Conor Dooley To: devicetree@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-kernel@vger.kernel.org, Lars Randers Subject: [RFC PATCH 02/11] hwmon: add a driver for the temp/voltage sensor on PolarFire SoC Date: Thu, 15 Aug 2024 15:01:05 +0100 Message-ID: <20240815-rebuilt-snowstorm-04bfdaa24a1f@spud> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240815-shindig-bunny-fd42792d638a@spud> References: <20240815-shindig-bunny-fd42792d638a@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=12022; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=8oatO5wTt5vz/iuFpGgGCMDMPpmbnqz7B3dspxsyhwE=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGn7uHS6K7vl1f+5FXm9W3ta8JhP+OUZB5veBe/3cJ87O 7CvYG1VRykLgxgHg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACYisIORYc89O+/VF++em+fd aCZ3PjaDIX5SZI2ZX8D/o6FTzkTf6WdkaD+zKfAf835mtTAV/ykPZqn/Wfdx8pQb5m9Nlpnwioc IMAAA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lars Randers Signed-off-by: Lars Randers Signed-off-by: Conor Dooley --- drivers/hwmon/Kconfig | 12 ++ drivers/hwmon/Makefile | 1 + drivers/hwmon/tvs-mpfs.c | 379 +++++++++++++++++++++++++++++++++ drivers/mailbox/mailbox-mpfs.c | 1 + 4 files changed, 393 insertions(+) create mode 100644 drivers/hwmon/tvs-mpfs.c diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index b60fe2e58ad6..2d2bed68dcad 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -2295,6 +2295,18 @@ config SENSORS_TMP513 This driver can also be built as a module. If so, the module will be called tmp513. =20 +config SENSORS_TVS_MPFS + tristate "PolarFire SoC (MPFS) temperature and voltage sensor" + depends on POLARFIRE_SOC_MAILBOX + help + This driver adds support for the PolarFire SoC (MPFS) Temperature and + Voltage Sensor. + + To compile this driver as a module, choose M here. the + module will be called tvs-mpfs. + + If unsure, say N. + config SENSORS_VEXPRESS tristate "Versatile Express" depends on VEXPRESS_CONFIG diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index b1c7056c37db..7f44c2567008 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -220,6 +220,7 @@ obj-$(CONFIG_SENSORS_TMP401) +=3D tmp401.o obj-$(CONFIG_SENSORS_TMP421) +=3D tmp421.o obj-$(CONFIG_SENSORS_TMP464) +=3D tmp464.o obj-$(CONFIG_SENSORS_TMP513) +=3D tmp513.o +obj-$(CONFIG_SENSORS_TVS_MPFS) +=3D tvs-mpfs.o obj-$(CONFIG_SENSORS_VEXPRESS) +=3D vexpress-hwmon.o obj-$(CONFIG_SENSORS_VIA_CPUTEMP)+=3D via-cputemp.o obj-$(CONFIG_SENSORS_VIA686A) +=3D via686a.o diff --git a/drivers/hwmon/tvs-mpfs.c b/drivers/hwmon/tvs-mpfs.c new file mode 100644 index 000000000000..6f117d0b7db6 --- /dev/null +++ b/drivers/hwmon/tvs-mpfs.c @@ -0,0 +1,379 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * + * Author: Lars Randers + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PFSOC_CONTROL_SCB_TVS_CONTROL 0x08 +#define PFSOC_CONTROL_SCB_TVS_OUTPUT0 0x24 +#define PFSOC_CONTROL_SCB_TVS_OUTPUT1 0x28 + +#define CTRL_POWEROFF BIT(5) +#define CTRL_ABORT BIT(4) +#define CTRL_TEMP BIT(3) +#define CTRL_2P5 BIT(2) +#define CTRL_1P8 BIT(1) +#define CTRL_1P05 BIT(0) + +#define OUTPUT0_U1P8_MASK GENMASK(30, 16) +#define OUTPUT0_U1P8_OFF 16 +#define OUTPUT0_U1P0_MASK GENMASK(14, 0) +#define OUTPUT0_U1P0_OFF 0 +#define OUTPUT1_TEMP_MASK GENMASK(31, 16) +#define OUTPUT1_TEMP_OFF 16 +#define OUTPUT1_U2P5_MASK GENMASK(14, 0) +#define OUTPUT1_U2P5_OFF 0 + +#define MPFS_TVS_MIN_POLL_INTERVAL_IN_MILLIS 2000 + +/* The following constant is 273.5 in (16.4) fixedpoint notation */ +#define MPFS_TVS_MIN_TEMP_IN_K 0x1112 + +typedef struct { + long min; + long actual; + long max; +} mpfs_tvs_sensor_t; + +typedef enum { + SN_V1P05 =3D 0, + SN_V1P8, + SN_V2P5, + SN_TEMP, + + SN_MAX +} mpfs_tvs_sn_t; + +static const char *mpfs_tvs_voltage_labels[] =3D { "U1P05", "U1P8", "U2P5"= }; + +struct mpfs_tvs { + struct device *dev; + struct device *hwmon_dev; + struct task_struct *poll_task; + struct regmap *regmap; + bool kthread_running; + long update_interval; /* in milli-seconds */ + mpfs_tvs_sensor_t sensors[SN_MAX]; +}; + +static int mpfs_tvs_update_sensors(struct mpfs_tvs *data) { + u32 temp; + u32 work; + int ret; + + ret =3D regmap_read(data->regmap, PFSOC_CONTROL_SCB_TVS_OUTPUT1, &temp); + if (ret) + return ret; + + work =3D temp; + + temp =3D (temp & OUTPUT1_TEMP_MASK) >> OUTPUT1_TEMP_OFF; + temp =3D clamp_val(temp, MPFS_TVS_MIN_TEMP_IN_K, INT_MAX); + temp =3D temp - MPFS_TVS_MIN_TEMP_IN_K; /* Kelvin to Celsius */ + temp =3D (1000 * temp) >> 4; /* fixed point (10.4) to millicentigrade */ + data->sensors[SN_TEMP].actual =3D temp; + data->sensors[SN_TEMP].max =3D + max(data->sensors[SN_TEMP].actual, data->sensors[SN_TEMP].max); + data->sensors[SN_TEMP].min =3D + min(data->sensors[SN_TEMP].min, data->sensors[SN_TEMP].actual); + + work &=3D OUTPUT1_U2P5_MASK; + /* fixed point (11.3) adjust; value is already millivolts */ + work =3D (1 * work) >> 3; + data->sensors[SN_V2P5].actual =3D work; + data->sensors[SN_V2P5].max =3D + max(data->sensors[SN_V2P5].actual, data->sensors[SN_V2P5].max); + data->sensors[SN_V2P5].min =3D + min(data->sensors[SN_V2P5].min, data->sensors[SN_V2P5].actual); + + ret =3D regmap_read(data->regmap, PFSOC_CONTROL_SCB_TVS_OUTPUT0, &temp); + if (ret) + return ret; + + work =3D temp; + temp =3D (OUTPUT0_U1P8_MASK & temp) >> OUTPUT0_U1P8_OFF; + /* fixed point (11.3) adjust; value is already millivolts */ + temp =3D (1 * temp) >> 3; + data->sensors[SN_V1P8].actual =3D temp; + data->sensors[SN_V1P8].max =3D + max(data->sensors[SN_V1P8].actual, data->sensors[SN_V1P8].max); + data->sensors[SN_V2P5].min =3D + min(data->sensors[SN_V1P8].min, data->sensors[SN_V1P8].actual); + + work &=3D OUTPUT0_U1P0_MASK; + /* fixed point (11.3) adjust; value is already millivolts */ + work =3D (1 * work) >> 3; + data->sensors[SN_V1P05].actual =3D work; + data->sensors[SN_V1P05].max =3D + max(data->sensors[SN_V1P05].actual, data->sensors[SN_V1P05].max); + data->sensors[SN_V1P05].min =3D + min(data->sensors[SN_V1P05].min, data->sensors[SN_V1P05].actual); + + return 0; +} + + +static int mpfs_tvs_chip_read(struct mpfs_tvs *data, long *val) +{ + *val =3D data->update_interval; + return 0; +} + +static int mpfs_tvs_temp_read(struct mpfs_tvs *data, u32 attr, + int channel, long *val) +{ + switch(attr) { + case hwmon_temp_input: + *val =3D data->sensors[SN_TEMP].actual; + break; + + case hwmon_temp_max: + *val =3D data->sensors[SN_TEMP].max; + break; + + default: + return -EOPNOTSUPP; + } + return 0; +} + +static int mpfs_tvs_voltage_read(struct mpfs_tvs *data, u32 attr, + int channel, long *val) +{ + dev_dbg(data->dev, "read voltage chan %d\n", channel); + switch(attr) { + case hwmon_in_input: + *val =3D data->sensors[channel].actual; + break; + + case hwmon_in_max: + *val =3D data->sensors[channel].max; + break; + + default: + return -EOPNOTSUPP; + } + return 0; +} + + +static ssize_t mpfs_tvs_interval_write(struct mpfs_tvs *data, long val) +{ + data->update_interval =3D + clamp_val(val, MPFS_TVS_MIN_POLL_INTERVAL_IN_MILLIS, INT_MAX); + return 0; +} + + +static umode_t mpfs_tvs_is_visible(const void *data, + enum hwmon_sensor_types type, + u32 attr, int channel) +{ + if(type =3D=3D hwmon_chip && attr =3D=3D hwmon_chip_update_interval) + return 0644; + + if(type =3D=3D hwmon_temp) { + switch(attr) { + case hwmon_temp_input: + case hwmon_temp_max: + case hwmon_temp_label: + return 0444; + + default: + return 0; + } + } else if(type =3D=3D hwmon_in) { + switch(attr) { + case hwmon_in_input: + case hwmon_in_label: + return 0444; + + default: + return 0; + } + } + return 0; +} + +static int mpfs_tvs_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *val) +{ + struct mpfs_tvs *data =3D dev_get_drvdata(dev); + + switch(type) { + case hwmon_temp: + return mpfs_tvs_temp_read(data, attr, channel, val); + case hwmon_in: + return mpfs_tvs_voltage_read(data, attr, channel, val); + case hwmon_chip: + return mpfs_tvs_chip_read(data, val); + + default: + return -EOPNOTSUPP; + } +} + +static int mpfs_tvs_write(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long val) +{ + struct mpfs_tvs *data =3D dev_get_drvdata(dev); + + switch(type) { + case hwmon_chip: + return mpfs_tvs_interval_write(data, val); + default: + return -EOPNOTSUPP; + } +} + +static int mpfs_tvs_read_labels(struct device *dev, + enum hwmon_sensor_types type, + u32 attr, int channel, + const char **str) +{ + switch(type) { + case hwmon_temp: + *str =3D "CPU Temp"; + return 0; + case hwmon_in: + *str =3D mpfs_tvs_voltage_labels[channel]; + return 0; + default: + return -EOPNOTSUPP; + } +} + + +static const struct hwmon_ops mpfs_tvs_ops =3D { + .is_visible =3D mpfs_tvs_is_visible, + .read_string =3D mpfs_tvs_read_labels, + .read =3D mpfs_tvs_read, + .write =3D mpfs_tvs_write, +}; + +static const struct hwmon_channel_info *mpfs_tvs_info[] =3D { + HWMON_CHANNEL_INFO(chip, + HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL), + HWMON_CHANNEL_INFO(temp, + HWMON_T_INPUT | HWMON_T_MIN | + HWMON_T_MAX | HWMON_T_LABEL), + HWMON_CHANNEL_INFO(in, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL), + NULL +}; + +static const struct hwmon_chip_info mpfs_tvs_chip_info =3D { + .ops =3D &mpfs_tvs_ops, + .info =3D mpfs_tvs_info, +}; + + +static int mpfs_tvs_poll_task(void *ptr) +{ + struct mpfs_tvs *data =3D ptr; + int ret =3D 0; + + data->kthread_running =3D true; + + set_freezable(); + + while(!kthread_should_stop()) { + schedule_timeout_interruptible(data->update_interval); + try_to_freeze(); + ret =3D mpfs_tvs_update_sensors(data); + if(ret) + break; + } + + data->kthread_running =3D false; + return ret; +} + +static int mpfs_tvs_probe(struct platform_device *pdev) +{ + struct device *hwmon_dev; + struct mpfs_tvs *data; + struct task_struct *task; + int err; + + data =3D devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if(!data) + return -ENOMEM; + + data->dev =3D &pdev->dev; + + data->regmap =3D syscon_node_to_regmap(data->dev->of_node->parent); + + data->kthread_running =3D false; + + hwmon_dev =3D devm_hwmon_device_register_with_info(data->dev, "mpfs_tvs", + data, + &mpfs_tvs_chip_info, + NULL); + + if(IS_ERR(hwmon_dev)) { + err =3D PTR_ERR(hwmon_dev); + dev_err(data->dev, "Class registration failed (%d)\n", err); + return err; + } + + /* enable HW sensor */ + err =3D regmap_write(data->regmap, PFSOC_CONTROL_SCB_TVS_CONTROL, + CTRL_1P05 | CTRL_1P8 | CTRL_2P5 | CTRL_TEMP); + + data->hwmon_dev =3D hwmon_dev; + data->sensors[SN_TEMP].max =3D 0; + data->sensors[SN_V1P05].min =3D + data->sensors[SN_V1P8].min =3D + data->sensors[SN_V2P5].min =3D 20000; + data->sensors[SN_V1P05].max =3D + data->sensors[SN_V1P8].max =3D + data->sensors[SN_V2P5].max =3D 0; + data->update_interval =3D MPFS_TVS_MIN_POLL_INTERVAL_IN_MILLIS; + mpfs_tvs_update_sensors(data); + + task =3D kthread_run(mpfs_tvs_poll_task, data, "tvs-mpfs-kthread"); + if (IS_ERR(task)) { + err =3D PTR_ERR(task); + dev_err(data->dev, "Unable to run kthread err %d\n", err); + return err; + } + + data->poll_task =3D task; + + dev_info(data->dev, "Registered MPFS TVS auxiliary driver\n"); + return 0; +} + +static const struct of_device_id mpfs_tvs_of_match[] =3D { + { .compatible =3D "microchip,mpfs-tvs", }, + {}, +}; +MODULE_DEVICE_TABLE(of, mpfs_tvs_of_match); + +static struct platform_driver mpfs_tvs_driver =3D { + .probe =3D mpfs_tvs_probe, + .driver =3D { + .name =3D "mpfs-tvs", + .of_match_table =3D mpfs_tvs_of_match, + }, +}; +module_platform_driver(mpfs_tvs_driver); + +MODULE_AUTHOR("Lars Randers "); +MODULE_DESCRIPTION("PolarFire SoC temperature & voltage sensor driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c index 20ee283a04cc..0fd83bdd4cee 100644 --- a/drivers/mailbox/mailbox-mpfs.c +++ b/drivers/mailbox/mailbox-mpfs.c @@ -262,6 +262,7 @@ static int mpfs_mbox_probe(struct platform_device *pdev) dev_err(&pdev->dev, "Registering MPFS mailbox controller failed\n"); return ret; } + dev_info(&pdev->dev, "Registered MPFS mailbox controller driver\n"); =20 return 0; --=20 2.43.0 From nobody Sun Feb 8 19:59:36 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 317D71A0710; Thu, 15 Aug 2024 14:01:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723730512; cv=none; b=bX1HnEMZQCDZTNwKpsWDJ5Vq/cU1352zRCMWDNrlzYijRacC1zP0k8czFJdY8M2lCioBUZWOV+wrC3iDMkgLbDMxvWLs4cI5Qj5DNA9zKMEjUOzzpYpiq6iBd2Xwe1RQlmd5XT7shwv+VgSfHRteRmmv2R3bvqDZuGTY7pX2Wvo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723730512; c=relaxed/simple; bh=NOz0Uv8wGGzTdwwKAO9HS5pRf+gFIIXkiQP/tdo821A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EvJE5HHmG6SCvzqGwYxzXBQW/N7pjdDZMd3ebCIsPyDEUYICLiwp+aIrVy2uM6Q8rJV/2PeHZXSAwN0SyOAaU0i2ghGzKLDU95ANQxmw+V9uVOSJ7OapfQWEUV7ykB6KYKD0s2KBVHYXAXJs3j5GsOJq3fZp+Rl670AZF4hHBZI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JXzjbCfV; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JXzjbCfV" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4B74EC4AF12; Thu, 15 Aug 2024 14:01:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723730512; bh=NOz0Uv8wGGzTdwwKAO9HS5pRf+gFIIXkiQP/tdo821A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JXzjbCfVMQI43SWYiP1/vltNgziBil/v7r9ulr7An346+FEcO6XuyFl32fkuTafQk i1s62y2vOA06ukgnyd5/03EA2rPqnewVcuQZBUTaUYeLmNkS4NwkuXkz5BzTlzpXPM REf4GMPb3vGse+cXF/6fKQ0yade6+8EKkP3YlXLcdegbU06WV4HsDk6QHTsX1Dsgcw xQPrqckPpGWxCiHOo1Rzy1KB8Tmd/YitkPlMAavOA5MoycvvPUI4cbeo56OZIW3xXX PifnqGz1YGTNWA1ZPN2PIkmB7HSk/MZC9LBdcNpxqyJy9B2L5YmWtNlRWt0DvItCZA KGsqb4TxKBnuQ== From: Conor Dooley To: devicetree@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-kernel@vger.kernel.org Subject: [RFC PATCH 03/11] mailbox: mpfs: support fixed binding (TODO: always use regmap) Date: Thu, 15 Aug 2024 15:01:06 +0100 Message-ID: <20240815-vantage-clambake-5923706562a8@spud> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240815-shindig-bunny-fd42792d638a@spud> References: <20240815-shindig-bunny-fd42792d638a@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4296; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=N2EYlHnPdpSTmBB5yWHl6UOJ2EHCrvSsT03RsLJC+eE=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGn7uHT2fWNPF7vY7XHr2/H4y0dC5l60+T+599btOQZ+/ DMsLkSXdpSyMIhxMMiKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAiyskM/2On9xyXmZjvIV5+ LdjqbuPE59v8XrMF3lh6/IHntt8e2h6MDFtNp3T+1t5w9oYlY+5Htozrl1k37p1+svff3L3zI6r yNbgA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The two previous bindings for this hardware were incorrect, as the control/status and interrupt register regions should have been described as syscons and dealt with via regmap in the driver. Add support for accessing these registers using that method now, so that the hwmon driver can be supported without using auxdev or hacks with io_remap(). Signed-off-by: Conor Dooley --- drivers/mailbox/mailbox-mpfs.c | 45 +++++++++++++++++++++++++++++++--- 1 file changed, 41 insertions(+), 4 deletions(-) diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c index 0fd83bdd4cee..65aa466ffe8b 100644 --- a/drivers/mailbox/mailbox-mpfs.c +++ b/drivers/mailbox/mailbox-mpfs.c @@ -13,12 +13,15 @@ #include #include #include +#include #include +#include #include #include #include #include =20 +#define MESSAGE_INT_OFFSET 0x18cu #define SERVICES_CR_OFFSET 0x50u #define SERVICES_SR_OFFSET 0x54u #define MAILBOX_REG_OFFSET 0x800u @@ -68,6 +71,7 @@ struct mpfs_mbox { void __iomem *int_reg; struct mbox_chan chans[1]; struct mpfs_mss_response *response; + struct regmap *sysreg_scb, *control_scb; u16 resp_offset; }; =20 @@ -75,7 +79,10 @@ static bool mpfs_mbox_busy(struct mpfs_mbox *mbox) { u32 status; =20 - status =3D readl_relaxed(mbox->ctrl_base + SERVICES_SR_OFFSET); + if (mbox->control_scb) + regmap_read(mbox->control_scb, SERVICES_SR_OFFSET, &status); + else + status =3D readl_relaxed(mbox->ctrl_base + SERVICES_SR_OFFSET); =20 return status & SCB_STATUS_BUSY_MASK; } @@ -95,7 +102,11 @@ static bool mpfs_mbox_last_tx_done(struct mbox_chan *ch= an) * Failed services are intended to generated interrupts, but in reality * this does not happen, so the status must be checked here. */ - val =3D readl_relaxed(mbox->ctrl_base + SERVICES_SR_OFFSET); + if (mbox->control_scb) + regmap_read(mbox->control_scb, SERVICES_SR_OFFSET, &val); + else + val =3D readl_relaxed(mbox->ctrl_base + SERVICES_SR_OFFSET); + response->resp_status =3D (val & SCB_STATUS_MASK) >> SCB_STATUS_POS; =20 return true; @@ -143,7 +154,12 @@ static int mpfs_mbox_send_data(struct mbox_chan *chan,= void *data) =20 tx_trigger =3D (opt_sel << SCB_CTRL_POS) & SCB_CTRL_MASK; tx_trigger |=3D SCB_CTRL_REQ_MASK | SCB_STATUS_NOTIFY_MASK; - writel_relaxed(tx_trigger, mbox->ctrl_base + SERVICES_CR_OFFSET); + + if (mbox->control_scb) + regmap_write(mbox->control_scb, SERVICES_CR_OFFSET, tx_trigger); + else + writel_relaxed(tx_trigger, mbox->ctrl_base + SERVICES_CR_OFFSET); + =20 return 0; } @@ -185,7 +201,10 @@ static irqreturn_t mpfs_mbox_inbox_isr(int irq, void *= data) struct mbox_chan *chan =3D data; struct mpfs_mbox *mbox =3D (struct mpfs_mbox *)chan->con_priv; =20 - writel_relaxed(0, mbox->int_reg); + if (mbox->control_scb) + regmap_write(mbox->sysreg_scb, MESSAGE_INT_OFFSET, 0); + else + writel_relaxed(0, mbox->int_reg); =20 mpfs_mbox_rx_data(chan); =20 @@ -231,6 +250,23 @@ static int mpfs_mbox_probe(struct platform_device *pde= v) if (!mbox) return -ENOMEM; =20 + mbox->control_scb =3D syscon_regmap_lookup_by_compatible("microchip,mpfs-= control-scb"); + if (IS_ERR(mbox->control_scb)) { + mbox->control_scb =3D NULL; + goto old_format; + } + + mbox->sysreg_scb =3D syscon_regmap_lookup_by_compatible("microchip,mpfs-s= ysreg-scb"); + if (IS_ERR(mbox->sysreg_scb)) + return -1; + + mbox->mbox_base =3D devm_platform_get_and_ioremap_resource(pdev, 0, ®s= ); + if (IS_ERR(mbox->ctrl_base)) + return PTR_ERR(mbox->mbox_base); + + goto done; + +old_format: mbox->ctrl_base =3D devm_platform_get_and_ioremap_resource(pdev, 0, ®s= ); if (IS_ERR(mbox->ctrl_base)) return PTR_ERR(mbox->ctrl_base); @@ -243,6 +279,7 @@ static int mpfs_mbox_probe(struct platform_device *pdev) if (IS_ERR(mbox->mbox_base)) // account for the old dt-binding w/ 2 regs mbox->mbox_base =3D mbox->ctrl_base + MAILBOX_REG_OFFSET; =20 +done: mbox->irq =3D platform_get_irq(pdev, 0); if (mbox->irq < 0) return mbox->irq; --=20 2.43.0 From nobody Sun Feb 8 19:59:36 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66F3F1A2570; Thu, 15 Aug 2024 14:01:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723730514; cv=none; b=YVdvKVaJeavAVg2kolSDPg52rT3VCaumizbxa81mzvRqDym4YqwG5ct3GDUnUN7nnAn0uBeaUKZ8vpQPtY6D7DbOVBq8mYTbacyw8TOHXszADMLgFfKBF4RyEeLWY2N+bviY0AmqC1BYhmJpt9KKmdwpz1FtYI2PUisTX3u31b0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723730514; c=relaxed/simple; bh=fB0OEDblSTWS+1OrourHNKnerO8x2dGxroXG5xI23Dg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UANg+Ge49t9MRIj5gmfWyeE9OeFogmHQ45gv/awTSo/ceH/Cv1ICxDKS/lf567ySgLsU6te6xceIp1TXoafMMCSunIvW2N6HMEyb3mPstDueZ0Hp+muH2eF7CyLWivW5LUHJzD4v8duXZIzzDu9BVL6aEWYcYi6PoHuibReKwIY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HmLZ0Gty; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HmLZ0Gty" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6CC8CC4AF10; Thu, 15 Aug 2024 14:01:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723730514; bh=fB0OEDblSTWS+1OrourHNKnerO8x2dGxroXG5xI23Dg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HmLZ0GtyIiHLqOxO+mvyT3OvArzfvvHah1TCLxY8BH5Lguv+jt3PuosVz5j61u3mb bgphO5bXoGm8ZhLzcyhXKkH682lQ2Rb0trYFPHnhK07izglKbxvvPrrZvJVgSW97+3 tYOu8xeHQ9NA2Sw977W0GXNvJ4vww19WJdvm/G2rxz9Ix8ikuw12eROXCWPYh9gM6H UN1P0SiMs8IGFUJOzRCKz6dhJRf/N8jkn5+EPLl4pkA0cu3eKGCv1aPSGPGo8qKv+a bxLbfs+OYj5CFyxKoVH2lYhN4X25r1EkKDSNqudv+hxKQmHYPRPY0Sim30LuLgowG2 tGA3tb+v6G55Q== From: Conor Dooley To: devicetree@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-kernel@vger.kernel.org Subject: [RFC PATCH 04/11] riscv: dts: microchip: fix mailbox description (TODO drop 3rd syscon from here) Date: Thu, 15 Aug 2024 15:01:07 +0100 Message-ID: <20240815-skydiver-generous-c1ab980d6300@spud> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240815-shindig-bunny-fd42792d638a@spud> References: <20240815-shindig-bunny-fd42792d638a@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2524; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=aJBHo+ioF9aGJ0SgdGbkuMDmZeNae1T9gy8tsO62fD8=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGn7uHT+cJzoEW3l81sS8mSh+0T/VczfWF9O+Oqy4hzfv 4luwQrmHaUsDGIcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZiI8xqGf4Ymkzfta7seL8Cn WXjzR9JsFy6XZza7az7Eq4Wf7XiyR42R4XhlRVT/l9joVfu65R9ffvJYc8FqrVPu0t0/tu6ayur ZwwEA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley When the binding for the mailbox on PolarFire SoC was originally written, and later modified, mistakes were made - and the precise nature of the later modification should have been a giveaway, but alas I was naive at the time. A more correct modelling of the hardware is to use two syscons and have a single reg entry for the mailbox, containing the mailbox region. The two syscons contain the general control/status registers for the mailbox and the interrupt related registers respectively. The reason for two syscons is that the same mailbox is present on the non-SoC version of the FPGA, which has no interrupt controller, and the shared part of the rtl was unchanged between devices. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/= microchip/mpfs.dtsi index 9883ca3554c5..1d655126b66f 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -251,6 +251,11 @@ pdma: dma-controller@3000000 { #dma-cells =3D <1>; }; =20 + mss_top_scb: syscon@20002000 { + compatible =3D "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd"; + reg =3D <0x0 0x20002000 0x0 0x1000>; + }; + clkcfg: clkcfg@20002000 { compatible =3D "microchip,mpfs-clkcfg"; reg =3D <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; @@ -259,6 +264,11 @@ clkcfg: clkcfg@20002000 { #reset-cells =3D <1>; }; =20 + sysreg_scb: syscon@20003000 { + compatible =3D "microchip,mpfs-sysreg-scb", "syscon"; + reg =3D <0x0 0x20003000 0x0 0x1000>; + }; + ccc_se: clock-controller@38010000 { compatible =3D "microchip,mpfs-ccc"; reg =3D <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>, @@ -521,10 +531,18 @@ usb: usb@20201000 { status =3D "disabled"; }; =20 - mbox: mailbox@37020000 { + control_scb: syscon@37020000 { + compatible =3D "microchip,mpfs-control-scb", "syscon", "simple-mfd"; + reg =3D <0x0 0x37020000 0x0 0x100>; + + sensor { + compatible =3D "microchip,mpfs-tvs"; + }; + }; + + mbox: mailbox@37020800 { compatible =3D "microchip,mpfs-mailbox"; - reg =3D <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>, - <0x0 0x37020800 0x0 0x100>; + reg =3D <0x0 0x37020800 0x0 0x100>; interrupt-parent =3D <&plic>; interrupts =3D <96>; #mbox-cells =3D <1>; --=20 2.43.0 From nobody Sun Feb 8 19:59:36 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7AF571A2C0F; Thu, 15 Aug 2024 14:01:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723730516; cv=none; b=rYKYf4/9LjkJBf1lcwFZEVRTVA5X58C+TZIdQyIcYiXOr1ahHuUlcLW6tKZsWh2eW4vel8++CnOIGCnCByFybZcMvzfV27Gd0qjVkzuVIAro8tsaf0cOaBc35gi8I9LQ5ZoMrW04XzuR/VvDUQYiUeBdenzgND5gWxntfRpXMyg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723730516; c=relaxed/simple; bh=KO+CxFioosPhJuOhJwS2XgoaJigS1Scj6/2TKWpq48I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Y/4h+EvfdQOkfbqxzMta2d8UEHsubs/g7zIckDSAAWSE2OmxiqNaipFxEPKMUIrjGbjQyFaDyWk8oPsvAc0mBIlX9kwegzAoN64QitAX7a2OaSM6n0lVH9I/VVxFaKe/aBDe002W8rq4kMzw78Yd71G0HdSukraGkONHIrv6Mls= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Svv4ptI+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Svv4ptI+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8D6D0C4AF0C; Thu, 15 Aug 2024 14:01:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723730516; bh=KO+CxFioosPhJuOhJwS2XgoaJigS1Scj6/2TKWpq48I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Svv4ptI+SN47Q+ejbZwApr0cv7ZFYRy3RPHiyffYmRomMCfLSvGrOnS+qzj097G9t uOcX2fi2bL0dXTbmEauqb+W0VgLIIs110yaIKomjv4u5I3/hzmcJCJqRSdSRZPKeTQ hBv8Bc1JMsftVBO/qjW+fsi7miOoLoFS5rPmBkqPiBU+2+bkEqc6rwZ7GO6qCFJghM W+bGaY8qbuIakpKBNmJOBP73Rp0j6QUBQLQUCGLgUCJzFBko9zCh/q3BXtZHNmLxjv 4jQtsjEtmURSZP4f/ZuCCFt4mNXvHvXlaQ6DF3T/q7YgwNfPJtTTnqOBeDCBFOAiYu 00CFeaoznldiA== From: Conor Dooley To: devicetree@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-kernel@vger.kernel.org Subject: [RFC PATCH 05/11] dt-bindings: mfd: syscon document the non simple-mfd syscon on PolarFire SoC Date: Thu, 15 Aug 2024 15:01:08 +0100 Message-ID: <20240815-jockstrap-unlovable-fc0a745604dc@spud> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240815-shindig-bunny-fd42792d638a@spud> References: <20240815-shindig-bunny-fd42792d638a@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1356; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=yoxgUiS5KEsrq0Jq9KVYTtTl2t+HJYVgJhtYs6CJM5A=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGn7uHSqzH5xFyUqKpTt4Vr2SDPvRCy39lTFn/w6q4vzP LtsX8p1lLIwiHEwyIopsiTe7muRWv/HZYdzz1uYOaxMIEMYuDgFYCIHuhn+yiz94lN7QPbShFU7 zh+11dP2TAxT/nIlOqDtvmHliZ9MnYwMXXJHE56blde9FXYo2raZ5/Bz1sibt2z7a7xzzvaYzNH gBAA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The "mss_top_scb" register region on PolarFire SoC contains many different functions, including controls for the AXI bus and other things mainly of interest to the bootloader. The interrupt register for the system controller's mailbox is also in here, which is needed by the operating system. Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentat= ion/devicetree/bindings/mfd/syscon.yaml index 9dc594ea3654..6e6eda8afeed 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -88,6 +88,7 @@ select: - mediatek,mt8173-pctl-a-syscfg - mediatek,mt8365-syscfg - microchip,lan966x-cpu-syscon + - microchip,mpfs-sysreg-scb - microchip,sam9x60-sfr - microchip,sama7g5-ddr3phy - mscc,ocelot-cpu-syscon @@ -183,6 +184,7 @@ properties: - mediatek,mt8173-pctl-a-syscfg - mediatek,mt8365-syscfg - microchip,lan966x-cpu-syscon + - microchip,mpfs-sysreg-scb - microchip,sam9x60-sfr - microchip,sama7g5-ddr3phy - mscc,ocelot-cpu-syscon --=20 2.43.0 From nobody Sun Feb 8 19:59:36 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE7881AC454; Thu, 15 Aug 2024 14:01:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723730518; cv=none; b=DCtMtJ84RSRrP+owCnZxa/TdwlL01vkdSvn5+9dcURe4hcmHi57Mr8NYYkWRNNc/uvIyMZDNe1VHOYUVEZla0Q/UNHSzFpY1SOkBFQdiJpPKsT30bHFp6r0BXAVWrY+6/nbBmpzoXMLBLiwnC+UVrZgmYRhpK/Bpj1qFsjuhVDA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723730518; c=relaxed/simple; bh=Ysz7QSlGk1Ks4f+xiFaqlb0KehG2/+7xlwhdMM3/2R0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gnjElQuDGb9XoVpyYyYW7gNZW/mEI6biWoyTZEPIFGMexxRHhuyg4uEb4a+uSM8A0/P5b9yCJPiZpkUHHDlxhxT8L5aifCD1YnOj8O68k7/QBYTLwoI/Yg7KsXJHc6KvXv7DmxQDc2u+pWgIsYBKB4Mfr49FXaF0ihtbLfKh6ac= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=meT1IHQc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="meT1IHQc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B1914C32786; Thu, 15 Aug 2024 14:01:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723730518; bh=Ysz7QSlGk1Ks4f+xiFaqlb0KehG2/+7xlwhdMM3/2R0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=meT1IHQcLknNu64QvU/CzZiCr+xKuzvCOc27jtRwePy7meMOeWV51fUV4D68J1oF8 0BRZkbLrxSKW14G2eShRMs+2y1xtso71QVRrxRvIlJvkQ+OOvwpEE+AtG5YsrCyl/O clCTFeY9wgFoj6QMbZb53Pfjh5eF0zTBLhGA3fZmKbtF53c1HWInkZWi8ga5/XmVhF PuaERH+PgEUnO2zAnsln67T2LvI500NAXAJ7jl+/bjahxskWlxoENeoGmfH7rho/aI ehJs6es8yuYjuBIaK2biqZ1UmC8jlZjwhbmVxahY6v4wX4VF7Oqeg23PGGqCWFL4sE N5duARtrMagzQ== From: Conor Dooley To: devicetree@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-kernel@vger.kernel.org Subject: [RFC PATCH 06/11] dt-bindings: soc: microchip: document the two simple-mfd syscons on PolarFire SoC Date: Thu, 15 Aug 2024 15:01:09 +0100 Message-ID: <20240815-pending-sacrifice-f2569ed756fe@spud> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240815-shindig-bunny-fd42792d638a@spud> References: <20240815-shindig-bunny-fd42792d638a@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5505; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=oXASywIAqOYqfZopaEeUt3A6SVedBQhIyWFoYy/OS28=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGn7uHSzA9at6M28w1gx6WzhHOO58tEytmemW5xa9Vnv0 8JzT9b0dpSyMIhxMMiKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAiG0QY/ud9kjLfoqQmU2a5 7vN2n760C4Uti9ITTv7dJ50wpSny+F6Gf4rm3OcbMyMiJnTH19UteJ73yfpIp/ncKzwnH6t8tN1 wggsA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley There are two syscons on PolarFire SoC that provide various functionality of use to the OS. The first of these is the "control-scb" region, that contains the "tvs" temperature and voltage sensors and the control/status registers for the system controller's mailbox. The mailbox has a dedicated node, so there's no need for a child node describing it, looking the syscon up by compatible is sufficient. The second, "mss-top-sysreg", contains clocks, pinctrl, resets, and interrupt controller and more. For this RFC, only the reset controller child is described as that's all that is described by the existing bindings. The clock controller already has a dedicated node, and will retain it as there are other clock regions, so like the mailbox, a compatible-based lookup of the syscon is sufficient to keep the clock driver working as before so no child is needed. Signed-off-by: Conor Dooley --- (I'll split this in two later, it's just easier when I have the same questions about both...) Are these things entitled to have child nodes for the reset and sensor nodes, or should the properties be in the parent and the OS probe the drivers for the functions? That's something that, despite supposedly being a maintainer, I do not understand the rules (of thumb?) for. Secondly, is it okay to make the "pragmatic" decision to not have a child clock node and keep routing the clocks via the existing & retained clock node (and therefore not update the various clocks nodes in the consumers)? Doing so would require a lot more hocus pocus with the clock driver than this series does, as the same driver would no longer be suitable for the before/after bindings. --- .../microchip/microchip,mpfs-control-scb.yaml | 54 +++++++++++++++++++ .../microchip,mpfs-mss-top-sysreg.yaml | 53 ++++++++++++++++++ 2 files changed, 107 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/microchip/microch= ip,mpfs-control-scb.yaml create mode 100644 Documentation/devicetree/bindings/soc/microchip/microch= ip,mpfs-mss-top-sysreg.yaml diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs= -control-scb.yaml b/Documentation/devicetree/bindings/soc/microchip/microch= ip,mpfs-control-scb.yaml new file mode 100644 index 000000000000..3673bf139ce8 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-contro= l-scb.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-control-sc= b.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire SoC System Controller Bus (SCB) Control Registe= r region + +maintainers: + - Conor Dooley + +description: + An assortment of system controller related registers, including voltage = and + temperature sensors and the status/control registers for the system + controller's mailbox. + +properties: + compatible: + items: + - const: microchip,mpfs-control-scb + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + sensor: + type: object + + properties: + compatible: + const: microchip,mpfs-tvs + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + syscon@37020000 { + compatible =3D "microchip,mpfs-control-scb", "syscon", "simple-mfd= "; + reg =3D <0x37020000 0x100>; + + sensor { + compatible =3D "microchip,mpfs-tvs"; + }; + }; + }; + diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs= -mss-top-sysreg.yaml b/Documentation/devicetree/bindings/soc/microchip/micr= ochip,mpfs-mss-top-sysreg.yaml new file mode 100644 index 000000000000..d70c9c3348ac --- /dev/null +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-to= p-sysreg.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-mss-top-sy= sreg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire SoC Microprocessor Subsystem (MSS) sysreg Regis= ter region + +maintainers: + - Conor Dooley + +description: + An wide assortment of registers that control elements of the MSS on Pola= rFire + SoC, including pinmuxing, resets and clocks among others. + +properties: + compatible: + items: + - const: microchip,mpfs-mss-top-sysreg + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + reset-controller: + type: object + + properties: + compatible: + const: microchip,mpfs-reset + + '#reset-cells': + description: + The AHB/AXI peripherals on the PolarFire SoC have reset support,= so + from CLK_ENVM to CLK_CFM. The reset consumer should specify the + desired peripheral via the clock ID in its "resets" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the ful= l list + of PolarFire clock/reset IDs. + const: 1 + + additionalProperties: false +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + }; + --=20 2.43.0 From nobody Sun Feb 8 19:59:36 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6E24762D2; Thu, 15 Aug 2024 14:02:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723730520; cv=none; b=E+NaMS34CDrlAIob+nhANK5rERf4eeF5OVTnugSBVUaYTsr20keVWud584Zmcf0U+v9e8d7QZYBi4UDNMQqFZC2Dijc65k1b2kSR/aAQv/ve0jjQeC3d+xxo15je1xJkSE77ft62HBhqHKuQbYXwOL6GyA8SO8z2yfkPp6rd2PA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723730520; c=relaxed/simple; bh=6yhvBvaGny+69tZh8nZxve26/b/KbXhb3BRlyWJ7W+w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eSlLo584UWREEktfSY27NDmGGcHr7agI5Yz0fuFyVXPu1f8PVsNhv/pQM4suRsy8n4zmHznip119GnLi6ubLbgAtXo7pIe2tgxbX/8NDP7snCJ6ocXA78F1YWLOJnmdGuFDd8ugmiqN35oTSGfxbJWlxScjNSxvEOJtx/OfbJB0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oOqlzuML; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oOqlzuML" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D2374C4AF0A; Thu, 15 Aug 2024 14:01:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723730520; bh=6yhvBvaGny+69tZh8nZxve26/b/KbXhb3BRlyWJ7W+w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oOqlzuMLSub6ZxlDDOKcQCu5vgxtpICLFbQRzwogjPi2T8/YV4bu/VwqrCv3rPZr4 VHUWFG7YBPO9KGHLWtU/WGL55M3u3xunNoSDzP7vHdTJTA/jFaoPL56Qt2CXepJ8Yt 8DDMXjbu0kNlbw3MzdxZ+jbH/rye7RBJocMGXUTsj4u2ZYY5PVgMNXpwJN5U9FBZuO /oywWnU2mPRbw9g2UtKrkESm/ai7/K4aIkzErfABVKLwZCi47q0HK+iL/e1WQIm0tq YwbufTcrM4sKc8VajiXAc2dTBneMjedl8Ou/R3GyP//DfxZsx//E4vhnLUWcX5GT9L gzNpEtyo6NRMw== From: Conor Dooley To: devicetree@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-kernel@vger.kernel.org Subject: [RFC PATCH 07/11] reset: mpfs: add non-auxiliary bus probing Date: Thu, 15 Aug 2024 15:01:10 +0100 Message-ID: <20240815-applicant-finch-0419dfefb71a@spud> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240815-shindig-bunny-fd42792d638a@spud> References: <20240815-shindig-bunny-fd42792d638a@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5379; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=wWv2IKjZ/+NYYa1Ld7U/AwY7oWpSP4gWZ0iOuf4p1PE=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGn7uHQ7Zl0XN76VLdvEKfxs84YY0Sk95Rn/S5rVxTcqT HMWlH3ZUcrCIMbBICumyJJ4u69Fav0flx3OPW9h5rAygQxh4OIUgIk4hTP8lX1aKb0rkJnpsuoU yVan26WCDTIZkud26KyOOrnywkNPfYafjL33mJPXLGQ/vTk9+d5bts6Uq7Z/D77Qzo5+4JpzSGo uIwA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley While the auxiliary bus was a nice bandaid, and meant that re-writing the representation of the clock regions in devicetree was not required, it has run its course. The "mss_top_sysreg" region that contains the clock and reset regions, also contains pinctrl and an interrupt controller, so the time has come rewrite the devicetree and probe the reset controller from a dedicated devicetree node, rather than implement those drivers using the auxiliary bus. Wanting to avoid propagating this naive/incorrect description of the hardware to the new pic64gx SoC is a major motivating factor here. Signed-off-by: Conor Dooley --- drivers/reset/reset-mpfs.c | 86 +++++++++++++++++++++++++++++++++----- 1 file changed, 75 insertions(+), 11 deletions(-) diff --git a/drivers/reset/reset-mpfs.c b/drivers/reset/reset-mpfs.c index 710f9c1676f9..3b5c1f680e79 100644 --- a/drivers/reset/reset-mpfs.c +++ b/drivers/reset/reset-mpfs.c @@ -9,10 +9,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -27,11 +29,14 @@ #define MPFS_SLEEP_MIN_US 100 #define MPFS_SLEEP_MAX_US 200 =20 +#define REG_SUBBLK_RESET_CR 0x88u + /* block concurrent access to the soft reset register */ static DEFINE_SPINLOCK(mpfs_reset_lock); =20 struct mpfs_reset { void __iomem *base; + struct regmap *regmap; struct reset_controller_dev rcdev; }; =20 @@ -51,9 +56,17 @@ static int mpfs_assert(struct reset_controller_dev *rcde= v, unsigned long id) =20 spin_lock_irqsave(&mpfs_reset_lock, flags); =20 - reg =3D readl(rst->base); + if (rst->regmap) + regmap_read(rst->regmap, REG_SUBBLK_RESET_CR, ®); + else + reg =3D readl(rst->base); + reg |=3D BIT(id); - writel(reg, rst->base); + + if (rst->regmap) + regmap_write(rst->regmap, REG_SUBBLK_RESET_CR, reg); + else + writel(reg, rst->base); =20 spin_unlock_irqrestore(&mpfs_reset_lock, flags); =20 @@ -68,9 +81,17 @@ static int mpfs_deassert(struct reset_controller_dev *rc= dev, unsigned long id) =20 spin_lock_irqsave(&mpfs_reset_lock, flags); =20 - reg =3D readl(rst->base); + if (rst->regmap) + regmap_read(rst->regmap, REG_SUBBLK_RESET_CR, ®); + else + reg =3D readl(rst->base); + reg &=3D ~BIT(id); - writel(reg, rst->base); + + if (rst->regmap) + regmap_write(rst->regmap, REG_SUBBLK_RESET_CR, reg); + else + writel(reg, rst->base); =20 spin_unlock_irqrestore(&mpfs_reset_lock, flags); =20 @@ -130,11 +151,54 @@ static int mpfs_reset_xlate(struct reset_controller_d= ev *rcdev, return index - MPFS_PERIPH_OFFSET; } =20 -static int mpfs_reset_probe(struct auxiliary_device *adev, - const struct auxiliary_device_id *id) +static int mpfs_reset_of_probe(struct platform_device *pdev) { - struct device *dev =3D &adev->dev; struct reset_controller_dev *rcdev; + struct device *dev =3D &pdev->dev; + struct mpfs_reset *rst; + + rst =3D devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL); + if (!rst) + return -ENOMEM; + + rst->regmap =3D syscon_node_to_regmap(dev->of_node->parent); + if (IS_ERR(rst->regmap)) + dev_err_probe(dev, PTR_ERR(rst->regmap), "Failed to find syscon regmap\n= "); + + rcdev =3D &rst->rcdev; + rcdev->dev =3D dev; + rcdev->ops =3D &mpfs_reset_ops; + + rcdev->of_node =3D dev->of_node; + rcdev->of_reset_n_cells =3D 1; + rcdev->of_xlate =3D mpfs_reset_xlate; + rcdev->nr_resets =3D MPFS_NUM_RESETS; + + printk("of probe\n"); + + return devm_reset_controller_register(dev, rcdev); +} + +static const struct of_device_id mpfs_reset_of_match[] =3D { + { .compatible =3D "microchip,mpfs-reset", }, + {}, +}; +MODULE_DEVICE_TABLE(of, mpfs_reset_of_match); + +static struct platform_driver mpfs_reset_of_driver =3D { + .probe =3D mpfs_reset_of_probe, + .driver =3D { + .name =3D "mpfs-reset", + .of_match_table =3D mpfs_reset_of_match, + }, +}; +module_platform_driver(mpfs_reset_of_driver); + +static int mpfs_reset_adev_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct reset_controller_dev *rcdev; + struct device *dev =3D &adev->dev; struct mpfs_reset *rst; =20 rst =3D devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL); @@ -145,8 +209,8 @@ static int mpfs_reset_probe(struct auxiliary_device *ad= ev, =20 rcdev =3D &rst->rcdev; rcdev->dev =3D dev; - rcdev->dev->parent =3D dev->parent; rcdev->ops =3D &mpfs_reset_ops; + rcdev->of_node =3D dev->parent->of_node; rcdev->of_reset_n_cells =3D 1; rcdev->of_xlate =3D mpfs_reset_xlate; @@ -222,12 +286,12 @@ static const struct auxiliary_device_id mpfs_reset_id= s[] =3D { }; MODULE_DEVICE_TABLE(auxiliary, mpfs_reset_ids); =20 -static struct auxiliary_driver mpfs_reset_driver =3D { - .probe =3D mpfs_reset_probe, +static struct auxiliary_driver mpfs_reset_aux_driver =3D { + .probe =3D mpfs_reset_adev_probe, .id_table =3D mpfs_reset_ids, }; =20 -module_auxiliary_driver(mpfs_reset_driver); +module_auxiliary_driver(mpfs_reset_aux_driver); =20 MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver"); MODULE_AUTHOR("Conor Dooley "); --=20 2.43.0 From nobody Sun Feb 8 19:59:36 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D7A911A7056; Thu, 15 Aug 2024 14:02:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723730522; cv=none; b=C+w9djN2Ks2FW9bsNuwvno2aHo/WnDF+0E3zJik4HqE2pE2UxsN+Dmlw7QVxboxJh+1OAUvzfG5T8NIWafdzvKtUi4ueSiRSNhgfuyG19BDZLO1W7l3WhnKfRDuKssFksNrRm0q9r9OyK+Uh3jxBJtNEk4JKgbtXXdzJJp6bPDI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723730522; c=relaxed/simple; bh=pX087AmU1PaUgpUD1h/mJcraFHVX9O0NaJswXItglDY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZEuWo3WLzDWH97A3vBJt47Hw+BN0MqBICuMOCZO84n22EOR1LYiw+sWLRp56i4HHQfIQHryL6DgUgnAGtR64cB8NG3z2278xdOUI66OFShaCTzyAadF0EK0709CjV5WrpzP2eodJaSpVJqbSeJlKIO/dzgfjM011e2cGfYVMFM4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=J8MJAMoB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="J8MJAMoB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id F2ACEC32786; Thu, 15 Aug 2024 14:02:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723730522; bh=pX087AmU1PaUgpUD1h/mJcraFHVX9O0NaJswXItglDY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=J8MJAMoB3RMbrKDcxeIEFBw++2H3qlyRoZHHOgEggMAb6a6Z0dFnUj9IFqjALz2lr EyDo9geBCnDUY0uFjDFEXyRcGH78ET4HmFPCn9Xt88wy3+Zd2uRQOoNmqLeIufyxIS 4MIwFCItiwszWadPVmDoerQsY9xoQJ0g63iDnd88tauiukFdCOI+xwgQVd0f49DQBW CcjkNgOhI4TS+xZW3dtBDpOsfoVvTwMIv6lF3kg5n5gRmy/I4WM0+uXEgjxDvbXj2b o4eWcU4ezx0vwDb7eWEfyOT2sGfak+5AmK/bh+57hobHBhW1Wh6hmqmfNMFCbx6bIT o6/UpiZtRVQ/Q== From: Conor Dooley To: devicetree@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-kernel@vger.kernel.org Subject: [RFC PATCH 08/11] copy meson clk-regmap for now Date: Thu, 15 Aug 2024 15:01:11 +0100 Message-ID: <20240815-skirmish-violator-8ce24c596b9f@spud> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240815-shindig-bunny-fd42792d638a@spud> References: <20240815-shindig-bunny-fd42792d638a@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=10704; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=7foUgvrOx4wJS1971cQwv0FEaKkGIfX/0niGM57yiMo=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGn7uHR95+69zHXwuvi1Lzd/v2ZJt9m4r4yD/5w7R9ikH J3cH9P3dpSyMIhxMMiKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAiC/QZ/qfwLHLZsc3zY9TW jdsM14pF512ZF7mdSe3MQ+2S2oNiP6cw/E+XWsQj8KTfp8HTmdeeL/fxxLZFvmfv/9vS13+3Ltu jnwcA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Signed-off-by: Conor Dooley --- drivers/clk/microchip/Makefile | 1 + drivers/clk/microchip/clk-regmap.c | 186 +++++++++++++++++++++++++++++ drivers/clk/microchip/clk-regmap.h | 137 +++++++++++++++++++++ 3 files changed, 324 insertions(+) create mode 100644 drivers/clk/microchip/clk-regmap.c create mode 100644 drivers/clk/microchip/clk-regmap.h diff --git a/drivers/clk/microchip/Makefile b/drivers/clk/microchip/Makefile index 13250e04e46c..6b463066c64e 100644 --- a/drivers/clk/microchip/Makefile +++ b/drivers/clk/microchip/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_COMMON_CLK_PIC32) +=3D clk-core.o obj-$(CONFIG_PIC32MZDA) +=3D clk-pic32mzda.o obj-$(CONFIG_MCHP_CLK_MPFS) +=3D clk-mpfs.o obj-$(CONFIG_MCHP_CLK_MPFS) +=3D clk-mpfs-ccc.o +obj-y +=3D clk-regmap.o diff --git a/drivers/clk/microchip/clk-regmap.c b/drivers/clk/microchip/clk= -regmap.c new file mode 100644 index 000000000000..ad116d24f700 --- /dev/null +++ b/drivers/clk/microchip/clk-regmap.c @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 BayLibre, SAS. + * Author: Jerome Brunet + */ + +#include +#include "clk-regmap.h" + +static int clk_regmap_gate_endisable(struct clk_hw *hw, int enable) +{ + struct clk_regmap *clk =3D to_clk_regmap(hw); + struct clk_regmap_gate_data *gate =3D clk_get_regmap_gate_data(clk); + int set =3D gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; + + set ^=3D enable; + + return regmap_update_bits(clk->map, gate->offset, BIT(gate->bit_idx), + set ? BIT(gate->bit_idx) : 0); +} + +static int clk_regmap_gate_enable(struct clk_hw *hw) +{ + return clk_regmap_gate_endisable(hw, 1); +} + +static void clk_regmap_gate_disable(struct clk_hw *hw) +{ + clk_regmap_gate_endisable(hw, 0); +} + +static int clk_regmap_gate_is_enabled(struct clk_hw *hw) +{ + struct clk_regmap *clk =3D to_clk_regmap(hw); + struct clk_regmap_gate_data *gate =3D clk_get_regmap_gate_data(clk); + unsigned int val; + + regmap_read(clk->map, gate->offset, &val); + if (gate->flags & CLK_GATE_SET_TO_DISABLE) + val ^=3D BIT(gate->bit_idx); + + val &=3D BIT(gate->bit_idx); + + return val ? 1 : 0; +} + +const struct clk_ops clk_regmap_gate_ops =3D { + .enable =3D clk_regmap_gate_enable, + .disable =3D clk_regmap_gate_disable, + .is_enabled =3D clk_regmap_gate_is_enabled, +}; +EXPORT_SYMBOL_GPL(clk_regmap_gate_ops); + +const struct clk_ops clk_regmap_gate_ro_ops =3D { + .is_enabled =3D clk_regmap_gate_is_enabled, +}; +EXPORT_SYMBOL_GPL(clk_regmap_gate_ro_ops); + +static unsigned long clk_regmap_div_recalc_rate(struct clk_hw *hw, + unsigned long prate) +{ + struct clk_regmap *clk =3D to_clk_regmap(hw); + struct clk_regmap_div_data *div =3D clk_get_regmap_div_data(clk); + unsigned int val; + int ret; + + ret =3D regmap_read(clk->map, div->offset, &val); + if (ret) + /* Gives a hint that something is wrong */ + return 0; + + val >>=3D div->shift; + val &=3D clk_div_mask(div->width); + return divider_recalc_rate(hw, prate, val, div->table, div->flags, + div->width); +} + +static int clk_regmap_div_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_regmap *clk =3D to_clk_regmap(hw); + struct clk_regmap_div_data *div =3D clk_get_regmap_div_data(clk); + unsigned int val; + int ret; + + /* if read only, just return current value */ + if (div->flags & CLK_DIVIDER_READ_ONLY) { + ret =3D regmap_read(clk->map, div->offset, &val); + if (ret) + return ret; + + val >>=3D div->shift; + val &=3D clk_div_mask(div->width); + + return divider_ro_determine_rate(hw, req, div->table, + div->width, div->flags, val); + } + + return divider_determine_rate(hw, req, div->table, div->width, + div->flags); +} + +static int clk_regmap_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_regmap *clk =3D to_clk_regmap(hw); + struct clk_regmap_div_data *div =3D clk_get_regmap_div_data(clk); + unsigned int val; + int ret; + + ret =3D divider_get_val(rate, parent_rate, div->table, div->width, + div->flags); + if (ret < 0) + return ret; + + val =3D (unsigned int)ret << div->shift; + return regmap_update_bits(clk->map, div->offset, + clk_div_mask(div->width) << div->shift, val); +}; + +/* Would prefer clk_regmap_div_ro_ops but clashes with qcom */ + +const struct clk_ops clk_regmap_divider_ops =3D { + .recalc_rate =3D clk_regmap_div_recalc_rate, + .determine_rate =3D clk_regmap_div_determine_rate, + .set_rate =3D clk_regmap_div_set_rate, +}; +EXPORT_SYMBOL_GPL(clk_regmap_divider_ops); + +const struct clk_ops clk_regmap_divider_ro_ops =3D { + .recalc_rate =3D clk_regmap_div_recalc_rate, + .determine_rate =3D clk_regmap_div_determine_rate, +}; +EXPORT_SYMBOL_GPL(clk_regmap_divider_ro_ops); + +static u8 clk_regmap_mux_get_parent(struct clk_hw *hw) +{ + struct clk_regmap *clk =3D to_clk_regmap(hw); + struct clk_regmap_mux_data *mux =3D clk_get_regmap_mux_data(clk); + unsigned int val; + int ret; + + ret =3D regmap_read(clk->map, mux->offset, &val); + if (ret) + return ret; + + val >>=3D mux->shift; + val &=3D mux->mask; + return clk_mux_val_to_index(hw, mux->table, mux->flags, val); +} + +static int clk_regmap_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_regmap *clk =3D to_clk_regmap(hw); + struct clk_regmap_mux_data *mux =3D clk_get_regmap_mux_data(clk); + unsigned int val =3D clk_mux_index_to_val(mux->table, mux->flags, index); + + return regmap_update_bits(clk->map, mux->offset, + mux->mask << mux->shift, + val << mux->shift); +} + +static int clk_regmap_mux_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_regmap *clk =3D to_clk_regmap(hw); + struct clk_regmap_mux_data *mux =3D clk_get_regmap_mux_data(clk); + + return clk_mux_determine_rate_flags(hw, req, mux->flags); +} + +const struct clk_ops clk_regmap_mux_ops =3D { + .get_parent =3D clk_regmap_mux_get_parent, + .set_parent =3D clk_regmap_mux_set_parent, + .determine_rate =3D clk_regmap_mux_determine_rate, +}; +EXPORT_SYMBOL_GPL(clk_regmap_mux_ops); + +const struct clk_ops clk_regmap_mux_ro_ops =3D { + .get_parent =3D clk_regmap_mux_get_parent, +}; +EXPORT_SYMBOL_GPL(clk_regmap_mux_ro_ops); + +MODULE_DESCRIPTION("Amlogic regmap backed clock driver"); +MODULE_AUTHOR("Jerome Brunet "); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/microchip/clk-regmap.h b/drivers/clk/microchip/clk= -regmap.h new file mode 100644 index 000000000000..e365312da54e --- /dev/null +++ b/drivers/clk/microchip/clk-regmap.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018 BayLibre, SAS. + * Author: Jerome Brunet + */ + +#ifndef __CLK_REGMAP_H +#define __CLK_REGMAP_H + +#include +#include + +/** + * struct clk_regmap - regmap backed clock + * + * @hw: handle between common and hardware-specific interfaces + * @map: pointer to the regmap structure controlling the clock + * @data: data specific to the clock type + * + * Clock which is controlled by regmap backed registers. The actual type of + * of the clock is controlled by the clock_ops and data. + */ +struct clk_regmap { + struct clk_hw hw; + struct regmap *map; + void *data; +}; + +static inline struct clk_regmap *to_clk_regmap(struct clk_hw *hw) +{ + return container_of(hw, struct clk_regmap, hw); +} + +/** + * struct clk_regmap_gate_data - regmap backed gate specific data + * + * @offset: offset of the register controlling gate + * @bit_idx: single bit controlling gate + * @flags: hardware-specific flags + * + * Flags: + * Same as clk_gate except CLK_GATE_HIWORD_MASK which is ignored + */ +struct clk_regmap_gate_data { + unsigned int offset; + u8 bit_idx; + u8 flags; +}; + +static inline struct clk_regmap_gate_data * +clk_get_regmap_gate_data(struct clk_regmap *clk) +{ + return (struct clk_regmap_gate_data *)clk->data; +} + +extern const struct clk_ops clk_regmap_gate_ops; +extern const struct clk_ops clk_regmap_gate_ro_ops; + +/** + * struct clk_regmap_div_data - regmap backed adjustable divider specific = data + * + * @offset: offset of the register controlling the divider + * @shift: shift to the divider bit field + * @width: width of the divider bit field + * @table: array of value/divider pairs, last entry should have div =3D 0 + * + * Flags: + * Same as clk_divider except CLK_DIVIDER_HIWORD_MASK which is ignored + */ +struct clk_regmap_div_data { + unsigned int offset; + u8 shift; + u8 width; + u8 flags; + const struct clk_div_table *table; +}; + +static inline struct clk_regmap_div_data * +clk_get_regmap_div_data(struct clk_regmap *clk) +{ + return (struct clk_regmap_div_data *)clk->data; +} + +extern const struct clk_ops clk_regmap_divider_ops; +extern const struct clk_ops clk_regmap_divider_ro_ops; + +/** + * struct clk_regmap_mux_data - regmap backed multiplexer clock specific d= ata + * + * @hw: handle between common and hardware-specific interfaces + * @offset: offset of theregister controlling multiplexer + * @table: array of parent indexed register values + * @shift: shift to multiplexer bit field + * @mask: mask of mutliplexer bit field + * @flags: hardware-specific flags + * + * Flags: + * Same as clk_divider except CLK_MUX_HIWORD_MASK which is ignored + */ +struct clk_regmap_mux_data { + unsigned int offset; + u32 *table; + u32 mask; + u8 shift; + u8 flags; +}; + +static inline struct clk_regmap_mux_data * +clk_get_regmap_mux_data(struct clk_regmap *clk) +{ + return (struct clk_regmap_mux_data *)clk->data; +} + +extern const struct clk_ops clk_regmap_mux_ops; +extern const struct clk_ops clk_regmap_mux_ro_ops; + +#define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \ +struct clk_regmap _name =3D { \ + .data =3D &(struct clk_regmap_gate_data){ \ + .offset =3D (_reg), \ + .bit_idx =3D (_bit), \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D #_name, \ + .ops =3D _ops, \ + .parent_hws =3D (const struct clk_hw *[]) { _pname }, \ + .num_parents =3D 1, \ + .flags =3D (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ + }, \ +} + +#define MESON_PCLK(_name, _reg, _bit, _pname) \ + __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname) + +#define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ + __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname) +#endif /* __CLK_REGMAP_H */ --=20 2.43.0 From nobody Sun Feb 8 19:59:36 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0012B1AC454; Thu, 15 Aug 2024 14:02:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723730525; cv=none; b=gd+IMkK3TJSzZah+WxxNvzAmr4eKIozoM7JYEBnGpLFc6TJTrPx32RkyvCfm80t0Jtg3hbUhbU4Nl12x0oaVi9ldAis8i71WV2tp8YIn6xlsPP5G6VXonAc8NbQ24sYGYz/Kon1IkS9AdyGy4poBSiHwvGuE0rCJ2puEHMOHzBY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723730525; c=relaxed/simple; bh=//J+70MpTR0Du2JzFTYBY8HR3h40SC+x8QIXmtCouSI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=W3QI9fXkaqis8xtot3AD8H3IivXkdkBXYsc3Y6W2g1l2DG1cUbA4mtOokpEi9mV+7a1h1NmVrVU81H9n1/s2DyL285jy89yoYjhoNczPdFLGcEBloLZ+mkn7weIJ/MagRQwXehkbmMf+hIUEORVIAXkYQv9Lx2pZap3mEtj6u6g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=umfABLK6; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="umfABLK6" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1E96EC4AF11; Thu, 15 Aug 2024 14:02:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723730524; bh=//J+70MpTR0Du2JzFTYBY8HR3h40SC+x8QIXmtCouSI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=umfABLK6ha8wtrFzMJkYv26fZ7ihfdbvdfi1HfIUgyq7zUnsqLt7DMfeeO55iUttx 68ws3Nxmkubqv2oh3xcpih/fmDuBrDDMgbChGWLujWKSPD0yCllPw6ZF8XTQnL86uw m7SJsmfCU+e3wxCnNv3qJDd/0A+G51gNSC+vudVELyORenwHQsGB8r+ulQU2ct7fS6 jTOaWzNlJF2YMubLPBv1esb+nxBEBZPxqdOoaxpjgOgKHj2E3lw47OsoB2S8A7riE3 EWv0Zz6JZiRjZkwZOScGUPHKsz54wVFZBdEyfy9kX+3fxBxB/mhgPE5+IgpE7GQ/n6 5XuEeiD0jH6hA== From: Conor Dooley To: devicetree@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-kernel@vger.kernel.org Subject: [RFC PATCH 09/11] clk: microchip: mpfs: use regmap clock types Date: Thu, 15 Aug 2024 15:01:12 +0100 Message-ID: <20240815-aspire-rocket-38a56ce389ae@spud> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240815-shindig-bunny-fd42792d638a@spud> References: <20240815-shindig-bunny-fd42792d638a@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=7027; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=8TEePMgwAHr2dnJymzvS6c7DD2P/83v04LyJwVYBlQ0=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGn7uHRvthd3Pd675k+pF7P6hEuZSmEnXvavem8YMX/Vw TktJt6eHaUsDGIcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZjI1OMM/zR4f5nnJq87/Hqi 8hP19pYXeyfuENHfYRtyTGvtM9PSy2yMDL2yz6/9neES2b5ddJrS7F83mnK/Lv+0XeHIoT5Z/c/ CWYwA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Convert the PolarFire SoC clock driver to use regmap clock types as a preparatory work for supporting the new binding for this device that will only provide the second of the two register regions, and will require the use of syscon regmap to access the "cfg" and "periph" clocks currently supported by the driver. Signed-off-by: Conor Dooley --- drivers/clk/microchip/clk-mpfs.c | 81 ++++++++++++++++++++++---------- 1 file changed, 56 insertions(+), 25 deletions(-) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-m= pfs.c index 28ec0da88cb3..e288c1729a23 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -6,10 +6,13 @@ */ #include #include +#include #include #include +#include #include #include +#include "clk-regmap.h" =20 /* address offset of control registers */ #define REG_MSSPLL_REF_CR 0x08u @@ -30,6 +33,14 @@ #define MSSPLL_POSTDIV_WIDTH 0x07u #define MSSPLL_FIXED_DIV 4u =20 +static const struct regmap_config clk_mpfs_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .val_format_endian =3D REGMAP_ENDIAN_LITTLE, + .max_register =3D REG_SUBBLK_CLOCK_CR, +}; + /* * This clock ID is defined here, rather than the binding headers, as it i= s an * internal clock only, and therefore has no consumers in other peripheral @@ -39,6 +50,7 @@ =20 struct mpfs_clock_data { struct device *dev; + struct regmap *regmap; void __iomem *base; void __iomem *msspll_base; struct clk_hw_onecell_data hw_data; @@ -68,14 +80,14 @@ struct mpfs_msspll_out_hw_clock { #define to_mpfs_msspll_out_clk(_hw) container_of(_hw, struct mpfs_msspll_o= ut_hw_clock, hw) =20 struct mpfs_cfg_hw_clock { - struct clk_divider cfg; - struct clk_init_data init; + struct clk_regmap sigh; + struct clk_regmap_div_data cfg; unsigned int id; - u32 reg_offset; }; =20 struct mpfs_periph_hw_clock { - struct clk_gate periph; + struct clk_regmap sigh; + struct clk_regmap_gate_data periph; unsigned int id; }; =20 @@ -225,10 +237,9 @@ static int mpfs_clk_register_msspll_outs(struct device= *dev, .cfg.shift =3D _shift, \ .cfg.width =3D _width, \ .cfg.table =3D _table, \ - .reg_offset =3D _offset, \ + .cfg.offset =3D _offset, \ .cfg.flags =3D _flags, \ - .cfg.hw.init =3D CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \ - .cfg.lock =3D &mpfs_clk_lock, \ + .sigh.hw.init =3D CLK_HW_INIT(_name, _parent, &clk_regmap_divider_ops, 0)= , \ } =20 #define CLK_CPU_OFFSET 0u @@ -248,10 +259,10 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] =3D { .cfg.shift =3D 0, .cfg.width =3D 12, .cfg.table =3D mpfs_div_rtcref_table, - .reg_offset =3D REG_RTC_CLOCK_CR, + .cfg.offset =3D REG_RTC_CLOCK_CR, .cfg.flags =3D CLK_DIVIDER_ONE_BASED, - .cfg.hw.init =3D - CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_divider_ops, = 0), + .sigh.hw.init =3D + CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_regmap_divide= r_ops, 0), } }; =20 @@ -264,14 +275,16 @@ static int mpfs_clk_register_cfgs(struct device *dev,= struct mpfs_cfg_hw_clock * for (i =3D 0; i < num_clks; i++) { struct mpfs_cfg_hw_clock *cfg_hw =3D &cfg_hws[i]; =20 - cfg_hw->cfg.reg =3D data->base + cfg_hw->reg_offset; - ret =3D devm_clk_hw_register(dev, &cfg_hw->cfg.hw); + cfg_hw->sigh.map =3D data->regmap; + cfg_hw->sigh.data =3D &cfg_hw->cfg; + + ret =3D devm_clk_hw_register(dev, &cfg_hw->sigh.hw); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", cfg_hw->id); =20 id =3D cfg_hw->id; - data->hw_data.hws[id] =3D &cfg_hw->cfg.hw; + data->hw_data.hws[id] =3D &cfg_hw->sigh.hw; } =20 return 0; @@ -283,13 +296,13 @@ static int mpfs_clk_register_cfgs(struct device *dev,= struct mpfs_cfg_hw_clock * =20 #define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ .id =3D _id, \ + .periph.offset =3D REG_SUBBLK_CLOCK_CR, \ .periph.bit_idx =3D _shift, \ - .periph.hw.init =3D CLK_HW_INIT_HW(_name, _parent, &clk_gate_ops, \ - _flags), \ - .periph.lock =3D &mpfs_clk_lock, \ + .sigh.hw.init =3D CLK_HW_INIT_HW(_name, _parent, &clk_regmap_gate_ops, \ + _flags), \ } =20 -#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].cfg.hw) +#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].sigh.hw) =20 /* * Critical clocks: @@ -346,14 +359,15 @@ static int mpfs_clk_register_periphs(struct device *d= ev, struct mpfs_periph_hw_c for (i =3D 0; i < num_clks; i++) { struct mpfs_periph_hw_clock *periph_hw =3D &periph_hws[i]; =20 - periph_hw->periph.reg =3D data->base + REG_SUBBLK_CLOCK_CR; - ret =3D devm_clk_hw_register(dev, &periph_hw->periph.hw); + periph_hw->sigh.map =3D data->regmap; + periph_hw->sigh.data =3D &periph_hw->periph; + ret =3D devm_clk_hw_register(dev, &periph_hw->sigh.hw); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", periph_hw->id); =20 id =3D periph_hws[i].id; - data->hw_data.hws[id] =3D &periph_hw->periph.hw; + data->hw_data.hws[id] =3D &periph_hw->sigh.hw; } =20 return 0; @@ -374,6 +388,19 @@ static int mpfs_clk_probe(struct platform_device *pdev) if (!clk_data) return -ENOMEM; =20 + clk_data->regmap =3D syscon_regmap_lookup_by_compatible("microchip,mpfs-m= ss-top-sysreg"); + if (IS_ERR(clk_data->regmap)) { + clk_data->regmap =3D NULL; + goto old_format; + } + + clk_data->msspll_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(clk_data->msspll_base)) + return PTR_ERR(clk_data->msspll_base); + + goto done; + +old_format: clk_data->base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(clk_data->base)) return PTR_ERR(clk_data->base); @@ -382,6 +409,14 @@ static int mpfs_clk_probe(struct platform_device *pdev) if (IS_ERR(clk_data->msspll_base)) return PTR_ERR(clk_data->msspll_base); =20 + clk_data->regmap =3D devm_regmap_init_mmio(dev, clk_data->base, &clk_mpfs= _regmap_config); + if (IS_ERR(clk_data->regmap)) + return PTR_ERR(clk_data->regmap); + + ret =3D mpfs_reset_controller_register(dev, clk_data->base + REG_SUBBLK_R= ESET_CR); + if (ret) + return ret; +done: clk_data->hw_data.num =3D num_clks; clk_data->dev =3D dev; dev_set_drvdata(dev, clk_data); @@ -406,11 +441,7 @@ static int mpfs_clk_probe(struct platform_device *pdev) if (ret) return ret; =20 - ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data= ->hw_data); - if (ret) - return ret; - - return mpfs_reset_controller_register(dev, clk_data->base + REG_SUBBLK_RE= SET_CR); + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data-= >hw_data); } =20 static const struct of_device_id mpfs_clk_of_match_table[] =3D { --=20 2.43.0 From nobody Sun Feb 8 19:59:36 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1AB301A7065; Thu, 15 Aug 2024 14:02:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723730527; cv=none; b=h8Y2JTWjhe/SYiShdQk5gtn1LhienAQxT8ikHMU+dqiUtZk4vepOOcHxA2TiwZN66i0b0g50Dusy5Y7Q9NSc3zjA+RHfTIDo4mWlGOQyNQ0K0s3tU2drC7PSNepQcXUkvMKeffHC09CAvVhSTILoTWyghyzRz6U6Bzr4DiqBcxg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723730527; c=relaxed/simple; bh=JZMd4+f34uhJRPeHFtVoTqHmc3yDcFsa+kBqeuczd+8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JoTYAxRYCE5D1tZxvXjW6A+/u5zmD/kAyMpgxStaEmnlZ4XRzuyhp1phe1F8KO9w8Y7WRKi8FK/YKxG/48kN1FW/TCPWNgvPYW59zNip5p16Nga2BWJthqIOLgJ0jI8KVqHr6CdQp9IDHjvLqloAGutXJLfcszfSYYjPY7MSQ/A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=O2+x2rFc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="O2+x2rFc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3E84EC4AF0A; Thu, 15 Aug 2024 14:02:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723730526; bh=JZMd4+f34uhJRPeHFtVoTqHmc3yDcFsa+kBqeuczd+8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=O2+x2rFcDFttOTB4PyU0eOZBRvG2nDbfIxSOodEYZH7OsMbfa8C6VA+Be3sdPX1Lv J/n2mS7OxgxvL5+0bE5ziwi6qe4EnofJhR/DMPk7ePRWYBI3ZrC86Nau2q1m7NdVtD pB/wcPd+Nr9voi0a+k7zQaerWWwwaasFnuG+VVjpFziVP6CmL32mWUCXYkVGkpWJaO r65/H7OsMwv6WcbrrNBHrF+8kTn782D84bU3BTcJSVv8oc9djexwE42LuykR6HzLzq 1AQ+rLh6mWSzK5Czau0tBFPzcZQpjvvrxF4EvzxwC3a6DsgG9t00mXCvv+ni5X6Qex uc+2k3XMvEDeA== From: Conor Dooley To: devicetree@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-kernel@vger.kernel.org Subject: [RFC PATCH 10/11] dt-bindings: clk: microchip: mpfs: remove first reg region Date: Thu, 15 Aug 2024 15:01:13 +0100 Message-ID: <20240815-fernlike-levitate-6004f5f46d66@spud> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240815-shindig-bunny-fd42792d638a@spud> References: <20240815-shindig-bunny-fd42792d638a@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3015; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=P+jscb60JU82jJ4ESec10lLvcGcMyUAEOrlQ0J21yqA=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGn7uPTulboK7Lpz54fhTcOvDbOaZrhZnPIr79Vk6b9wa d4+Dr6rHaUsDGIcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZiIjTsjw28//ueVk9atyDsy uVp62qaM0lNuv3cl3ur0yH7uyiq+tZ/hn72DPOvLqq+/dYsfRW73nrb6Ovs7tvCyhImWn55a5wW 3cwIA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The first reg region in this binding is not exclusively for clocks, as evidenced by the dual role of this device as a reset controller at present. The first region is however better described by a simple-mfd syscon, but this would have require a significant re-write of the devicetree for the platform, so the easy way out was chosen when reset support was first introduced. The region doesn't just contain clock and reset registers, it also contains pinctrl and interrupt controller functionality, so drop the region from the clock binding so that it can be described instead by a simple-mfd syscon rather than propagate this incorrect description of the hardware to the new pic64gx SoC. Signed-off-by: Conor Dooley --- .../bindings/clock/microchip,mpfs-clkcfg.yaml | 33 +++++++++++-------- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.= yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml index e4e1c31267d2..df861eb73e86 100644 --- a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml @@ -22,16 +22,23 @@ properties: const: microchip,mpfs-clkcfg =20 reg: - items: - - description: | - clock config registers: - These registers contain enable, reset & divider tables for the, = cpu, - axi, ahb and rtc/mtimer reference clocks as well as enable and r= eset - for the peripheral clocks. - - description: | - mss pll dri registers: - Block of registers responsible for dynamic reconfiguration of th= e mss - pll + oneOf: + - items: + - description: | + clock config registers: + These registers contain enable, reset & divider tables for t= he, cpu, + axi, ahb and rtc/mtimer reference clocks as well as enable a= nd reset + for the peripheral clocks. + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration o= f the mss + pll + - items: + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration o= f the mss + pll + =20 clocks: maxItems: 1 @@ -69,11 +76,9 @@ examples: - | #include soc { - #address-cells =3D <2>; - #size-cells =3D <2>; - clkcfg: clock-controller@20002000 { + clkcfg: clock-controller@3E001000 { compatible =3D "microchip,mpfs-clkcfg"; - reg =3D <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0= x1000>; + reg =3D <0x3E001000 0x1000>; clocks =3D <&ref>; #clock-cells =3D <1>; }; --=20 2.43.0 From nobody Sun Feb 8 19:59:36 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3834A1B3747; Thu, 15 Aug 2024 14:02:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723730529; cv=none; b=o1ecuwfgDSOJ3jCMKdwL4xvBONfIx8PBaObPMW9VgLRjPGW/Q0PF2nHifLCT0f+ESLxD8ZVeQ+N2k8ciRQJKIm1+qdzvST2YTKqEVfVDrGNW8DhW81vI8VMqgqtv4ZRTJGG4RzrONhKbSvWODg5JNMMrNjuynxEDBxgmnGHlELY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723730529; c=relaxed/simple; bh=6/BDDzn6NjgJMHOa8BpYXh/OmIkUNmyDyx/qEELsamA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oAymUYbFWC7cC4G/BUmjTXSXgkWNjNtzJvHyyYxWl+7QKaR9sIdExOPha8I7UAZog2JQE/4o5FsmWbnjBaTGkaClDj7zxwxuZN2dr7E79RzdMhkLhhLGQbluLQpWPF3qAAg70Y51Tsxbl9/+h51JkAKj4EkxdtR6vFiYbOzSsJk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=m6O2ZoQo; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="m6O2ZoQo" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5DE22C4AF0A; Thu, 15 Aug 2024 14:02:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723730529; bh=6/BDDzn6NjgJMHOa8BpYXh/OmIkUNmyDyx/qEELsamA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=m6O2ZoQoc4awh3MvU70X5edxGhKV1a/OmLUXo6vRtJTnxtt6ZJlSz4NJTuhlWVhHW AS4OB8qdbx6emxhdXzMWjQyIRKZab+oY3CVQaq5xhIbY1j9tYxB5Lp+ZgSKlkHFnjJ 1AeGuskC9QOrQ8dWa8UhAo+2GxA7R0m612Srt9cSh6e/OjT5wj+2/W+6kWvsc2pxIe NuP/rs6roXN/WF170qn9ZJVAvyon9D/lwEK4NdLuwzyLkADKn0XbNK2xVTV+K2YUED hR9/7mz3wbGlzE9kPZm2HwfBdZmIdWzib5ydrEaYdVaQ3CSQAwSpU318Bh7OY5O3ku Pc6kwC9wT12AA== From: Conor Dooley To: devicetree@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-kernel@vger.kernel.org Subject: [RFC PATCH 11/11] riscv: dts: microchip: convert clock and reset (TODO: fixup phandle) Date: Thu, 15 Aug 2024 15:01:14 +0100 Message-ID: <20240815-handsaw-estranged-f9f33c533564@spud> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240815-shindig-bunny-fd42792d638a@spud> References: <20240815-shindig-bunny-fd42792d638a@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1874; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=P0nSk7Ep1qroS73NOlAoSWLxzzlqao33UjAL2l5A8Ag=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGn7uPTulz/r+bFwd5e4kENnWZjmdt//y99Vpecky0hMW akr89G0o5SFQYyDQVZMkSXxdl+L1Po/Ljuce97CzGFlAhnCwMUpABPhX8Pwvzxkx335PN5ZYS9z LgfMbM+bu+Ga/9U5M2bOy3m0NLrv1AeGvzJGyv8ibETvKVyccqX9b41Q7/sdF+58qGTe4Lxw09/ DR3kB X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/= microchip/mpfs.dtsi index 1d655126b66f..6c5b6fef313f 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -254,14 +254,11 @@ pdma: dma-controller@3000000 { mss_top_scb: syscon@20002000 { compatible =3D "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd"; reg =3D <0x0 0x20002000 0x0 0x1000>; - }; =20 - clkcfg: clkcfg@20002000 { - compatible =3D "microchip,mpfs-clkcfg"; - reg =3D <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; - clocks =3D <&refclk>; - #clock-cells =3D <1>; - #reset-cells =3D <1>; + rst: reset-controller { + compatible =3D "microchip,mpfs-reset"; + #reset-cells =3D <1>; + }; }; =20 sysreg_scb: syscon@20003000 { @@ -457,7 +454,7 @@ mac0: ethernet@20110000 { local-mac-address =3D [00 00 00 00 00 00]; clocks =3D <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; clock-names =3D "pclk", "hclk"; - resets =3D <&clkcfg CLK_MAC0>; + resets =3D <&rst CLK_MAC0>; status =3D "disabled"; }; =20 @@ -471,7 +468,7 @@ mac1: ethernet@20112000 { local-mac-address =3D [00 00 00 00 00 00]; clocks =3D <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; clock-names =3D "pclk", "hclk"; - resets =3D <&clkcfg CLK_MAC1>; + resets =3D <&rst CLK_MAC1>; status =3D "disabled"; }; =20 @@ -559,5 +556,12 @@ syscontroller_qspi: spi@37020100 { clocks =3D <&scbclk>; status =3D "disabled"; }; + + clkcfg: clkcfg@3e001000 { + compatible =3D "microchip,mpfs-clkcfg"; + reg =3D <0x0 0x3e001000 0x0 0x1000>; + clocks =3D <&refclk>; + #clock-cells =3D <1>; + }; }; }; --=20 2.43.0