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([2a01:4262:1ab:c:bbf4:eba3:898f:7501]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a80f411bdcbsm182316866b.105.2024.08.14.07.56.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Aug 2024 07:56:44 -0700 (PDT) From: Emil Renner Berthing To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Anup Patel Cc: Thomas Gleixner , Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou Subject: [PATCH v1 1/9] Revert "irqchip/sifive-plic: Chain to parent IRQ after handlers are ready" Date: Wed, 14 Aug 2024 16:56:33 +0200 Message-ID: <20240814145642.344485-2-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240814145642.344485-1-emil.renner.berthing@canonical.com> References: <20240814145642.344485-1-emil.renner.berthing@canonical.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This reverts commit e306a894bd511804ba9db7c00ca9cc05b55df1f2. This is a prerequisite to reverting the patch converting the PLIC into a platform driver. Unfortunately this breaks booting the Allwinner D1 SoC. Fixes: 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a platf= orm driver") Signed-off-by: Emil Renner Berthing Acked-by: Palmer Dabbelt Tested-by: Palmer Dabbelt # QEMU --- drivers/irqchip/irq-sifive-plic.c | 34 +++++++++++++++---------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index 9e22f7e378f5..8fb183ced1e7 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -85,7 +85,7 @@ struct plic_handler { struct plic_priv *priv; }; static int plic_parent_irq __ro_after_init; -static bool plic_global_setup_done __ro_after_init; +static bool plic_cpuhp_setup_done __ro_after_init; static DEFINE_PER_CPU(struct plic_handler, plic_handlers); =20 static int plic_irq_set_type(struct irq_data *d, unsigned int type); @@ -487,8 +487,10 @@ static int plic_probe(struct platform_device *pdev) unsigned long plic_quirks =3D 0; struct plic_handler *handler; u32 nr_irqs, parent_hwirq; + struct irq_domain *domain; struct plic_priv *priv; irq_hw_number_t hwirq; + bool cpuhp_setup; =20 if (is_of_node(dev->fwnode)) { const struct of_device_id *id; @@ -547,6 +549,14 @@ static int plic_probe(struct platform_device *pdev) continue; } =20 + /* Find parent domain and register chained handler */ + domain =3D irq_find_matching_fwnode(riscv_get_intc_hwnode(), DOMAIN_BUS_= ANY); + if (!plic_parent_irq && domain) { + plic_parent_irq =3D irq_create_mapping(domain, RV_IRQ_EXT); + if (plic_parent_irq) + irq_set_chained_handler(plic_parent_irq, plic_handle_irq); + } + /* * When running in M-mode we need to ignore the S-mode handler. * Here we assume it always comes later, but that might be a @@ -587,35 +597,25 @@ static int plic_probe(struct platform_device *pdev) goto fail_cleanup_contexts; =20 /* - * We can have multiple PLIC instances so setup global state + * We can have multiple PLIC instances so setup cpuhp state * and register syscore operations only once after context * handlers of all online CPUs are initialized. */ - if (!plic_global_setup_done) { - struct irq_domain *domain; - bool global_setup =3D true; - + if (!plic_cpuhp_setup_done) { + cpuhp_setup =3D true; for_each_online_cpu(cpu) { handler =3D per_cpu_ptr(&plic_handlers, cpu); if (!handler->present) { - global_setup =3D false; + cpuhp_setup =3D false; break; } } - - if (global_setup) { - /* Find parent domain and register chained handler */ - domain =3D irq_find_matching_fwnode(riscv_get_intc_hwnode(), DOMAIN_BUS= _ANY); - if (domain) - plic_parent_irq =3D irq_create_mapping(domain, RV_IRQ_EXT); - if (plic_parent_irq) - irq_set_chained_handler(plic_parent_irq, plic_handle_irq); - + if (cpuhp_setup) { cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, "irqchip/sifive/plic:starting", plic_starting_cpu, plic_dying_cpu); register_syscore_ops(&plic_irq_syscore_ops); - plic_global_setup_done =3D true; + plic_cpuhp_setup_done =3D true; } } =20 --=20 2.43.0 From nobody Sun Feb 8 13:39:40 2026 Received: from smtp-relay-internal-1.canonical.com (smtp-relay-internal-1.canonical.com [185.125.188.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADABA1B4C29 for ; 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([2a01:4262:1ab:c:bbf4:eba3:898f:7501]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a80f411bdcbsm182316866b.105.2024.08.14.07.56.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Aug 2024 07:56:45 -0700 (PDT) From: Emil Renner Berthing To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Anup Patel Cc: Thomas Gleixner , Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou Subject: [PATCH v1 2/9] Revert "irqchip/sifive-plic: Avoid explicit cpumask allocation on stack" Date: Wed, 14 Aug 2024 16:56:34 +0200 Message-ID: <20240814145642.344485-3-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240814145642.344485-1-emil.renner.berthing@canonical.com> References: <20240814145642.344485-1-emil.renner.berthing@canonical.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This reverts commit a7fb69ffd7ce438a259b2f9fbcebc62f5caf2d4f. This is a prerequisite to reverting the patch converting the PLIC into a platform driver. Unfortunately this breaks booting the Allwinner D1 SoC. Fixes: 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a platf= orm driver") Signed-off-by: Emil Renner Berthing Acked-by: Palmer Dabbelt Tested-by: Palmer Dabbelt # QEMU --- drivers/irqchip/irq-sifive-plic.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index 8fb183ced1e7..f3d4cb9e34f7 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -164,12 +164,15 @@ static int plic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, bool force) { unsigned int cpu; + struct cpumask amask; struct plic_priv *priv =3D irq_data_get_irq_chip_data(d); =20 + cpumask_and(&amask, &priv->lmask, mask_val); + if (force) - cpu =3D cpumask_first_and(&priv->lmask, mask_val); + cpu =3D cpumask_first(&amask); else - cpu =3D cpumask_first_and_and(&priv->lmask, mask_val, cpu_online_mask); + cpu =3D cpumask_any_and(&amask, cpu_online_mask); =20 if (cpu >=3D nr_cpu_ids) return -EINVAL; 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([2a01:4262:1ab:c:bbf4:eba3:898f:7501]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a80f411bdcbsm182316866b.105.2024.08.14.07.56.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Aug 2024 07:56:46 -0700 (PDT) From: Emil Renner Berthing To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Anup Patel Cc: Thomas Gleixner , Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou Subject: [PATCH v1 3/9] Revert "irqchip/sifive-plic: Improve locking safety by using irqsave/irqrestore" Date: Wed, 14 Aug 2024 16:56:35 +0200 Message-ID: <20240814145642.344485-4-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240814145642.344485-1-emil.renner.berthing@canonical.com> References: <20240814145642.344485-1-emil.renner.berthing@canonical.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This reverts commit abb7205794900503d6358ef1fb645373753a794d. This is a prerequisite to reverting the patch converting the PLIC into a platform driver. Unfortunately this breaks booting the Allwinner D1 SoC. Fixes: 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a platf= orm driver") Signed-off-by: Emil Renner Berthing Acked-by: Palmer Dabbelt Tested-by: Palmer Dabbelt # QEMU --- drivers/irqchip/irq-sifive-plic.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index f3d4cb9e34f7..cbccd1da3ea1 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -103,11 +103,9 @@ static void __plic_toggle(void __iomem *enable_base, i= nt hwirq, int enable) =20 static void plic_toggle(struct plic_handler *handler, int hwirq, int enabl= e) { - unsigned long flags; - - raw_spin_lock_irqsave(&handler->enable_lock, flags); + raw_spin_lock(&handler->enable_lock); __plic_toggle(handler->enable_base, hwirq, enable); - raw_spin_unlock_irqrestore(&handler->enable_lock, flags); + raw_spin_unlock(&handler->enable_lock); } =20 static inline void plic_irq_toggle(const struct cpumask *mask, @@ -244,7 +242,6 @@ static int plic_irq_set_type(struct irq_data *d, unsign= ed int type) static int plic_irq_suspend(void) { unsigned int i, cpu; - unsigned long flags; u32 __iomem *reg; struct plic_priv *priv; =20 @@ -262,12 +259,12 @@ static int plic_irq_suspend(void) if (!handler->present) continue; =20 - raw_spin_lock_irqsave(&handler->enable_lock, flags); + raw_spin_lock(&handler->enable_lock); for (i =3D 0; i < DIV_ROUND_UP(priv->nr_irqs, 32); i++) { reg =3D handler->enable_base + i * sizeof(u32); handler->enable_save[i] =3D readl(reg); } - raw_spin_unlock_irqrestore(&handler->enable_lock, flags); + raw_spin_unlock(&handler->enable_lock); } =20 return 0; @@ -276,7 +273,6 @@ static int plic_irq_suspend(void) static void plic_irq_resume(void) { unsigned int i, index, cpu; - unsigned long flags; u32 __iomem *reg; struct plic_priv *priv; =20 @@ -294,12 +290,12 @@ static void plic_irq_resume(void) if (!handler->present) continue; =20 - raw_spin_lock_irqsave(&handler->enable_lock, flags); + raw_spin_lock(&handler->enable_lock); for (i =3D 0; i < DIV_ROUND_UP(priv->nr_irqs, 32); i++) { reg =3D handler->enable_base + i * sizeof(u32); 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([2a01:4262:1ab:c:bbf4:eba3:898f:7501]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a80f411bdcbsm182316866b.105.2024.08.14.07.56.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Aug 2024 07:56:47 -0700 (PDT) From: Emil Renner Berthing To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Anup Patel Cc: Thomas Gleixner , Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou Subject: [PATCH v1 4/9] Revert "irqchip/sifive-plic: Parse number of interrupts and contexts early in plic_probe()" Date: Wed, 14 Aug 2024 16:56:36 +0200 Message-ID: <20240814145642.344485-5-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240814145642.344485-1-emil.renner.berthing@canonical.com> References: <20240814145642.344485-1-emil.renner.berthing@canonical.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This reverts commit 95652106478030f54620b1f0d28f78ab110b3212. This is a prerequisite to reverting the patch converting the PLIC into a platform driver. Unfortunately this breaks booting the Allwinner D1 SoC. Fixes: 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a platf= orm driver") Signed-off-by: Emil Renner Berthing Acked-by: Palmer Dabbelt Tested-by: Palmer Dabbelt # QEMU --- drivers/irqchip/irq-sifive-plic.c | 43 +++++++------------------------ 1 file changed, 10 insertions(+), 33 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index cbccd1da3ea1..b4c4050a02fb 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -423,34 +423,6 @@ static const struct of_device_id plic_match[] =3D { {} }; =20 -static int plic_parse_nr_irqs_and_contexts(struct platform_device *pdev, - u32 *nr_irqs, u32 *nr_contexts) -{ - struct device *dev =3D &pdev->dev; - int rc; - - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ - if (!is_of_node(dev->fwnode)) - return -EINVAL; - - rc =3D of_property_read_u32(to_of_node(dev->fwnode), "riscv,ndev", nr_irq= s); - if (rc) { - dev_err(dev, "riscv,ndev property not available\n"); - return rc; - } - - *nr_contexts =3D of_irq_count(to_of_node(dev->fwnode)); - if (WARN_ON(!(*nr_contexts))) { - dev_err(dev, "no PLIC context available\n"); - return -EINVAL; - } - - return 0; -} - static int plic_parse_context_parent(struct platform_device *pdev, u32 con= text, u32 *parent_hwirq, int *parent_cpu) { @@ -499,26 +471,31 @@ static int plic_probe(struct platform_device *pdev) plic_quirks =3D (unsigned long)id->data; } =20 - error =3D plic_parse_nr_irqs_and_contexts(pdev, &nr_irqs, &nr_contexts); - if (error) - return error; - priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; =20 priv->dev =3D dev; priv->plic_quirks =3D plic_quirks; - priv->nr_irqs =3D nr_irqs; =20 priv->regs =3D devm_platform_ioremap_resource(pdev, 0); if (WARN_ON(!priv->regs)) return -EIO; =20 + of_property_read_u32(to_of_node(dev->fwnode), "riscv,ndev", &nr_irqs); + if (WARN_ON(!nr_irqs)) + return -EINVAL; + + priv->nr_irqs =3D nr_irqs; + priv->prio_save =3D devm_bitmap_zalloc(dev, nr_irqs, GFP_KERNEL); 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([2a01:4262:1ab:c:bbf4:eba3:898f:7501]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a80f411bdcbsm182316866b.105.2024.08.14.07.56.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Aug 2024 07:56:47 -0700 (PDT) From: Emil Renner Berthing To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Anup Patel Cc: Thomas Gleixner , Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou Subject: [PATCH v1 5/9] Revert "irqchip/sifive-plic: Cleanup PLIC contexts upon irqdomain creation failure" Date: Wed, 14 Aug 2024 16:56:37 +0200 Message-ID: <20240814145642.344485-6-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240814145642.344485-1-emil.renner.berthing@canonical.com> References: <20240814145642.344485-1-emil.renner.berthing@canonical.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This reverts commit a15587277a246c388c83b1cd9cf7c1a868cd752f. This is a prerequisite to reverting the patch converting the PLIC into a platform driver. Unfortunately this breaks booting the Allwinner D1 SoC. Fixes: 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a platf= orm driver") Signed-off-by: Emil Renner Berthing Acked-by: Palmer Dabbelt Tested-by: Palmer Dabbelt # QEMU --- drivers/irqchip/irq-sifive-plic.c | 73 +++++++++---------------------- 1 file changed, 20 insertions(+), 53 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index b4c4050a02fb..85e94b8f4c06 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -423,45 +423,17 @@ static const struct of_device_id plic_match[] =3D { {} }; =20 -static int plic_parse_context_parent(struct platform_device *pdev, u32 con= text, - u32 *parent_hwirq, int *parent_cpu) -{ - struct device *dev =3D &pdev->dev; - struct of_phandle_args parent; - unsigned long hartid; - int rc; - - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ - if (!is_of_node(dev->fwnode)) - return -EINVAL; - - rc =3D of_irq_parse_one(to_of_node(dev->fwnode), context, &parent); - if (rc) - return rc; - - rc =3D riscv_of_parent_hartid(parent.np, &hartid); - if (rc) - return rc; - - *parent_hwirq =3D parent.args[0]; - *parent_cpu =3D riscv_hartid_to_cpuid(hartid); - return 0; -} - static int plic_probe(struct platform_device *pdev) { - int error =3D 0, nr_contexts, nr_handlers =3D 0, cpu, i; + int error =3D 0, nr_contexts, nr_handlers =3D 0, i; struct device *dev =3D &pdev->dev; unsigned long plic_quirks =3D 0; struct plic_handler *handler; - u32 nr_irqs, parent_hwirq; struct irq_domain *domain; struct plic_priv *priv; - irq_hw_number_t hwirq; bool cpuhp_setup; + unsigned int cpu; + u32 nr_irqs; =20 if (is_of_node(dev->fwnode)) { const struct of_device_id *id; @@ -497,9 +469,13 @@ static int plic_probe(struct platform_device *pdev) return -EINVAL; =20 for (i =3D 0; i < nr_contexts; i++) { - error =3D plic_parse_context_parent(pdev, i, &parent_hwirq, &cpu); - if (error) { - dev_warn(dev, "hwirq for context%d not found\n", i); + struct of_phandle_args parent; + irq_hw_number_t hwirq; + int cpu; + unsigned long hartid; + + if (of_irq_parse_one(to_of_node(dev->fwnode), i, &parent)) { + dev_err(dev, "failed to parse parent for context %d.\n", i); continue; } =20 @@ -507,7 +483,7 @@ static int plic_probe(struct platform_device *pdev) * Skip contexts other than external interrupts for our * privilege level. */ - if (parent_hwirq !=3D RV_IRQ_EXT) { + if (parent.args[0] !=3D RV_IRQ_EXT) { /* Disable S-mode enable bits if running in M-mode. */ if (IS_ENABLED(CONFIG_RISCV_M_MODE)) { void __iomem *enable_base =3D priv->regs + @@ -520,6 +496,13 @@ static int plic_probe(struct platform_device *pdev) continue; } =20 + error =3D riscv_of_parent_hartid(parent.np, &hartid); + if (error < 0) { + dev_warn(dev, "failed to parse hart ID for context %d.\n", i); + continue; + } + + cpu =3D riscv_hartid_to_cpuid(hartid); if (cpu < 0) { dev_warn(dev, "Invalid cpuid for context %d\n", i); continue; @@ -557,7 +540,7 @@ static int plic_probe(struct platform_device *pdev) handler->enable_save =3D devm_kcalloc(dev, DIV_ROUND_UP(nr_irqs, 32), sizeof(*handler->enable_save), GFP_KERNEL); if (!handler->enable_save) - goto fail_cleanup_contexts; + return -ENOMEM; done: for (hwirq =3D 1; hwirq <=3D nr_irqs; hwirq++) { plic_toggle(handler, hwirq, 0); @@ -570,7 +553,7 @@ static int plic_probe(struct platform_device *pdev) priv->irqdomain =3D irq_domain_add_linear(to_of_node(dev->fwnode), nr_irq= s + 1, &plic_irqdomain_ops, priv); if (WARN_ON(!priv->irqdomain)) - goto fail_cleanup_contexts; + return -ENOMEM; =20 /* * We can have multiple PLIC instances so setup cpuhp state @@ -598,22 +581,6 @@ static int plic_probe(struct platform_device *pdev) dev_info(dev, "mapped %d interrupts with %d handlers for %d contexts.\n", nr_irqs, nr_handlers, nr_contexts); return 0; - -fail_cleanup_contexts: - for (i =3D 0; i < nr_contexts; i++) { - if (plic_parse_context_parent(pdev, i, &parent_hwirq, &cpu)) - continue; - if (parent_hwirq !=3D RV_IRQ_EXT || cpu < 0) - continue; - - handler =3D per_cpu_ptr(&plic_handlers, cpu); - handler->present =3D false; - handler->hart_base =3D NULL; - handler->enable_base =3D NULL; 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([2a01:4262:1ab:c:bbf4:eba3:898f:7501]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a80f411bdcbsm182316866b.105.2024.08.14.07.56.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Aug 2024 07:56:48 -0700 (PDT) From: Emil Renner Berthing To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Anup Patel Cc: Thomas Gleixner , Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou Subject: [PATCH v1 6/9] Revert "irqchip/sifive-plic: Use riscv_get_intc_hwnode() to get parent fwnode" Date: Wed, 14 Aug 2024 16:56:38 +0200 Message-ID: <20240814145642.344485-7-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240814145642.344485-1-emil.renner.berthing@canonical.com> References: <20240814145642.344485-1-emil.renner.berthing@canonical.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This reverts commit 6c725f33d67b53f2d302c2c4509deae953fc6ade. This is a prerequisite to reverting the patch converting the PLIC into a platform driver. Unfortunately this breaks booting the Allwinner D1 SoC. Fixes: 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a platf= orm driver") Signed-off-by: Emil Renner Berthing Acked-by: Palmer Dabbelt Tested-by: Palmer Dabbelt # QEMU --- drivers/irqchip/irq-sifive-plic.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index 85e94b8f4c06..7dbc662a229c 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -429,7 +429,6 @@ static int plic_probe(struct platform_device *pdev) struct device *dev =3D &pdev->dev; unsigned long plic_quirks =3D 0; struct plic_handler *handler; - struct irq_domain *domain; struct plic_priv *priv; bool cpuhp_setup; unsigned int cpu; @@ -509,11 +508,11 @@ static int plic_probe(struct platform_device *pdev) } =20 /* Find parent domain and register chained handler */ - domain =3D irq_find_matching_fwnode(riscv_get_intc_hwnode(), DOMAIN_BUS_= ANY); - if (!plic_parent_irq && domain) { - plic_parent_irq =3D irq_create_mapping(domain, RV_IRQ_EXT); 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([2a01:4262:1ab:c:bbf4:eba3:898f:7501]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a80f411bdcbsm182316866b.105.2024.08.14.07.56.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Aug 2024 07:56:49 -0700 (PDT) From: Emil Renner Berthing To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Anup Patel Cc: Thomas Gleixner , Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou Subject: [PATCH v1 7/9] Revert "irqchip/sifive-plic: Use devm_xyz() for managed allocation" Date: Wed, 14 Aug 2024 16:56:39 +0200 Message-ID: <20240814145642.344485-8-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240814145642.344485-1-emil.renner.berthing@canonical.com> References: <20240814145642.344485-1-emil.renner.berthing@canonical.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This reverts commit b68d0ff529a939a118ec52f271be8cad5d99e79a. This is a prerequisite to reverting the patch converting the PLIC into a platform driver. Unfortunately this breaks booting the Allwinner D1 SoC. Fixes: 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a platf= orm driver") Signed-off-by: Emil Renner Berthing Acked-by: Palmer Dabbelt Tested-by: Palmer Dabbelt # QEMU --- drivers/irqchip/irq-sifive-plic.c | 49 +++++++++++++++++++++---------- 1 file changed, 33 insertions(+), 16 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index 7dbc662a229c..7cf06bbb3098 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -442,30 +442,39 @@ static int plic_probe(struct platform_device *pdev) plic_quirks =3D (unsigned long)id->data; } =20 - priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + priv =3D kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; =20 priv->dev =3D dev; priv->plic_quirks =3D plic_quirks; =20 - priv->regs =3D devm_platform_ioremap_resource(pdev, 0); - if (WARN_ON(!priv->regs)) - return -EIO; + priv->regs =3D of_iomap(to_of_node(dev->fwnode), 0); + if (WARN_ON(!priv->regs)) { + error =3D -EIO; + goto out_free_priv; + } =20 + error =3D -EINVAL; of_property_read_u32(to_of_node(dev->fwnode), "riscv,ndev", &nr_irqs); if (WARN_ON(!nr_irqs)) - return -EINVAL; + goto out_iounmap; =20 priv->nr_irqs =3D nr_irqs; =20 - priv->prio_save =3D devm_bitmap_zalloc(dev, nr_irqs, GFP_KERNEL); + priv->prio_save =3D bitmap_alloc(nr_irqs, GFP_KERNEL); if (!priv->prio_save) - return -ENOMEM; + goto out_free_priority_reg; =20 nr_contexts =3D of_irq_count(to_of_node(dev->fwnode)); if (WARN_ON(!nr_contexts)) - return -EINVAL; + goto out_free_priority_reg; + + error =3D -ENOMEM; + priv->irqdomain =3D irq_domain_add_linear(to_of_node(dev->fwnode), nr_irq= s + 1, + &plic_irqdomain_ops, priv); + if (WARN_ON(!priv->irqdomain)) + goto out_free_priority_reg; =20 for (i =3D 0; i < nr_contexts; i++) { struct of_phandle_args parent; @@ -536,10 +545,10 @@ static int plic_probe(struct platform_device *pdev) i * CONTEXT_ENABLE_SIZE; handler->priv =3D priv; =20 - handler->enable_save =3D devm_kcalloc(dev, DIV_ROUND_UP(nr_irqs, 32), - sizeof(*handler->enable_save), GFP_KERNEL); + handler->enable_save =3D kcalloc(DIV_ROUND_UP(nr_irqs, 32), + sizeof(*handler->enable_save), GFP_KERNEL); if (!handler->enable_save) - return -ENOMEM; + goto out_free_enable_reg; done: for (hwirq =3D 1; hwirq <=3D nr_irqs; hwirq++) { plic_toggle(handler, hwirq, 0); @@ -549,11 +558,6 @@ static int plic_probe(struct platform_device *pdev) nr_handlers++; } =20 - priv->irqdomain =3D irq_domain_add_linear(to_of_node(dev->fwnode), nr_irq= s + 1, - &plic_irqdomain_ops, priv); - if (WARN_ON(!priv->irqdomain)) - return -ENOMEM; - /* * We can have multiple PLIC instances so setup cpuhp state * and register syscore operations only once after context @@ -580,6 +584,19 @@ static int plic_probe(struct platform_device *pdev) dev_info(dev, "mapped %d interrupts with %d handlers for %d contexts.\n", nr_irqs, nr_handlers, nr_contexts); return 0; + +out_free_enable_reg: + for_each_cpu(cpu, cpu_present_mask) { + handler =3D per_cpu_ptr(&plic_handlers, cpu); + kfree(handler->enable_save); + } +out_free_priority_reg: + kfree(priv->prio_save); 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([2a01:4262:1ab:c:bbf4:eba3:898f:7501]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a80f411bdcbsm182316866b.105.2024.08.14.07.56.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Aug 2024 07:56:50 -0700 (PDT) From: Emil Renner Berthing To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Anup Patel Cc: Thomas Gleixner , Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou Subject: [PATCH v1 8/9] Revert "irqchip/sifive-plic: Use dev_xyz() in-place of pr_xyz()" Date: Wed, 14 Aug 2024 16:56:40 +0200 Message-ID: <20240814145642.344485-9-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240814145642.344485-1-emil.renner.berthing@canonical.com> References: <20240814145642.344485-1-emil.renner.berthing@canonical.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This reverts commit 25d862e183d4efeb5e8b9843d783c90aaae4b14a. This is a prerequisite to reverting the patch converting the PLIC into a platform driver. Unfortunately this breaks booting the Allwinner D1 SoC. Fixes: 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a platf= orm driver") Signed-off-by: Emil Renner Berthing Acked-by: Palmer Dabbelt Tested-by: Palmer Dabbelt # QEMU --- drivers/irqchip/irq-sifive-plic.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index 7cf06bbb3098..ac274e1166c3 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 SiFive * Copyright (C) 2018 Christoph Hellwig */ +#define pr_fmt(fmt) "plic: " fmt #include #include #include @@ -376,10 +377,9 @@ static void plic_handle_irq(struct irq_desc *desc) while ((hwirq =3D readl(claim))) { int err =3D generic_handle_domain_irq(handler->priv->irqdomain, hwirq); - if (unlikely(err)) { - dev_warn_ratelimited(handler->priv->dev, - "can't find mapping for hwirq %lu\n", hwirq); - } + if (unlikely(err)) + pr_warn_ratelimited("can't find mapping for hwirq %lu\n", + hwirq); } =20 chained_irq_exit(chip, desc); @@ -407,7 +407,7 @@ static int plic_starting_cpu(unsigned int cpu) enable_percpu_irq(plic_parent_irq, irq_get_trigger_type(plic_parent_irq)); else - dev_warn(handler->priv->dev, "cpu%d: parent irq not available\n", cpu); + pr_warn("cpu%d: parent irq not available\n", cpu); plic_set_threshold(handler, PLIC_ENABLE_THRESHOLD); =20 return 0; @@ -483,7 +483,7 @@ static int plic_probe(struct platform_device *pdev) unsigned long hartid; =20 if (of_irq_parse_one(to_of_node(dev->fwnode), i, &parent)) { - dev_err(dev, "failed to parse parent for context %d.\n", i); + pr_err("failed to parse parent for context %d.\n", i); continue; } =20 @@ -506,13 +506,13 @@ static int plic_probe(struct platform_device *pdev) =20 error =3D riscv_of_parent_hartid(parent.np, &hartid); if (error < 0) { - dev_warn(dev, "failed to parse hart ID for context %d.\n", i); + pr_warn("failed to parse hart ID for context %d.\n", i); continue; } =20 cpu =3D riscv_hartid_to_cpuid(hartid); if (cpu < 0) { - dev_warn(dev, "Invalid cpuid for context %d\n", i); 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([2a01:4262:1ab:c:bbf4:eba3:898f:7501]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a80f411bdcbsm182316866b.105.2024.08.14.07.56.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Aug 2024 07:56:51 -0700 (PDT) From: Emil Renner Berthing To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Anup Patel Cc: Thomas Gleixner , Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou Subject: [PATCH v1 9/9] Revert "irqchip/sifive-plic: Convert PLIC driver into a platform driver" Date: Wed, 14 Aug 2024 16:56:41 +0200 Message-ID: <20240814145642.344485-10-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240814145642.344485-1-emil.renner.berthing@canonical.com> References: <20240814145642.344485-1-emil.renner.berthing@canonical.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This reverts commit 8ec99b033147ef3bb8f0a560c24eb1baec3bc0be. This change makes the Allwinner D1 SoC lock up at boot as described in the thread below. Link: https://lore.kernel.org/linux-riscv/CAJM55Z9hGKo4784N3s3DhWw=3DnMRKZK= cmvZ58x7uVBghExhoc9A@mail.gmail.com/ Fixes: 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a platf= orm driver") Signed-off-by: Emil Renner Berthing Acked-by: Palmer Dabbelt Tested-by: Palmer Dabbelt # QEMU --- drivers/irqchip/irq-sifive-plic.c | 103 ++++++++++++------------------ 1 file changed, 41 insertions(+), 62 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index ac274e1166c3..bf0b40b0fad4 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -64,7 +64,6 @@ #define PLIC_QUIRK_EDGE_INTERRUPT 0 =20 struct plic_priv { - struct device *dev; struct cpumask lmask; struct irq_domain *irqdomain; void __iomem *regs; @@ -413,50 +412,30 @@ static int plic_starting_cpu(unsigned int cpu) return 0; } =20 -static const struct of_device_id plic_match[] =3D { - { .compatible =3D "sifive,plic-1.0.0" }, - { .compatible =3D "riscv,plic0" }, - { .compatible =3D "andestech,nceplic100", - .data =3D (const void *)BIT(PLIC_QUIRK_EDGE_INTERRUPT) }, - { .compatible =3D "thead,c900-plic", - .data =3D (const void *)BIT(PLIC_QUIRK_EDGE_INTERRUPT) }, - {} -}; - -static int plic_probe(struct platform_device *pdev) +static int __init __plic_init(struct device_node *node, + struct device_node *parent, + unsigned long plic_quirks) { int error =3D 0, nr_contexts, nr_handlers =3D 0, i; - struct device *dev =3D &pdev->dev; - unsigned long plic_quirks =3D 0; - struct plic_handler *handler; - struct plic_priv *priv; - bool cpuhp_setup; - unsigned int cpu; u32 nr_irqs; - - if (is_of_node(dev->fwnode)) { - const struct of_device_id *id; - - id =3D of_match_node(plic_match, to_of_node(dev->fwnode)); - if (id) - plic_quirks =3D (unsigned long)id->data; - } + struct plic_priv *priv; + struct plic_handler *handler; + unsigned int cpu; =20 priv =3D kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; =20 - priv->dev =3D dev; priv->plic_quirks =3D plic_quirks; =20 - priv->regs =3D of_iomap(to_of_node(dev->fwnode), 0); + priv->regs =3D of_iomap(node, 0); if (WARN_ON(!priv->regs)) { error =3D -EIO; goto out_free_priv; } =20 error =3D -EINVAL; - of_property_read_u32(to_of_node(dev->fwnode), "riscv,ndev", &nr_irqs); + of_property_read_u32(node, "riscv,ndev", &nr_irqs); if (WARN_ON(!nr_irqs)) goto out_iounmap; =20 @@ -466,13 +445,13 @@ static int plic_probe(struct platform_device *pdev) if (!priv->prio_save) goto out_free_priority_reg; =20 - nr_contexts =3D of_irq_count(to_of_node(dev->fwnode)); + nr_contexts =3D of_irq_count(node); if (WARN_ON(!nr_contexts)) goto out_free_priority_reg; =20 error =3D -ENOMEM; - priv->irqdomain =3D irq_domain_add_linear(to_of_node(dev->fwnode), nr_irq= s + 1, - &plic_irqdomain_ops, priv); + priv->irqdomain =3D irq_domain_add_linear(node, nr_irqs + 1, + &plic_irqdomain_ops, priv); if (WARN_ON(!priv->irqdomain)) goto out_free_priority_reg; =20 @@ -482,7 +461,7 @@ static int plic_probe(struct platform_device *pdev) int cpu; unsigned long hartid; =20 - if (of_irq_parse_one(to_of_node(dev->fwnode), i, &parent)) { + if (of_irq_parse_one(node, i, &parent)) { pr_err("failed to parse parent for context %d.\n", i); continue; } @@ -518,7 +497,7 @@ static int plic_probe(struct platform_device *pdev) =20 /* Find parent domain and register chained handler */ if (!plic_parent_irq && irq_find_host(parent.np)) { - plic_parent_irq =3D irq_of_parse_and_map(to_of_node(dev->fwnode), i); + plic_parent_irq =3D irq_of_parse_and_map(node, i); if (plic_parent_irq) irq_set_chained_handler(plic_parent_irq, plic_handle_irq); @@ -560,29 +539,20 @@ static int plic_probe(struct platform_device *pdev) =20 /* * We can have multiple PLIC instances so setup cpuhp state - * and register syscore operations only once after context - * handlers of all online CPUs are initialized. + * and register syscore operations only when context handler + * for current/boot CPU is present. */ - if (!plic_cpuhp_setup_done) { - cpuhp_setup =3D true; - for_each_online_cpu(cpu) { - handler =3D per_cpu_ptr(&plic_handlers, cpu); - if (!handler->present) { - cpuhp_setup =3D false; - break; - } - } - if (cpuhp_setup) { - cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, - "irqchip/sifive/plic:starting", - plic_starting_cpu, plic_dying_cpu); - register_syscore_ops(&plic_irq_syscore_ops); - plic_cpuhp_setup_done =3D true; - } + handler =3D this_cpu_ptr(&plic_handlers); + if (handler->present && !plic_cpuhp_setup_done) { + cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, + "irqchip/sifive/plic:starting", + plic_starting_cpu, plic_dying_cpu); + register_syscore_ops(&plic_irq_syscore_ops); + plic_cpuhp_setup_done =3D true; } =20 - pr_info("%pOFP: mapped %d interrupts with %d handlers for %d contexts.\n", - to_of_node(dev->fwnode), nr_irqs, nr_handlers, nr_contexts); + pr_info("%pOFP: mapped %d interrupts with %d handlers for" + " %d contexts.\n", node, nr_irqs, nr_handlers, nr_contexts); return 0; =20 out_free_enable_reg: @@ -599,11 +569,20 @@ static int plic_probe(struct platform_device *pdev) return error; } =20 -static struct platform_driver plic_driver =3D { - .driver =3D { - .name =3D "riscv-plic", - .of_match_table =3D plic_match, - }, - .probe =3D plic_probe, -}; -builtin_platform_driver(plic_driver); +static int __init plic_init(struct device_node *node, + struct device_node *parent) +{ + return __plic_init(node, parent, 0); +} + +IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init); +IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy syst= ems */ + +static int __init plic_edge_init(struct device_node *node, + struct device_node *parent) +{ + return __plic_init(node, parent, BIT(PLIC_QUIRK_EDGE_INTERRUPT)); +} + +IRQCHIP_DECLARE(andestech_nceplic100, "andestech,nceplic100", plic_edge_in= it); +IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_edge_init); --=20 2.43.0