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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Aug 2024 10:00:40.3753 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e4409ccf-682c-46dd-0789-08dcbc47f425 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000013E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6274 Content-Type: text/plain; charset="utf-8" - AMD provides custom protocol to read Machine Check Architecture(MCA) registers over sideband. The inforamtion is accessed for range of MCA reg= isters by passing register address and thread ID to the protocol. Access is read-only Signed-off-by: Akshay Gupta Reviewed-by: Naveen Krishna Chatradhi --- Changes since v2: - update the MACROS name as per feedback Changes since v1: - bifurcated from previous patch 5 drivers/misc/amd-sbi/rmi-core.c | 90 +++++++++++++++++++++++++++++++++ include/uapi/misc/amd-apml.h | 17 ++++--- 2 files changed, 101 insertions(+), 6 deletions(-) diff --git a/drivers/misc/amd-sbi/rmi-core.c b/drivers/misc/amd-sbi/rmi-cor= e.c index fdac6848ae9a..56fe09e1e54c 100644 --- a/drivers/misc/amd-sbi/rmi-core.c +++ b/drivers/misc/amd-sbi/rmi-core.c @@ -32,10 +32,16 @@ #define CPUID_WR_DATA_LEN 0x8 #define CPUID_RD_REG_LEN 0xa #define CPUID_WR_REG_LEN 0x9 +/* MSR */ +#define MSR_RD_REG_LEN 0xa +#define MSR_WR_REG_LEN 0x8 +#define MSR_RD_DATA_LEN 0x8 +#define MSR_WR_DATA_LEN 0x7 =20 /* CPUID MSR Command Ids */ #define CPUID_MCA_CMD 0x73 #define RD_CPUID_CMD 0x91 +#define RD_MCA_CMD 0x86 =20 /* input for bulk write to CPUID protocol */ struct cpu_msr_indata { @@ -68,6 +74,13 @@ struct cpu_msr_outdata { input.value =3D func, \ input.ext =3D ext_func =20 +#define prepare_mca_msr_input_message(input, thread_id, data_in) \ + input.rd_len =3D MSR_RD_DATA_LEN, \ + input.wr_len =3D MSR_WR_DATA_LEN, \ + input.proto_cmd =3D RD_MCA_CMD, \ + input.thread =3D thread_id << 1, \ + input.value =3D data_in + /* * For Mailbox command software alert status bit is set by firmware * to indicate command completion @@ -191,6 +204,79 @@ static int rmi_cpuid_read(struct sbrmi_data *data, return ret; } =20 +/* MCA MSR protocol */ +static int rmi_mca_msr_read(struct sbrmi_data *data, + struct apml_message *msg) +{ + struct cpu_msr_outdata output =3D {0}; + struct cpu_msr_indata input =3D {0}; + int ret, val =3D 0; + int hw_status; + u16 thread; + + mutex_lock(&data->lock); + /* cache the rev value to identify if protocol is supported or not */ + if (!data->rev) { + ret =3D sbrmi_get_rev(data); + if (ret < 0) + goto exit_unlock; + } + /* MCA MSR protocol for REV 0x10 is not supported*/ + if (data->rev =3D=3D 0x10) { + ret =3D -EOPNOTSUPP; + goto exit_unlock; + } + + thread =3D msg->data_in.reg_in[AMD_SBI_THREAD_LOW_INDEX] | + msg->data_in.reg_in[AMD_SBI_THREAD_HI_INDEX] << 8; + + /* Thread > 127, Thread128 CS register, 1'b1 needs to be set to 1 */ + if (thread > 127) { + thread -=3D 128; + val =3D 1; + } + ret =3D regmap_write(data->regmap, SBRMI_THREAD128CS, val); + if (ret < 0) + goto exit_unlock; + + prepare_mca_msr_input_message(input, thread, + msg->data_in.mb_in[AMD_SBI_RD_WR_DATA_INDEX]); + + ret =3D regmap_bulk_write(data->regmap, CPUID_MCA_CMD, + &input, MSR_WR_REG_LEN); + if (ret < 0) + goto exit_unlock; + + ret =3D sbrmi_wait_status(data, &hw_status, HW_ALERT_MASK); + if (ret < 0) + goto exit_unlock; + + ret =3D regmap_bulk_read(data->regmap, CPUID_MCA_CMD, + &output, MSR_RD_REG_LEN); + if (ret < 0) + goto exit_unlock; + + ret =3D regmap_write(data->regmap, SBRMI_STATUS, + HW_ALERT_MASK); + if (ret < 0) + goto exit_unlock; + + if (output.num_bytes !=3D MSR_RD_REG_LEN - 1) { + ret =3D -EMSGSIZE; + goto exit_unlock; + } + if (output.status) { + ret =3D -EPROTOTYPE; + msg->fw_ret_code =3D output.status; + goto exit_unlock; + } + msg->data_out.cpu_msr_out =3D output.value; + +exit_unlock: + mutex_unlock(&data->lock); + return ret; +} + int rmi_mailbox_xfer(struct sbrmi_data *data, struct apml_message *msg) { @@ -317,6 +403,10 @@ static long sbrmi_ioctl(struct file *fp, unsigned int = cmd, unsigned long arg) case APML_CPUID: ret =3D rmi_cpuid_read(data, &msg); break; + case APML_MCA_MSR: + /* MCAMSR protocol */ + ret =3D rmi_mca_msr_read(data, &msg); + break; default: pr_err("Command:0x%x not recognized\n", msg.cmd); break; diff --git a/include/uapi/misc/amd-apml.h b/include/uapi/misc/amd-apml.h index 30bb6307993b..8d1fdf2a54f0 100644 --- a/include/uapi/misc/amd-apml.h +++ b/include/uapi/misc/amd-apml.h @@ -7,8 +7,11 @@ =20 #include =20 -/* command ID to identify CPUID protocol */ -#define APML_CPUID 0x1000 +enum apml_protocol { + APML_CPUID =3D 0x1000, + APML_MCA_MSR, +}; + /* These are byte indexes into data_in and data_out arrays */ #define AMD_SBI_RD_WR_DATA_INDEX 0 #define AMD_SBI_REG_OFF_INDEX 0 @@ -24,13 +27,14 @@ struct apml_message { /* message ids: * Mailbox Messages: 0x0 ... 0x999 * APML_CPUID: 0x1000 + * APML_MCA_MSR: 0x1001 */ __u32 cmd; =20 /* * 8 bit data for reg read, * 32 bit data in case of mailbox, - * up to 64 bit in case of cpuid + * up to 64 bit in case of cpuid and mca msr */ union { __u64 cpu_msr_out; @@ -40,8 +44,9 @@ struct apml_message { =20 /* * [0]...[3] mailbox 32bit input - * cpuid, - * [4][5] cpuid: thread + * cpuid & mca msr, + * [4][5] cpuid & mca msr: thread + * [4] rmi reg wr: value * [6] cpuid: ext function & read eax/ebx or ecx/edx * [7:0] -> bits [7:4] -> ext function & * bit [0] read eax/ebx or ecx/edx @@ -53,7 +58,7 @@ struct apml_message { __u8 reg_in[8]; } data_in; /* - * Status code is returned in case of CPUID access + * Status code is returned in case of CPUID/MCA access * Error code is returned in case of soft mailbox */ __u32 fw_ret_code; --=20 2.44.0