From nobody Mon Feb 9 16:54:49 2026 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3B8813E04C; Wed, 14 Aug 2024 07:48:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723621687; cv=none; b=Yrb2WDy6AlIksmZw6Qn8IqP167XW433y3CVAH3udmojZxbM8jE9Gu8ufcMOvm2QNys810gQ0ob+4LcogEo8YRtU8XHoJ69Nl2/vX9o4CPeyMcE8mvwC6XlV/TCi5h1hfiy1GyiBEWXHD3eeuP+6gbXbeIWfAgzqJOb8NJN/kIBU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723621687; c=relaxed/simple; bh=wIL63u0sUgCGeBUxinDgEka6jYsdrZP97prBQiVbpaA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=fKMmOvsoRsEBlgdYLUdHvFxSVL5qb9kq6sXoz7GqOMNXJf1x9uhQZi/8n51OHSrDxkfqxyTXpxtcMoKf9uBIF2LKYtBk/nI6JEk3tNmBD7TZlEeeb5IrwwOryPWE19vwzFPHEPn9nv/rezxboKguOgw7/2aktmpsmn7T09RnCtE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=PiJvlIYV; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="PiJvlIYV" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 47E7lnSd038609; Wed, 14 Aug 2024 02:47:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1723621669; bh=8lkHb1C/YgunbLvMwrwE3WOA+6IBg1dbaT7OBA7VZu4=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=PiJvlIYV16AOVjRxn2VS5jjH3UUy3EKATv6zERNpUyq7FC2ctrj3OauwNrvu0cNdj YKWywgAGWaqO9AVqFDhXDLUm7al7r4GbHr8a/E9BqCPuTymq58/eIbaBkHGvwx/Q78 IBLd/l13IgUg9YBoQO1RQChIHj+44v4tLTdqmn68= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 47E7lnBQ059871 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 14 Aug 2024 02:47:49 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 14 Aug 2024 02:47:49 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 14 Aug 2024 02:47:48 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 47E7lT2H059812; Wed, 14 Aug 2024 02:47:44 -0500 From: Manorit Chawdhry Date: Wed, 14 Aug 2024 13:17:30 +0530 Subject: [PATCH v4 3/5] arm64: dts: ti: k3-am68*: Add bootph-* properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240814-b4-upstream-bootph-all-v4-3-f2b462000f25@ti.com> References: <20240814-b4-upstream-bootph-all-v4-0-f2b462000f25@ti.com> In-Reply-To: <20240814-b4-upstream-bootph-all-v4-0-f2b462000f25@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1723621650; l=4171; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=wIL63u0sUgCGeBUxinDgEka6jYsdrZP97prBQiVbpaA=; b=lk5Gc9K6twkJ577JWFx1tnd7W5q0a+meZNXpAxMLn7BO9J/cxphKMPmLroc8jxgQeaAa4uhDd o24H7g83MsZBQWcSa8otPNHMWtmDsAxHbMWomrXSoPet1wE2/hUyfxp X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Signed-off-by: Manorit Chawdhry Reviewed-by: Udit Kumar --- arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 11 +++++++++++ arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 5 +++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/= boot/dts/ti/k3-am68-sk-base-board.dts index 90dbe31c5b81..e7dd31b49081 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -184,6 +184,7 @@ main_uart8_pins_default: main-uart8-default-pins { J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ >; + bootph-all; }; =20 main_i2c0_pins_default: main-i2c0-default-pins { @@ -210,6 +211,7 @@ J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ >; + bootph-all; }; =20 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { @@ -222,6 +224,7 @@ main_usbss0_pins_default: main-usbss0-default-pins { pinctrl-single,pins =3D < J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ >; + bootph-all; }; =20 main_mcan6_pins_default: main-mcan6-default-pins { @@ -312,6 +315,7 @@ J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_G= PIO0_7.WKUP_UART0_RTSn */ J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ >; + bootph-all; }; =20 mcu_cpsw_pins_default: mcu-cpsw-default-pins { @@ -371,6 +375,7 @@ mcu_uart0_pins_default: mcu-uart0-default-pins { J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0= _RXD */ J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART= 0_TXD */ >; + bootph-all; }; =20 mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-default-pins-0 { @@ -412,6 +417,7 @@ &wkup_uart0 { status =3D "reserved"; pinctrl-names =3D "default"; pinctrl-0 =3D <&wkup_uart0_pins_default>; + bootph-all; }; =20 &wkup_i2c0 { @@ -494,6 +500,7 @@ &mcu_uart0 { status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_uart0_pins_default>; + bootph-all; }; =20 &main_uart8 { @@ -502,6 +509,7 @@ &main_uart8 { pinctrl-0 =3D <&main_uart8_pins_default>; /* Shared with TFA on this platform */ power-domains =3D <&k3_pds 357 TI_SCI_PD_SHARED>; + bootph-all; }; =20 &main_i2c0 { @@ -596,6 +604,7 @@ &main_sdhci1 { disable-wp; vmmc-supply =3D <&vdd_mmc1>; vqmmc-supply =3D <&vdd_sd_dv>; + bootph-all; }; =20 &mcu_cpsw { @@ -727,6 +736,7 @@ &usbss0 { status =3D "okay"; pinctrl-0 =3D <&main_usbss0_pins_default>; pinctrl-names =3D "default"; + bootph-all; ti,vbus-divider; }; =20 @@ -735,4 +745,5 @@ &usb0 { maximum-speed =3D "super-speed"; phys =3D <&serdes0_usb_link>; phy-names =3D "cdns3,usb3-phy"; + bootph-all; }; diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/d= ts/ti/k3-am68-sk-som.dtsi index 5c66e0ec6e82..aab8e6ad0ad2 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi @@ -156,6 +156,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins { J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ >; + bootph-all; }; }; =20 @@ -169,6 +170,7 @@ eeprom@51 { /* AT24C512C-MAHM-T */ compatible =3D "atmel,24c512"; reg =3D <0x51>; + bootph-all; }; }; =20 @@ -190,7 +192,6 @@ flash@0 { cdns,read-delay =3D <4>; =20 partitions { - bootph-all; compatible =3D "fixed-partitions"; #address-cells =3D <1>; #size-cells =3D <1>; @@ -226,9 +227,9 @@ partition@800000 { }; =20 partition@3fc0000 { - bootph-pre-ram; label =3D "ospi.phypattern"; reg =3D <0x3fc0000 0x40000>; + bootph-all; }; }; }; --=20 2.46.0