From nobody Fri Dec 19 04:19:00 2025 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD0434DA00; Wed, 14 Aug 2024 07:47:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723621679; cv=none; b=b+cEg+gBpJRgas6xy6Qpyze9HKKIMEvsr6RV70hVqxXBeISrOBcMEU5naxwRopeyHP4SGoJiImpzb6YXJ2mNqIzNcJireSWzZISVQS/nEYXjdIHVCJA+eW6smPI7mSr/NDPQwcjBBqfGGx42G265Fjwj+MAaO+tJp2qX0VKV0Ds= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723621679; c=relaxed/simple; bh=E18ABw4VmZqc3yGsHecwERFeyMUEihA9E2+JvUrSWcE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=TAvs0K4m0IS/EqbvGJyUR5UeMxdUKXm3TVj1M7kVj4xEPAOXMfkkifscV18qsCB4fy4F4/eCE/901ZDObPpDBEydH1VF5OXX4i9LkzJmsKs2ELCasltY3J5S8f25xg2nmYthE77Oisz+/uIdbkFROaDwa5Y8Oq9JiOCeLriJur4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=rrhuxyKz; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="rrhuxyKz" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 47E7le7C087691; Wed, 14 Aug 2024 02:47:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1723621660; bh=HTE6CIoNEEGXnHWPsTmPYdGJCh1kTwWBMXVzCMoYXAA=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=rrhuxyKzYkTkUYF9nVq6AWugLFsxwPEYBmkn1rFQyOM+bC9mdbK0wKmSz2GxRqh74 k/66oXP0IhjGGbSZLKcrGPxK2EPphvdOVq/AM3JWlSGUipVvaQ+NGyd6NGJ1wbtlOt C/6xUw6pQc9RYq/XcIDgtWQxIy5gOa7t29slrwBc= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 47E7lepw059827 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 14 Aug 2024 02:47:40 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 14 Aug 2024 02:47:39 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 14 Aug 2024 02:47:39 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 47E7lT2F059812; Wed, 14 Aug 2024 02:47:35 -0500 From: Manorit Chawdhry Date: Wed, 14 Aug 2024 13:17:28 +0530 Subject: [PATCH v4 1/5] arm64: dts: ti: k3-j721s2*: Add bootph-* properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240814-b4-upstream-bootph-all-v4-1-f2b462000f25@ti.com> References: <20240814-b4-upstream-bootph-all-v4-0-f2b462000f25@ti.com> In-Reply-To: <20240814-b4-upstream-bootph-all-v4-0-f2b462000f25@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1723621650; l=8791; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=E18ABw4VmZqc3yGsHecwERFeyMUEihA9E2+JvUrSWcE=; b=pL34v6QpLr4pQ/3UBlxIHRLPyuMAawVefIyPcIx6UEQULaTdD4dHu46gBr+xmyWMQsJDo1kYK Gf2L2R3CE6CDpaJjwlsJLBu6wZqi/ll5K6R56aabJVP+IDPgWutJ8c5 X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Reviewed-by: Andrew Davis Signed-off-by: Manorit Chawdhry --- arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 14 ++++++++++++++ arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 4 +++- arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 17 ++++++++++++++= +-- arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 2 ++ 4 files changed, 34 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index c5a0b7cbb14f..3b5f8f08cf32 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -138,6 +138,7 @@ J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR= 1.UART8_RTSn */ J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ >; + bootph-all; }; =20 main_i2c3_pins_default: main-i2c3-default-pins { @@ -165,6 +166,7 @@ J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ >; + bootph-all; }; =20 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { @@ -177,6 +179,7 @@ main_usbss0_pins_default: main-usbss0-default-pins { pinctrl-single,pins =3D < J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ >; + bootph-all; }; =20 main_mcan3_pins_default: main-mcan3-default-pins { @@ -200,6 +203,7 @@ wkup_uart0_pins_default: wkup-uart0-default-pins { J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ >; + bootph-all; }; =20 mcu_uart0_pins_default: mcu-uart0-default-pins { @@ -209,6 +213,7 @@ J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_G= PIO0_15.MCU_UART0_RTSn */ J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0= _RXD */ J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART= 0_TXD */ >; + bootph-all; }; =20 mcu_cpsw_pins_default: mcu-cpsw-default-pins { @@ -301,6 +306,7 @@ J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (A20) MCU_OSP= I1_D3 */ J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ >; + bootph-all; }; }; =20 @@ -316,12 +322,14 @@ &wkup_uart0 { status =3D "reserved"; pinctrl-names =3D "default"; pinctrl-0 =3D <&wkup_uart0_pins_default>; + bootph-all; }; =20 &mcu_uart0 { status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_uart0_pins_default>; + bootph-all; }; =20 &main_uart8 { @@ -330,6 +338,7 @@ &main_uart8 { pinctrl-0 =3D <&main_uart8_pins_default>; /* Shared with TFA on this platform */ power-domains =3D <&k3_pds 357 TI_SCI_PD_SHARED>; + bootph-all; }; =20 &main_i2c0 { @@ -385,6 +394,7 @@ &main_sdhci0 { non-removable; ti,driver-strength-ohm =3D <50>; disable-wp; + bootph-all; }; =20 &main_sdhci1 { @@ -395,6 +405,7 @@ &main_sdhci1 { disable-wp; vmmc-supply =3D <&vdd_mmc1>; vqmmc-supply =3D <&vdd_sd_dv>; + bootph-all; }; =20 &mcu_cpsw { @@ -444,6 +455,7 @@ &usbss0 { status =3D "okay"; pinctrl-0 =3D <&main_usbss0_pins_default>; pinctrl-names =3D "default"; + bootph-all; ti,vbus-divider; ti,usb2-only; }; @@ -451,6 +463,7 @@ &usbss0 { &usb0 { dr_mode =3D "otg"; maximum-speed =3D "high-speed"; + bootph-all; }; =20 &ospi1 { @@ -464,6 +477,7 @@ flash@0 { spi-tx-bus-width =3D <1>; spi-rx-bus-width =3D <4>; spi-max-frequency =3D <40000000>; + bootph-all; cdns,tshsl-ns =3D <60>; cdns,tsd2d-ns =3D <60>; cdns,tchsh-ns =3D <60>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 9ed6949b40e9..0d72dd0b5033 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -816,6 +816,7 @@ secure_proxy_main: mailbox@32c00000 { <0x00 0x32800000 0x00 0x100000>; interrupt-names =3D "rx_011"; interrupts =3D ; + bootph-all; }; =20 hwspinlock: spinlock@30e00000 { @@ -1225,6 +1226,7 @@ usb0: usb@6000000 { interrupt-names =3D "host", "peripheral", "otg"; maximum-speed =3D "super-speed"; dr_mode =3D "otg"; + bootph-all; }; }; =20 @@ -1944,8 +1946,8 @@ c71_1: dsp@65800000 { main_esm: esm@700000 { compatible =3D "ti,j721e-esm"; reg =3D <0x00 0x700000 0x00 0x1000>; - ti,esm-pins =3D <688>, <689>; bootph-pre-ram; + ti,esm-pins =3D <688>, <689>; }; =20 watchdog0: watchdog@2200000 { diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 8feb42c89e47..05a5e35fddcd 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -21,16 +21,19 @@ sms: system-controller@44083000 { k3_pds: power-controller { compatible =3D "ti,sci-pm-domain"; #power-domain-cells =3D <2>; + bootph-all; }; =20 k3_clks: clock-controller { compatible =3D "ti,k2g-sci-clk"; #clock-cells =3D <2>; + bootph-all; }; =20 k3_reset: reset-controller { compatible =3D "ti,sci-reset"; #reset-cells =3D <2>; + bootph-all; }; }; =20 @@ -43,6 +46,7 @@ wkup_conf: bus@43000000 { chipid: chipid@14 { compatible =3D "ti,am654-chipid"; reg =3D <0x14 0x4>; + bootph-all; }; }; =20 @@ -53,6 +57,8 @@ secure_proxy_sa3: mailbox@43600000 { reg =3D <0x00 0x43600000 0x00 0x10000>, <0x00 0x44880000 0x00 0x20000>, <0x00 0x44860000 0x00 0x20000>; + bootph-pre-ram; + /* * Marked Disabled: * Node is incomplete as it is meant for bootloaders and @@ -167,6 +173,7 @@ mcu_timer0: timer@40400000 { assigned-clocks =3D <&k3_clks 35 1>; assigned-clock-parents =3D <&k3_clks 35 2>; power-domains =3D <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + bootph-pre-ram; ti,timer-pwm; /* Non-MPU Firmware usage */ status =3D "reserved"; @@ -361,6 +368,7 @@ wkup_i2c0: i2c@42120000 { clocks =3D <&k3_clks 223 1>; clock-names =3D "fck"; power-domains =3D <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; + bootph-all; status =3D "disabled"; }; =20 @@ -469,6 +477,7 @@ mcu_ringacc: ringacc@2b800000 { <0x0 0x2a500000 0x0 0x40000>, <0x0 0x28440000 0x0 0x40000>; reg-names =3D "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; + bootph-all; ti,num-rings =3D <286>; ti,sci-rm-range-gp-rings =3D <0x1>; ti,sci =3D <&sms>; @@ -488,6 +497,7 @@ mcu_udmap: dma-controller@285c0000 { "tchan", "rchan", "rflow"; msi-parent =3D <&main_udmass_inta>; #dma-cells =3D <1>; + bootph-all; =20 ti,sci =3D <&sms>; ti,sci-dev-id =3D <273>; @@ -507,6 +517,8 @@ secure_proxy_mcu: mailbox@2a480000 { reg =3D <0x00 0x2a480000 0x00 0x80000>, <0x00 0x2a380000 0x00 0x80000>, <0x00 0x2a400000 0x00 0x80000>; + bootph-pre-ram; + /* * Marked Disabled: * Node is incomplete as it is meant for bootloaders and @@ -667,6 +679,7 @@ wkup_vtm0: temperature-sensor@42040000 { <0x00 0x42050000 0x0 0x350>; power-domains =3D <&k3_pds 180 TI_SCI_PD_SHARED>; #thermal-sensor-cells =3D <1>; + bootph-pre-ram; }; =20 mcu_r5fss0: r5fss@41000000 { @@ -712,15 +725,15 @@ mcu_r5fss0_core1: r5f@41400000 { mcu_esm: esm@40800000 { compatible =3D "ti,j721e-esm"; reg =3D <0x00 0x40800000 0x00 0x1000>; - ti,esm-pins =3D <95>; bootph-pre-ram; + ti,esm-pins =3D <95>; }; =20 wkup_esm: esm@42080000 { compatible =3D "ti,j721e-esm"; reg =3D <0x00 0x42080000 0x00 0x1000>; - ti,esm-pins =3D <63>; bootph-pre-ram; + ti,esm-pins =3D <63>; }; =20 /* diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot= /dts/ti/k3-j721s2-som-p0.dtsi index 36136db26a47..c333148f2789 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -170,6 +170,7 @@ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSP= I0_D7 */ J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */ >; 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Wed, 14 Aug 2024 02:47:44 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 47E7lT2G059812; Wed, 14 Aug 2024 02:47:40 -0500 From: Manorit Chawdhry Date: Wed, 14 Aug 2024 13:17:29 +0530 Subject: [PATCH v4 2/5] arm64: dts: ti: k3-j784s4*: Remove bootph properties from parent nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240814-b4-upstream-bootph-all-v4-2-f2b462000f25@ti.com> References: <20240814-b4-upstream-bootph-all-v4-0-f2b462000f25@ti.com> In-Reply-To: <20240814-b4-upstream-bootph-all-v4-0-f2b462000f25@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1723621650; l=4521; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=MnJSlDIzS3p80J0ddGpEn71a3q+1W+2Dm9IKE2uIXN8=; b=Sa+GpxuE06IpbYpQNr0vR74U6FmFemCPtNfAh7bVUaJ/0E020PRQwKyUk2XEwZReIrejA35Pe FIzGOkeNcneBrfi/A+y8zi4Zx+YSQQ9VzhUvrh3KwRzbEi2aofDMQbf X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Removes bootph-* properties from parent nodes and adds bootph for other bootloader nodes. Also moves bootph from mcu_timer1 to mcu_timer0 as that is the one that is used in bootloader. Signed-off-by: Manorit Chawdhry --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 10 +--------- arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 10 ++++++---- 2 files changed, 7 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts= /ti/k3-j784s4-evm.dts index ffa38f41679d..08f4791a3ee8 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -334,7 +334,6 @@ &wkup_gpio0 { }; =20 &main_pmx0 { - bootph-all; main_cpsw2g_default_pins: main-cpsw2g-default-pins { pinctrl-single,pins =3D < J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */ @@ -461,7 +460,6 @@ J784S4_IOPAD(0x078, PIN_OUTPUT, 1) /* (AH37) MCAN2_RX.A= UDIO_EXT_REFCLK1 */ }; =20 &wkup_pmx2 { - bootph-all; wkup_uart0_pins_default: wkup-uart0-default-pins { bootph-all; pinctrl-single,pins =3D < @@ -577,7 +575,6 @@ J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7) }; =20 &wkup_pmx0 { - bootph-all; mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { bootph-all; pinctrl-single,pins =3D < @@ -597,7 +594,6 @@ J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSP= I0_DQS */ }; =20 &wkup_pmx1 { - bootph-all; mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins { bootph-all; pinctrl-single,pins =3D < @@ -668,6 +664,7 @@ bucka12: buck12 { regulator-max-microvolt =3D <1100000>; regulator-boot-on; regulator-always-on; + bootph-pre-ram; }; =20 bucka3: buck3 { @@ -769,18 +766,15 @@ &ufs_wrapper { }; =20 &fss { - bootph-all; status =3D "okay"; }; =20 &ospi0 { - bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_def= ault>; =20 flash@0 { - bootph-all; compatible =3D "jedec,spi-nor"; reg =3D <0x0>; spi-tx-bus-width =3D <8>; @@ -837,13 +831,11 @@ partition@3fc0000 { }; =20 &ospi1 { - bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_fss0_ospi1_pins_default>; =20 flash@0 { - bootph-all; compatible =3D "jedec,spi-nor"; reg =3D <0x0>; spi-tx-bus-width =3D <1>; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index f3a6ed1c979d..6409e702ffd4 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -7,7 +7,6 @@ =20 &cbass_mcu_wakeup { sms: system-controller@44083000 { - bootph-all; compatible =3D "ti,k2g-sci"; ti,host-id =3D <12>; =20 @@ -39,7 +38,6 @@ k3_reset: reset-controller { }; =20 wkup_conf: bus@43000000 { - bootph-all; compatible =3D "simple-bus"; #address-cells =3D <1>; #size-cells =3D <1>; @@ -59,6 +57,8 @@ secure_proxy_sa3: mailbox@43600000 { reg =3D <0x00 0x43600000 0x00 0x10000>, <0x00 0x44880000 0x00 0x20000>, <0x00 0x44860000 0x00 0x20000>; + bootph-pre-ram; + /* * Marked Disabled: * Node is incomplete as it is meant for bootloaders and @@ -172,13 +172,13 @@ mcu_timer0: timer@40400000 { assigned-clocks =3D <&k3_clks 35 2>; assigned-clock-parents =3D <&k3_clks 35 3>; power-domains =3D <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + bootph-all; ti,timer-pwm; /* Non-MPU Firmware usage */ status =3D "reserved"; }; =20 mcu_timer1: timer@40410000 { - bootph-all; compatible =3D "ti,am654-timer"; reg =3D <0x00 0x40410000 0x00 0x400>; interrupts =3D ; @@ -458,7 +458,6 @@ mcu_spi2: spi@40320000 { }; =20 mcu_navss: bus@28380000 { - bootph-all; compatible =3D "simple-bus"; #address-cells =3D <2>; #size-cells =3D <2>; @@ -515,6 +514,8 @@ secure_proxy_mcu: mailbox@2a480000 { reg =3D <0x00 0x2a480000 0x00 0x80000>, <0x00 0x2a380000 0x00 0x80000>, <0x00 0x2a400000 0x00 0x80000>; + bootph-pre-ram; + /* * Marked Disabled: * Node is incomplete as it is meant for bootloaders and @@ -632,6 +633,7 @@ wkup_vtm0: temperature-sensor@42040000 { <0x00 0x42050000 0x00 0x350>; power-domains =3D <&k3_pds 243 TI_SCI_PD_SHARED>; #thermal-sensor-cells =3D <1>; + bootph-pre-ram; }; =20 tscadc0: tscadc@40200000 { --=20 2.46.0 From nobody Fri Dec 19 04:19:00 2025 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3B8813E04C; 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Wed, 14 Aug 2024 02:47:49 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 14 Aug 2024 02:47:49 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 14 Aug 2024 02:47:48 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 47E7lT2H059812; Wed, 14 Aug 2024 02:47:44 -0500 From: Manorit Chawdhry Date: Wed, 14 Aug 2024 13:17:30 +0530 Subject: [PATCH v4 3/5] arm64: dts: ti: k3-am68*: Add bootph-* properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240814-b4-upstream-bootph-all-v4-3-f2b462000f25@ti.com> References: <20240814-b4-upstream-bootph-all-v4-0-f2b462000f25@ti.com> In-Reply-To: <20240814-b4-upstream-bootph-all-v4-0-f2b462000f25@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1723621650; l=4171; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=wIL63u0sUgCGeBUxinDgEka6jYsdrZP97prBQiVbpaA=; b=lk5Gc9K6twkJ577JWFx1tnd7W5q0a+meZNXpAxMLn7BO9J/cxphKMPmLroc8jxgQeaAa4uhDd o24H7g83MsZBQWcSa8otPNHMWtmDsAxHbMWomrXSoPet1wE2/hUyfxp X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Signed-off-by: Manorit Chawdhry Reviewed-by: Udit Kumar --- arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 11 +++++++++++ arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 5 +++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/= boot/dts/ti/k3-am68-sk-base-board.dts index 90dbe31c5b81..e7dd31b49081 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -184,6 +184,7 @@ main_uart8_pins_default: main-uart8-default-pins { J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ >; + bootph-all; }; =20 main_i2c0_pins_default: main-i2c0-default-pins { @@ -210,6 +211,7 @@ J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ >; + bootph-all; }; =20 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { @@ -222,6 +224,7 @@ main_usbss0_pins_default: main-usbss0-default-pins { pinctrl-single,pins =3D < J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ >; + bootph-all; }; =20 main_mcan6_pins_default: main-mcan6-default-pins { @@ -312,6 +315,7 @@ J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_G= PIO0_7.WKUP_UART0_RTSn */ J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ >; + bootph-all; }; =20 mcu_cpsw_pins_default: mcu-cpsw-default-pins { @@ -371,6 +375,7 @@ mcu_uart0_pins_default: mcu-uart0-default-pins { J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0= _RXD */ J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART= 0_TXD */ >; + bootph-all; }; =20 mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-default-pins-0 { @@ -412,6 +417,7 @@ &wkup_uart0 { status =3D "reserved"; pinctrl-names =3D "default"; pinctrl-0 =3D <&wkup_uart0_pins_default>; + bootph-all; }; =20 &wkup_i2c0 { @@ -494,6 +500,7 @@ &mcu_uart0 { status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_uart0_pins_default>; + bootph-all; }; =20 &main_uart8 { @@ -502,6 +509,7 @@ &main_uart8 { pinctrl-0 =3D <&main_uart8_pins_default>; /* Shared with TFA on this platform */ power-domains =3D <&k3_pds 357 TI_SCI_PD_SHARED>; + bootph-all; }; =20 &main_i2c0 { @@ -596,6 +604,7 @@ &main_sdhci1 { disable-wp; vmmc-supply =3D <&vdd_mmc1>; vqmmc-supply =3D <&vdd_sd_dv>; + bootph-all; }; =20 &mcu_cpsw { @@ -727,6 +736,7 @@ &usbss0 { status =3D "okay"; pinctrl-0 =3D <&main_usbss0_pins_default>; pinctrl-names =3D "default"; + bootph-all; ti,vbus-divider; }; =20 @@ -735,4 +745,5 @@ &usb0 { maximum-speed =3D "super-speed"; phys =3D <&serdes0_usb_link>; phy-names =3D "cdns3,usb3-phy"; + bootph-all; }; diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/d= ts/ti/k3-am68-sk-som.dtsi index 5c66e0ec6e82..aab8e6ad0ad2 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi @@ -156,6 +156,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins { J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ >; 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Wed, 14 Aug 2024 02:47:53 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 47E7lT2I059812; Wed, 14 Aug 2024 02:47:49 -0500 From: Manorit Chawdhry Date: Wed, 14 Aug 2024 13:17:31 +0530 Subject: [PATCH v4 4/5] arm64: dts: ti: k3-j721e*: Add bootph-* properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240814-b4-upstream-bootph-all-v4-4-f2b462000f25@ti.com> References: <20240814-b4-upstream-bootph-all-v4-0-f2b462000f25@ti.com> In-Reply-To: <20240814-b4-upstream-bootph-all-v4-0-f2b462000f25@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1723621650; l=14362; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=Kvq0Lxt7KlsIJNSSVChxjgfC1uEMTKi152AiPZa+D0w=; b=HARvdwkcBlX9s/+VUZQCu8pKXZhZ6uv0VGsqfST0aLF8XVkCSDU/43vmXH8uRJ+Esq3doqBqr 00Qy1BpQPDYDu9XzRKCHVFpvUuaee3ZH5yleMpwXCA1/oESYmy/TXVI X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Reviewed-by: Neha Malcom Francis Signed-off-by: Manorit Chawdhry --- .../arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 20 ++++++++++++++++= ++++ arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 12 +++++++++++- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 18 ++++++++++++++++= ++ arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 5 +++++ 5 files changed, 56 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 8230d53cd696..cc21ce51b2ce 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -193,6 +193,7 @@ J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UAR= T0_RTSn */ J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ >; + bootph-all; }; =20 main_uart1_pins_default: main-uart1-default-pins { @@ -234,6 +235,7 @@ J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */ >; + bootph-all; }; =20 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { @@ -247,6 +249,7 @@ main_usbss0_pins_default: main-usbss0-default-pins { J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ >; + bootph-all; }; =20 main_usbss1_pins_default: main-usbss1-default-pins { @@ -272,6 +275,7 @@ main_i2c0_pins_default: main-i2c0-default-pins { J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ >; + bootph-all; }; =20 main_i2c1_pins_default: main-i2c1-default-pins { @@ -342,6 +346,7 @@ wkup_uart0_pins_default: wkup-uart0-default-pins { J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ >; + bootph-all; }; =20 mcu_uart0_pins_default: mcu-uart0-default-pins { @@ -351,6 +356,7 @@ J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPI= O0_15.MCU_UART0_RTSn */ J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_R= XD */ J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_= TXD */ >; + bootph-all; }; =20 sw11_button_pins_default: sw11-button-default-pins { @@ -370,6 +376,7 @@ J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1= _D3 */ J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */ J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */ >; + bootph-all; }; =20 mcu_cpsw_pins_default: mcu-cpsw-default-pins { @@ -427,6 +434,7 @@ wkup_gpio_pins_default: wkup-gpio-default-pins { pinctrl-single,pins =3D < J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */ >; + bootph-all; }; }; =20 @@ -435,12 +443,14 @@ &wkup_uart0 { status =3D "reserved"; pinctrl-names =3D "default"; pinctrl-0 =3D <&wkup_uart0_pins_default>; + bootph-all; }; =20 &mcu_uart0 { status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_uart0_pins_default>; + bootph-all; }; =20 &main_uart0 { @@ -449,6 +459,7 @@ &main_uart0 { pinctrl-0 =3D <&main_uart0_pins_default>; /* Shared with ATF on this platform */ power-domains =3D <&k3_pds 146 TI_SCI_PD_SHARED>; + bootph-all; }; =20 &main_uart1 { @@ -473,6 +484,7 @@ &wkup_gpio0 { status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&wkup_gpio_pins_default>; + bootph-all; }; =20 &main_gpio0 { @@ -489,6 +501,7 @@ &main_sdhci0 { non-removable; ti,driver-strength-ohm =3D <50>; disable-wp; + bootph-all; }; =20 &main_sdhci1 { @@ -500,10 +513,12 @@ &main_sdhci1 { pinctrl-0 =3D <&main_mmc1_pins_default>; ti,driver-strength-ohm =3D <50>; disable-wp; + bootph-all; }; =20 &usb_serdes_mux { idle-states =3D <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */ + bootph-all; }; =20 &serdes_ln_ctrl { @@ -513,6 +528,7 @@ &serdes_ln_ctrl { , , , , , ; + bootph-all; }; =20 &serdes_wiz3 { @@ -533,6 +549,7 @@ serdes3_usb_link: phy@0 { &usbss0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_usbss0_pins_default>; + bootph-all; ti,vbus-divider; }; =20 @@ -541,6 +558,7 @@ &usb0 { maximum-speed =3D "super-speed"; phys =3D <&serdes3_usb_link>; phy-names =3D "cdns3,usb3-phy"; + bootph-all; }; =20 &usbss1 { @@ -613,6 +631,7 @@ partition@800000 { partition@3fe0000 { label =3D "qspi.phypattern"; reg =3D <0x3fe0000 0x20000>; + bootph-all; }; }; }; @@ -650,6 +669,7 @@ exp2: gpio@22 { reg =3D <0x22>; gpio-controller; #gpio-cells =3D <2>; + bootph-all; =20 p09-hog { /* P11 - MCASP/TRACE_MUX_S0 */ diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j721e-main.dtsi index 0da785be80ff..af3d730154ac 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -226,6 +226,7 @@ secure_proxy_main: mailbox@32c00000 { <0x00 0x32800000 0x00 0x100000>; interrupt-names =3D "rx_011"; interrupts =3D ; + bootph-all; }; =20 smmu0: iommu@36600000 { @@ -2853,6 +2854,7 @@ main_spi7: spi@2170000 { main_esm: esm@700000 { compatible =3D "ti,j721e-esm"; reg =3D <0x0 0x700000 0x0 0x1000>; + bootph-pre-ram; ti,esm-pins =3D <344>, <345>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 6b6ef6a30614..425a5dedaa74 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -21,16 +21,19 @@ dmsc: system-controller@44083000 { k3_pds: power-controller { compatible =3D "ti,sci-pm-domain"; #power-domain-cells =3D <2>; + bootph-all; }; =20 k3_clks: clock-controller { compatible =3D "ti,k2g-sci-clk"; #clock-cells =3D <2>; + bootph-all; }; =20 k3_reset: reset-controller { compatible =3D "ti,sci-reset"; #reset-cells =3D <2>; + bootph-all; }; }; =20 @@ -61,6 +64,7 @@ wkup_conf: bus@43000000 { chipid: chipid@14 { compatible =3D "ti,am654-chipid"; reg =3D <0x14 0x4>; + bootph-all; }; }; =20 @@ -112,6 +116,7 @@ mcu_timer0: timer@40400000 { assigned-clocks =3D <&k3_clks 35 1>; assigned-clock-parents =3D <&k3_clks 35 2>; power-domains =3D <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + bootph-pre-ram; ti,timer-pwm; /* Non-MPU Firmware usage */ status =3D "reserved"; @@ -362,6 +367,7 @@ hbmc_mux: mux-controller@47000004 { reg =3D <0x00 0x47000004 0x00 0x4>; #mux-control-cells =3D <1>; mux-reg-masks =3D <0x0 0x2>; /* HBMC select */ + bootph-all; }; =20 hbmc: hyperbus@47034000 { @@ -470,6 +476,7 @@ mcu_ringacc: ringacc@2b800000 { <0x0 0x2a500000 0x0 0x40000>, <0x0 0x28440000 0x0 0x40000>; reg-names =3D "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; + bootph-all; ti,num-rings =3D <286>; ti,sci-rm-range-gp-rings =3D <0x1>; /* GP ring range */ ti,sci =3D <&dmsc>; @@ -489,6 +496,7 @@ mcu_udmap: dma-controller@285c0000 { "tchan", "rchan", "rflow"; msi-parent =3D <&main_udmass_inta>; #dma-cells =3D <1>; + bootph-all; =20 ti,sci =3D <&dmsc>; ti,sci-dev-id =3D <236>; @@ -509,6 +517,7 @@ secure_proxy_mcu: mailbox@2a480000 { reg =3D <0x0 0x2a480000 0x0 0x80000>, <0x0 0x2a380000 0x0 0x80000>, <0x0 0x2a400000 0x0 0x80000>; + bootph-pre-ram; /* * Marked Disabled: * Node is incomplete as it is meant for bootloaders and @@ -687,12 +696,13 @@ wkup_vtm0: temperature-sensor@42040000 { <0x00 0x43000300 0x00 0x10>; power-domains =3D <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; #thermal-sensor-cells =3D <1>; + bootph-pre-ram; }; =20 mcu_esm: esm@40800000 { compatible =3D "ti,j721e-esm"; reg =3D <0x00 0x40800000 0x00 0x1000>; - ti,esm-pins =3D <95>; bootph-pre-ram; + ti,esm-pins =3D <95>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/t= i/k3-j721e-sk.dts index 89fbfb21e5d3..2ce81eb84ac6 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -346,6 +346,7 @@ J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ >; + bootph-all; }; =20 main_uart0_pins_default: main-uart0-default-pins { @@ -355,6 +356,7 @@ J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */ J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ >; + bootph-all; }; =20 main_uart1_pins_default: main-uart1-default-pins { @@ -390,12 +392,14 @@ main_usbss0_pins_default: main-usbss0-default-pins { J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ >; + bootph-all; }; =20 main_usbss1_pins_default: main-usbss1-default-pins { pinctrl-single,pins =3D < J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ >; + bootph-all; }; =20 main_csi_mux_sel_pins_default: main-csi-mux-sel-default-pins { @@ -594,6 +598,7 @@ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0= _D6 */ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */ J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */ >; + bootph-all; }; =20 vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins { @@ -622,6 +627,7 @@ J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_= SDA.MCU_UART0_RTSn */ J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_R= XD */ J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_T= XD */ >; + bootph-all; }; =20 wkup_i2c0_pins_default: wkup-i2c0-default-pins { @@ -629,6 +635,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins { J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ >; + bootph-all; }; =20 mcu_mcan0_pins_default: mcu-mcan0-default-pins { @@ -657,6 +664,7 @@ &wkup_uart0 { status =3D "reserved"; pinctrl-names =3D "default"; pinctrl-0 =3D <&wkup_uart0_pins_default>; + bootph-all; }; =20 &wkup_i2c0 { @@ -821,6 +829,7 @@ &mcu_uart0 { status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_uart0_pins_default>; + bootph-all; }; =20 &main_uart0 { @@ -829,6 +838,7 @@ &main_uart0 { pinctrl-0 =3D <&main_uart0_pins_default>; /* Shared with ATF on this platform */ power-domains =3D <&k3_pds 146 TI_SCI_PD_SHARED>; + bootph-all; }; =20 &main_uart1 { @@ -846,6 +856,7 @@ &main_sdhci1 { pinctrl-0 =3D <&main_mmc1_pins_default>; ti,driver-strength-ohm =3D <50>; disable-wp; + bootph-all; }; =20 &ospi0 { @@ -908,6 +919,7 @@ partition@800000 { partition@3fc0000 { label =3D "ospi.phypattern"; reg =3D <0x3fc0000 0x40000>; + bootph-all; }; }; }; @@ -1003,6 +1015,7 @@ &wkup_gpio0 { =20 &usb_serdes_mux { idle-states =3D <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ + bootph-all; }; =20 &serdes_ln_ctrl { @@ -1012,6 +1025,7 @@ &serdes_ln_ctrl { , , , , , ; + bootph-all; }; =20 &serdes_wiz3 { @@ -1050,6 +1064,7 @@ &mhdp { &usbss0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_usbss0_pins_default>; + bootph-all; ti,vbus-divider; }; =20 @@ -1058,6 +1073,7 @@ &usb0 { maximum-speed =3D "super-speed"; phys =3D <&serdes3_usb_link>; phy-names =3D "cdns3,usb3-phy"; + bootph-all; }; =20 &serdes2 { @@ -1073,6 +1089,7 @@ serdes2_usb_link: phy@1 { &usbss1 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_usbss1_pins_default>; + bootph-all; ti,vbus-divider; }; =20 @@ -1081,6 +1098,7 @@ &usb1 { maximum-speed =3D "super-speed"; phys =3D <&serdes2_usb_link>; phy-names =3D "cdns3,usb3-phy"; + bootph-all; }; =20 &mcu_cpsw { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/= dts/ti/k3-j721e-som-p0.dtsi index 5ba947771b84..100cc7a59576 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -151,6 +151,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins { J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ >; + bootph-all; }; =20 pmic_irq_pins_default: pmic-irq-default-pins { @@ -173,6 +174,7 @@ J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6= */ J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ >; + bootph-all; }; =20 mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins { @@ -192,6 +194,7 @@ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* MCU_HYPERBUS0_= DQ5 */ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ6 */ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ7 */ >; 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Wed, 14 Aug 2024 02:47:58 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 47E7lT2J059812; Wed, 14 Aug 2024 02:47:54 -0500 From: Manorit Chawdhry Date: Wed, 14 Aug 2024 13:17:32 +0530 Subject: [PATCH v4 5/5] arm64: dts: ti: k3-j7200*: Add bootph-* properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240814-b4-upstream-bootph-all-v4-5-f2b462000f25@ti.com> References: <20240814-b4-upstream-bootph-all-v4-0-f2b462000f25@ti.com> In-Reply-To: <20240814-b4-upstream-bootph-all-v4-0-f2b462000f25@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1723621650; l=9880; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=aHj/7FNn0DoPn17r60UPCCEoxDsKo0OQksFH02RaHKU=; b=GNfXWZYTEA30vviK7G/EaAhzE4OO3NEBl1khCWx9KMHXbN6Z5tVsyLYx0j3XTC4wBC4W78tH1 ZmrTqEkYOD+Cp/F2y0d6N1xPxtnTIpPlT8EgkwwbWcfZjunWr8KosBW X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Reviewed-by: Aniket Limaye Signed-off-by: Manorit Chawdhry --- .../arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 20 ++++++++++++++++= ++++ arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 13 ++++++++++++- arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 7 +++++++ 4 files changed, 41 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 6593c5da82c0..134a43346c13 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -129,6 +129,7 @@ J721E_WKUP_IOPAD(0x94, PIN_OUTPUT, 0) /* (E21) MCU_UART= 0_RTSn */ J721E_WKUP_IOPAD(0x8c, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ J721E_WKUP_IOPAD(0x88, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ >; + bootph-all; }; =20 wkup_uart0_pins_default: wkup-uart0-default-pins { @@ -136,6 +137,7 @@ wkup_uart0_pins_default: wkup-uart0-default-pins { J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ J721E_WKUP_IOPAD(0x4c, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ >; + bootph-all; }; =20 mcu_cpsw_pins_default: mcu-cpsw-default-pins { @@ -159,6 +161,7 @@ wkup_gpio_pins_default: wkup-gpio-default-pins { pinctrl-single,pins =3D < J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */ >; + bootph-all; }; =20 mcu_mdio_pins_default: mcu-mdio1-default-pins { @@ -204,6 +207,7 @@ J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */ J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */ J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */ >; + bootph-all; }; =20 main_uart1_pins_default: main-uart1-default-pins { @@ -238,6 +242,7 @@ J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */ J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */ J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */ >; + bootph-all; }; =20 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { @@ -259,6 +264,7 @@ main_usbss0_pins_default: main-usbss0-default-pins { pinctrl-single,pins =3D < J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ >; + bootph-all; }; }; =20 @@ -267,12 +273,14 @@ &wkup_uart0 { status =3D "reserved"; pinctrl-names =3D "default"; pinctrl-0 =3D <&wkup_uart0_pins_default>; + bootph-all; }; =20 &mcu_uart0 { status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_uart0_pins_default>; + bootph-all; }; =20 &main_uart0 { @@ -281,6 +289,7 @@ &main_uart0 { power-domains =3D <&k3_pds 146 TI_SCI_PD_SHARED>; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_uart0_pins_default>; + bootph-all; }; =20 &main_uart1 { @@ -310,6 +319,7 @@ &wkup_gpio0 { status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&wkup_gpio_pins_default>; + bootph-all; }; =20 &mcu_cpsw { @@ -341,6 +351,7 @@ exp1: gpio@20 { reg =3D <0x20>; gpio-controller; #gpio-cells =3D <2>; + bootph-all; }; =20 exp2: gpio@22 { @@ -348,6 +359,7 @@ exp2: gpio@22 { reg =3D <0x22>; gpio-controller; #gpio-cells =3D <2>; + bootph-all; }; }; =20 @@ -381,6 +393,7 @@ &main_sdhci0 { non-removable; ti,driver-strength-ohm =3D <50>; disable-wp; + bootph-all; }; =20 &main_sdhci1 { @@ -392,20 +405,24 @@ &main_sdhci1 { vqmmc-supply =3D <&vdd_sd_dv>; ti,driver-strength-ohm =3D <50>; disable-wp; + bootph-all; }; =20 &serdes_ln_ctrl { idle-states =3D , , , ; + bootph-all; }; =20 &usb_serdes_mux { idle-states =3D <1>; /* USB0 to SERDES lane 3 */ + bootph-all; }; =20 &usbss0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_usbss0_pins_default>; + bootph-all; ti,vbus-divider; ti,usb2-only; }; @@ -413,6 +430,7 @@ &usbss0 { &usb0 { dr_mode =3D "otg"; maximum-speed =3D "high-speed"; + bootph-all; }; =20 &tscadc0 { @@ -432,6 +450,7 @@ serdes0_pcie_link: phy@0 { #phy-cells =3D <0>; cdns,phy-type =3D ; resets =3D <&serdes_wiz0 1>, <&serdes_wiz0 2>; + bootph-all; }; =20 serdes0_qsgmii_link: phy@1 { @@ -440,6 +459,7 @@ serdes0_qsgmii_link: phy@1 { #phy-cells =3D <0>; cdns,phy-type =3D ; resets =3D <&serdes_wiz0 3>; + bootph-all; }; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j7200-main.dtsi index 9386bf3ef9f6..ac9c0a939461 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -136,6 +136,7 @@ secure_proxy_main: mailbox@32c00000 { <0x00 0x32800000 0x00 0x100000>; interrupt-names =3D "rx_011"; interrupts =3D ; + bootph-all; }; =20 hwspinlock: spinlock@30e00000 { @@ -1527,6 +1528,7 @@ main_r5fss0_core1: r5f@5d00000 { main_esm: esm@700000 { compatible =3D "ti,j721e-esm"; reg =3D <0x0 0x700000 0x0 0x1000>; + bootph-pre-ram; ti,esm-pins =3D <656>, <657>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 5097d192c2b2..7fc6f268bfe6 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -21,16 +21,19 @@ dmsc: system-controller@44083000 { k3_pds: power-controller { compatible =3D "ti,sci-pm-domain"; #power-domain-cells =3D <2>; + bootph-all; }; =20 k3_clks: clock-controller { compatible =3D "ti,k2g-sci-clk"; #clock-cells =3D <2>; + bootph-all; }; =20 k3_reset: reset-controller { compatible =3D "ti,sci-reset"; #reset-cells =3D <2>; + bootph-all; }; }; =20 @@ -44,6 +47,7 @@ mcu_timer0: timer@40400000 { assigned-clocks =3D <&k3_clks 35 1>; assigned-clock-parents =3D <&k3_clks 35 2>; power-domains =3D <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + bootph-pre-ram; ti,timer-pwm; }; =20 @@ -191,6 +195,7 @@ wkup_conf: bus@43000000 { chipid: chipid@14 { compatible =3D "ti,am654-chipid"; reg =3D <0x14 0x4>; + bootph-all; }; }; =20 @@ -344,6 +349,7 @@ mcu_ringacc: ringacc@2b800000 { <0x00 0x28440000 0x00 0x40000>; reg-names =3D "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; + bootph-all; ti,num-rings =3D <286>; ti,sci-rm-range-gp-rings =3D <0x1>; /* GP ring range */ ti,sci =3D <&dmsc>; @@ -363,6 +369,7 @@ mcu_udmap: dma-controller@285c0000 { "tchan", "rchan", "rflow"; msi-parent =3D <&main_udmass_inta>; #dma-cells =3D <1>; + bootph-all; =20 ti,sci =3D <&dmsc>; ti,sci-dev-id =3D <236>; @@ -383,6 +390,8 @@ secure_proxy_mcu: mailbox@2a480000 { reg =3D <0x0 0x2a480000 0x0 0x80000>, <0x0 0x2a380000 0x0 0x80000>, <0x0 0x2a400000 0x0 0x80000>; + bootph-pre-ram; + /* * Marked Disabled: * Node is incomplete as it is meant for bootloaders and @@ -534,6 +543,7 @@ hbmc_mux: mux-controller@47000004 { reg =3D <0x00 0x47000004 0x00 0x4>; #mux-control-cells =3D <1>; mux-reg-masks =3D <0x0 0x2>; /* HBMC select */ + bootph-all; }; =20 hbmc: hyperbus@47034000 { @@ -652,13 +662,14 @@ wkup_vtm0: temperature-sensor@42040000 { <0x00 0x42050000 0x00 0x350>; power-domains =3D <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; #thermal-sensor-cells =3D <1>; + bootph-pre-ram; }; =20 mcu_esm: esm@40800000 { compatible =3D "ti,j721e-esm"; reg =3D <0x00 0x40800000 0x00 0x1000>; - ti,esm-pins =3D <95>; bootph-pre-ram; + ti,esm-pins =3D <95>; }; =20 mcu_mcan0: can@40528000 { diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/= dts/ti/k3-j7200-som-p0.dtsi index 89b68325e4e2..2b4aa02b2077 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -121,6 +121,7 @@ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_= D5.MCU_HYPERBUS0_DQ5 */ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0= _DQ6 */ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0= _DQ7 */ >; + bootph-all; }; =20 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { @@ -137,6 +138,7 @@ J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6= */ J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ >; + bootph-all; }; }; =20 @@ -146,6 +148,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins { J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */ J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ >; + bootph-all; }; }; =20 @@ -163,6 +166,7 @@ main_i2c0_pins_default: main-i2c0-default-pins { J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ >; + bootph-all; }; =20 main_mcan0_pins_default: main-mcan0-default-pins { @@ -186,6 +190,7 @@ &hbmc { flash@0,0 { compatible =3D "cypress,hyperflash", "cfi-flash"; reg =3D <0x00 0x00 0x4000000>; + bootph-all; =20 partitions { compatible =3D "fixed-partitions"; @@ -330,6 +335,7 @@ bucka1: buck1 { regulator-max-microvolt =3D <1800000>; regulator-boot-on; regulator-always-on; + bootph-all; }; =20 bucka2: buck2 { @@ -503,6 +509,7 @@ partition@800000 { partition@3fc0000 { label =3D "ospi.phypattern"; reg =3D <0x3fc0000 0x40000>; + bootph-all; }; }; }; --=20 2.46.0