From nobody Fri Dec 19 16:06:18 2025 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EFF4816DEA9; Tue, 13 Aug 2024 23:03:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723590209; cv=none; b=Vqrlx8ZKjw6DHYZRiHFStyNoLaqQOigrE5+M9/IiU0lZOuNx0lfssWj3MgYY+FdqmGKpR20X/izJY441L38F8V7j2MbQvvoqISpVlag0d4z78oTU7f/LA1FlnuVYRju+M7BhYqr/AMtDrYCzv88RCqzby4Vyho4QKY4r8ZR/mL4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723590209; c=relaxed/simple; bh=c9atz1oVyaKQqGu9LyFP6Irr7fN60a3IRcLA7/QU9qY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=p9JBqg9sbvtOKZZ6dkuIQqHCqxSlyz7NldnmO7lSwDlbIWsZ3mdMGbjeYT9UQTeuWIRBuLbL4tjCCtj4o9Y0rPO+6Xlw7E9TG2mIZd9zzSVztIypkiYR2jBkazQgTxJhedOHJaXQ+7D8NAwh/oE+h2uDtpsX76xatAP0MEppWZ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=AbV3OSDa; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="AbV3OSDa" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 47DN3Lwn099211; Tue, 13 Aug 2024 18:03:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1723590201; bh=PVOe6aH9/bfKo9BOInR25L5zNVD08picT0YatODE5rM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=AbV3OSDakivMurob+f+IZMB2/vJ5F7Jct/SD7XTP1/YwoIb0HkLoHrkt2sqzm7zXi t+zN80vJfw8tKaqLZFNgenDovRZZoMzubt0m2qJNq0/MgAeFTDemYwDpnVd4UySwfM NKIhcObT8ccmeAfIVrEZ+kd43eLLkE4lwrwcaBg8= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 47DN3Lol087055 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 13 Aug 2024 18:03:21 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 13 Aug 2024 18:03:21 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 13 Aug 2024 18:03:21 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 47DN3Khm026425; Tue, 13 Aug 2024 18:03:21 -0500 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon CC: Vignesh Raghavendra , , , Jan Kiszka , Judith Mendez Subject: [PATCH v2 1/6] arm64: dts: ti: k3-am62a: Add ESM nodes Date: Tue, 13 Aug 2024 18:03:07 -0500 Message-ID: <20240813230312.3289428-2-jm@ti.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240813230312.3289428-1-jm@ti.com> References: <20240813230312.3289428-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" Add Error Signaling Module (ESM) instances in MCU and MAIN domains, set ESM interrupt sources for rti as per TRM [0] 10.4 Interrupt Sources. Add comments to describe what interrupt sources are routed to ESM modules. [0] https://www.ti.com/lit/ug/spruj16b/spruj16b.pdf Signed-off-by: Judith Mendez --- Changes since v1: - Add bootph flag - Add comment to ESM nodes --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 8 ++++++++ arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-am62a-main.dtsi index 916fcf3cc57d1..8c35293c3d2b0 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -265,6 +265,14 @@ main_pmx0: pinctrl@f4000 { pinctrl-single,function-mask =3D <0xffffffff>; }; =20 + main_esm: esm@420000 { + compatible =3D "ti,j721e-esm"; + reg =3D <0x0 0x420000 0x0 0x1000>; + /* Interrupt sources: rti0, rti1, wrti0, rti4, rti2, rti3 */ + ti,esm-pins =3D <192>, <193>, <195>, <204>, <209>, <210>; + bootph-pre-ram; + }; + main_timer0: timer@2400000 { compatible =3D "ti,am654-timer"; reg =3D <0x00 0x2400000 0x00 0x400>; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts= /ti/k3-am62a-mcu.dtsi index 8c36e56f41388..a5ca4ce523a46 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi @@ -15,6 +15,14 @@ mcu_pmx0: pinctrl@4084000 { status =3D "disabled"; }; =20 + mcu_esm: esm@4100000 { + compatible =3D "ti,j721e-esm"; + reg =3D <0x0 0x4100000 0x0 0x1000>; + /* Interrupt sources: esm0_cfg, esm0_hi, esm0_low, mrti0 */ + ti,esm-pins =3D <0>, <1>, <2>, <85>; + bootph-pre-ram; + }; + /* * The MCU domain timer interrupts are routed only to the ESM module, * and not currently available for Linux. The MCU domain timers are --=20 2.46.0 From nobody Fri Dec 19 16:06:18 2025 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0C751AC438; Tue, 13 Aug 2024 23:03:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723590210; cv=none; b=c6sQYYnyisc13yrK9euUHmAr2ej/Pek0M6kz4WMCGctz+R8XrwcxWHrNXUAX0rlFAxlcLvWY0qAMiB6YIz/8/7mcUFrIAi7ZWULvYwVj0XDKN/UMYnsk9tv99UoZpthuwjaeCPeoaIQ9lh75UXRIfuAksHBcSFvJVS+yGbXaE7M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723590210; c=relaxed/simple; bh=jFgRU4QLs3xhkkmaXBhRpSZc7851Cih4nn9TUODBu+k=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PgYVmkakaxpxhpR+QAMcvWnTh7i4pqh9mmkmCVe6l1doRrVCdtU6cV3Y17ekUYwRXHZDLhDwt7FIf+ByKT3G0FYVFA4zrj3wdOzOKHHi2S5IABk5TZomlnOm5KA3lPAvJ7OquC12lvOdEgRJ3fkzI9e6w1IyUWG8lN+dLqw2PRA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=h7CRviJa; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="h7CRviJa" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 47DN3Mf0034179; Tue, 13 Aug 2024 18:03:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1723590202; bh=JfbzJd3CTvNYSfJ+E107WsKEBy9UnpH5DGqvNLDwKOY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=h7CRviJa2aXQsmtE3xtzqxv9qz161SDUxsUA3LquWDcfzEBEOVDBMo3UdoBtd/xE+ nDyh9ZQUGpAGpC2x7cLIsOXn6XCqZ92YNb5eyQRAt53Gc8mnZlewvCmCSk8BW8K7sT M6G+GkLRYItmvqT8rtuijwe28b4D3RNpy2w4KlTU= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 47DN3MMQ025574 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 13 Aug 2024 18:03:22 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 13 Aug 2024 18:03:22 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 13 Aug 2024 18:03:22 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 47DN3Khn026425; Tue, 13 Aug 2024 18:03:21 -0500 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon CC: Vignesh Raghavendra , , , Jan Kiszka , Judith Mendez Subject: [PATCH v2 2/6] arm64: dts: ti: k3-am62p: Fix ESM interrupt sources Date: Tue, 13 Aug 2024 18:03:08 -0500 Message-ID: <20240813230312.3289428-3-jm@ti.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240813230312.3289428-1-jm@ti.com> References: <20240813230312.3289428-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" Fix interrupt sources for rti routed to the ESM0 as per [0], in 10.4 Interrupt Sources Add comments to describe what interrupt sources are routed to ESM modules. [0] https://www.ti.com/lit/ug/spruj83/spruj83.pdf Fixes: b5080c7c1f7e ("arm64: dts: ti: k3-am62p: Add nodes for more IPs") Signed-off-by: Judith Mendez --- Changes since v1: - Add comment to ESM nodes - Add more interrupt sources to ESM nodes --- arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 3 ++- arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi | 5 +++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/= arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi index 9701fc69aed94..7941aab09cf72 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi @@ -260,7 +260,8 @@ main_pmx0: pinctrl@f4000 { main_esm: esm@420000 { compatible =3D "ti,j721e-esm"; reg =3D <0x00 0x420000 0x00 0x1000>; - ti,esm-pins =3D <160>, <161>, <162>, <163>, <177>, <178>; + /* Interrupt sources: rti0, rti1, wrti0 rti2, rti3, rti15 */ + ti,esm-pins =3D <224>, <225>, <227>, <241>, <242>, <248>; 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charset="utf-8" From: Santhosh Kumar K Remove 'reserved' status for MCU ESM node. Watchdog reset is propagated through ESM0 to MCU ESM to reset the CPU, so enable MCU ESM to reset the CPU with watchdog timeout. Signed-off-by: Santhosh Kumar K [Judith: Fix commit message] Signed-off-by: Judith Mendez --- Changes since v1: - Fix commit mesage --- arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi b/arch/a= rm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi index 49dda340752aa..625d353b97600 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi @@ -29,7 +29,6 @@ mcu_esm: esm@4100000 { /* Interrupt sources: esm0_cfg, esm0_hi, esm0_low, mrti0, wrti0 */ ti,esm-pins =3D <0>, <1>, <2>, <85>, <86>; bootph-pre-ram; - status =3D "reserved"; }; =20 /* --=20 2.46.0 From nobody Fri Dec 19 16:06:18 2025 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72AF11AC452; Tue, 13 Aug 2024 23:03:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723590211; cv=none; b=g1yZfar/wJ7JFWAi+4LNTxiPj84r60po80A1+W/h3nJgBWaVaj+4Zx5LQpFvB/+l302HDaOEUbqxENSx9VxOHXkFipDdkAoZBBAbx1GLqLL1XxjOXsoxH4mjeNSagufuyYOM0aIcu8lUJns76N96fqQnaHwFnpU8oehf8mHRTwM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723590211; c=relaxed/simple; bh=CT3H5p8o3j+6UENMBxUdmJtEdOKk1cCSzZAzTTQD/Sw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=JRfaGnS3Ds8GqBKoGKsrOl5GIxWOvuGcfFiOzDzAx5J77+3Rb6a/wvOcD+d8c67qBsjiqvFFoZqv+fbxbU5OMAbRTO2gf0KnpEbnAvwVyI1FwRGVcbbxMCFTlqt2aWApI/IBH1Eybfo72z87vTTwMUYkFR5gPcCbN2cl4/0E+v0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=rDJ2QjjJ; arc=none smtp.client-ip=198.47.19.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="rDJ2QjjJ" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 47DN3NuX014081; Tue, 13 Aug 2024 18:03:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1723590203; bh=mlgavM4VLcXnEeYWwNPzCmvF+eUbd1j6VMtMjnxMa3E=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=rDJ2QjjJbUWsMnzpJgis8uz17sFFHOd9qshjQDQ5SNbxpwoikCfLyf4VJGxaMHoK5 5m57pbDMFJTSgxdirtqiO1x8mUv2bD+u4+ChGL+fCTeDZofuBj52d3XPdbGh3JlYFb 7Bi1gYICkrrjzuwjKU9pwa+qvMxTtEF2eBtnOKqg= Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 47DN3NBi033316 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 13 Aug 2024 18:03:23 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 13 Aug 2024 18:03:22 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 13 Aug 2024 18:03:23 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 47DN3Khp026425; Tue, 13 Aug 2024 18:03:23 -0500 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon CC: Vignesh Raghavendra , , , Jan Kiszka , Judith Mendez Subject: [PATCH v2 4/6] arm64: dts: ti: k3-am62: Add comments to ESM nodes Date: Tue, 13 Aug 2024 18:03:10 -0500 Message-ID: <20240813230312.3289428-5-jm@ti.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240813230312.3289428-1-jm@ti.com> References: <20240813230312.3289428-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" Add comments to describe what interrupt sources are routed to ESM modules. There is no functional change. Signed-off-by: Judith Mendez --- Changes since v1: - Add comment to ESM nodes --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am62-main.dtsi index 328929c740dc0..5b92aef5b284b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -241,6 +241,7 @@ main_esm: esm@420000 { bootph-pre-ram; compatible =3D "ti,j721e-esm"; reg =3D <0x00 0x420000 0x00 0x1000>; + /* Interrupt sources: rti0, rti1, rti15, wrti0, rti2, rti3 */ ti,esm-pins =3D <160>, <161>, <162>, <163>, <177>, <178>; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi b/arch/arm64/boot/dts/= ti/k3-am62-mcu.dtsi index e66d486ef1f21..bb43a411f59b2 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi @@ -19,6 +19,7 @@ mcu_esm: esm@4100000 { bootph-pre-ram; compatible =3D "ti,j721e-esm"; reg =3D <0x00 0x4100000 0x00 0x1000>; + /* Interrupt sources: esm0_cfg, esm0_hi, esm0_low, mrti0 */ ti,esm-pins =3D <0>, <1>, <2>, <85>; }; =20 --=20 2.46.0 From nobody Fri Dec 19 16:06:18 2025 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1BCD1AD3EE; Tue, 13 Aug 2024 23:03:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723590211; cv=none; b=ErDyqhfWnxqZquU7jNrrBVyJsInvOit/H5ykwQuIjHlJqOYsMjVUFwUk4UvMFL1pcezEuzTaXQSmwVgjXzDVPNI2k5nXVUboPIzBiDNI52Mj1bAjm86X87mTARKihs4DgUvn37O3n6Us1C54KNZxkxuknuZc1VSTXGp5FGb0YT8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723590211; c=relaxed/simple; bh=apEqxCQKvZC4aqxsMLNsr6VNH3d6tZNmlJxc+Vku1sY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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Tue, 13 Aug 2024 18:03:23 -0500 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon CC: Vignesh Raghavendra , , , Jan Kiszka , Judith Mendez Subject: [PATCH v2 5/6] arm64: dts: ti: k3-am64: Add more ESM interrupt sources Date: Tue, 13 Aug 2024 18:03:11 -0500 Message-ID: <20240813230312.3289428-6-jm@ti.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240813230312.3289428-1-jm@ti.com> References: <20240813230312.3289428-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" Add ESM interrupt sources for rti as per TRM [0] in 9.4 Interrupt Sources. [0] https://www.ti.com/lit/ug/spruim2h/spruim2h.pdf Signed-off-by: Judith Mendez --- Changes since v1: - Add patch 5/6 for am64x --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 3 ++- arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am64-main.dtsi index f8370dd033502..652653bb24f26 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -389,7 +389,8 @@ main_esm: esm@420000 { bootph-pre-ram; compatible =3D "ti,j721e-esm"; reg =3D <0x00 0x420000 0x00 0x1000>; - ti,esm-pins =3D <160>, <161>; + /* Interrupt sources: rti0, rti1, rti8, rti9, rti10, rti11 */ + ti,esm-pins =3D <160>, <161>, <162>, <163>, <164>, <165>; }; =20 main_uart0: serial@2800000 { diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/= ti/k3-am64-mcu.dtsi index ec17285869da6..ad4bed5d3f9eb 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi @@ -158,6 +158,7 @@ mcu_esm: esm@4100000 { bootph-pre-ram; compatible =3D "ti,j721e-esm"; reg =3D <0x00 0x4100000 0x00 0x1000>; - ti,esm-pins =3D <0>, <1>; + /* Interrupt sources: esm0_cfg, esm0_hi, esm0_low, mrti0 */ + ti,esm-pins =3D <0>, <1>, <2>, <85>; }; }; --=20 2.46.0 From nobody Fri Dec 19 16:06:18 2025 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FE251AC43D; Tue, 13 Aug 2024 23:03:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723590212; cv=none; b=kaBSYIt7EBSXvnTb7Vj1j/gAWtThrtYh4x007TgH1fcJbjbUAiyLraoFbsjeUR6UQ0nFRiePt0gGtHH24mrDm0Z5EEseYMqZp4zraggMYa5R1bBmsW1DZdM+0qWw3vhPLc5lIUfA4V7mFS8GwMmmm0S4j3qnqHwa0WxywchxCB8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723590212; c=relaxed/simple; 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Tue, 13 Aug 2024 18:03:24 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 47DN3Khr026425; Tue, 13 Aug 2024 18:03:24 -0500 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon CC: Vignesh Raghavendra , , , Jan Kiszka , Judith Mendez Subject: [PATCH v2 6/6] arm64: dts: ti: k3-am65: Add ESM nodes Date: Tue, 13 Aug 2024 18:03:12 -0500 Message-ID: <20240813230312.3289428-7-jm@ti.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240813230312.3289428-1-jm@ti.com> References: <20240813230312.3289428-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" Add Error Signaling Module (ESM) instances in MCU and MAIN domains, set ESM interrupt sources for rti as per TRM [0] 9.4 Interrupt Sources. Add comments to describe what interrupt sources are routed to ESM modules. [0] https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf Signed-off-by: Judith Mendez --- Changes since v1: - Add patch 6/6 for am65x --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 8 ++++++++ arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am65-main.dtsi index 1af3dedde1f67..07c9f043dac0b 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -54,6 +54,14 @@ gic_its: msi-controller@1820000 { }; }; =20 + main_esm: esm@700000 { + compatible =3D "ti,j721e-esm"; + reg =3D <0x00 0x700000 0x00 0x1000>; + /* Interrupt sources: rti0, rti1, rti2, rti3 */ + ti,esm-pins =3D <224>, <225>, <226>, <227>; + bootph-pre-ram; + }; + serdes0: serdes@900000 { compatible =3D "ti,phy-am654-serdes"; reg =3D <0x0 0x900000 0x0 0x2000>; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/= ti/k3-am65-mcu.dtsi index 43c6118d2bf0f..e10cb9f483698 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -440,6 +440,14 @@ mcu_r5fss0_core1: r5f@41400000 { }; }; =20 + mcu_esm: esm@40800000 { + compatible =3D "ti,j721e-esm"; + reg =3D <0x00 0x40800000 0x00 0x1000>; + /* Interrupt sources: mrti0, mrti1 */ + ti,esm-pins =3D <104>, <105>; + bootph-pre-ram; + }; + mcu_rti1: watchdog@40610000 { compatible =3D "ti,j7-rti-wdt"; reg =3D <0x0 0x40610000 0x0 0x100>; --=20 2.46.0