From nobody Tue Feb 10 14:33:40 2026 Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5546719306B; Tue, 13 Aug 2024 14:02:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.190 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723557764; cv=none; b=rhSM1ELXzclMLsUU9X3Bgjyj8riy4f/3SycGAUlpa7sjsK9GJqeNidU8wQJp7bir46sRFDV8OKn18Ell6Mrj2efxdCW1U4eVpo0ikzagILiZxxrr2vef3tPfaye/rzdgCZs1PBMNEK50rD3BUIVK0qx5UyY2rUbtvmMbI3w7cZo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723557764; c=relaxed/simple; bh=c0w6xi2XFLIWh+oe9OllzcOGbsi88/66YS+StIWRMg4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Bufxvo/swGzJFJaHAxTbPm8xvSpBwl/TC2tmKAlmbSOP4e/bd/TBGWtrDcgkGFSck8zHskg/SDS63AjThlp6UHbZr/315rMAgozAJGvFPlaXL0PwB2WAmWCbeIS155qg5/3QJVW/keHOwJEdBBGgonQqK0FaMYrbAYsrIgUKgEA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.190 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.44]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4WjtHt0jm0z2CmGw; Tue, 13 Aug 2024 21:57:46 +0800 (CST) Received: from kwepemm000007.china.huawei.com (unknown [7.193.23.189]) by mail.maildlp.com (Postfix) with ESMTPS id F1B1D140361; Tue, 13 Aug 2024 22:02:36 +0800 (CST) Received: from localhost.localdomain (10.90.30.45) by kwepemm000007.china.huawei.com (7.193.23.189) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 13 Aug 2024 22:02:36 +0800 From: Jijie Shao To: , , , , , , CC: , , , , , , , , , , , , Subject: [RFC PATCH V2 net-next 02/11] net: hibmcge: Add read/write registers supported through the bar space Date: Tue, 13 Aug 2024 21:56:31 +0800 Message-ID: <20240813135640.1694993-3-shaojijie@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20240813135640.1694993-1-shaojijie@huawei.com> References: <20240813135640.1694993-1-shaojijie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To kwepemm000007.china.huawei.com (7.193.23.189) Content-Type: text/plain; charset="utf-8" Add support for to read and write registers through the pic bar space. Some driver parameters, such as mac_id, are determined by the board form. Therefore, these parameters are initialized from the register as device specifications. the device specifications register are initialized and writed by bmc. driver will read these registers when loading. Signed-off-by: Jijie Shao --- .../ethernet/hisilicon/hibmcge/hbg_common.h | 28 ++++++++ .../net/ethernet/hisilicon/hibmcge/hbg_hw.c | 70 +++++++++++++++++++ .../net/ethernet/hisilicon/hibmcge/hbg_hw.h | 32 +++++++++ .../net/ethernet/hisilicon/hibmcge/hbg_main.c | 32 +++++++++ .../net/ethernet/hisilicon/hibmcge/hbg_reg.h | 20 ++++++ 5 files changed, 182 insertions(+) create mode 100644 drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c create mode 100644 drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h create mode 100644 drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_common.h b/drivers/= net/ethernet/hisilicon/hibmcge/hbg_common.h index 614650e9a71f..d1f05484f246 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_common.h +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_common.h @@ -7,10 +7,38 @@ #include #include =20 +enum hbg_nic_state { + HBG_NIC_STATE_INITED =3D 0, + HBG_NIC_STATE_EVENT_HANDLING, +}; + +enum hbg_hw_event_type { + HBG_HW_EVENT_NONE =3D 0, + HBG_HW_EVENT_INIT, /* driver is loading */ +}; + +struct hbg_dev_specs { + u32 mac_id; + struct sockaddr mac_addr; + u32 phy_addr; + u32 mdio_frequency; + u32 rx_fifo_num; + u32 tx_fifo_num; + u32 vlan_layers; + u32 max_mtu; + u32 min_mtu; + + u32 max_frame_len; + u32 rx_buf_size; +}; + struct hbg_priv { struct net_device *netdev; struct pci_dev *pdev; u8 __iomem *io_base; + struct regmap *regmap; + struct hbg_dev_specs dev_specs; + unsigned long state; }; =20 #endif diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c b/drivers/net/= ethernet/hisilicon/hibmcge/hbg_hw.c new file mode 100644 index 000000000000..978f680ad089 --- /dev/null +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2024 Hisilicon Limited. + +#include +#include +#include +#include +#include "hbg_common.h" +#include "hbg_hw.h" +#include "hbg_reg.h" + +static bool hbg_hw_spec_is_valid(struct hbg_priv *priv) +{ + return hbg_reg_read(priv, HBG_REG_SPEC_VALID_ADDR) && + !hbg_reg_read(priv, HBG_REG_EVENT_REQ_ADDR); +} + +int hbg_hw_event_notify(struct hbg_priv *priv, enum hbg_hw_event_type even= t_type) +{ +#define HBG_HW_EVENT_WAIT_TIMEOUT_US (2 * 1000 * 1000) +#define HBG_HW_EVENT_WAIT_INTERVAL_US (10 * 1000) + + bool is_valid; + int ret; + + if (test_and_set_bit(HBG_NIC_STATE_EVENT_HANDLING, &priv->state)) + return -EBUSY; + + /* notify */ + hbg_reg_write(priv, HBG_REG_EVENT_REQ_ADDR, event_type); + + ret =3D read_poll_timeout(hbg_hw_spec_is_valid, is_valid, is_valid, + HBG_HW_EVENT_WAIT_INTERVAL_US, + HBG_HW_EVENT_WAIT_TIMEOUT_US, + HBG_HW_EVENT_WAIT_INTERVAL_US, priv); + + clear_bit(HBG_NIC_STATE_EVENT_HANDLING, &priv->state); + + if (ret) + dev_err(&priv->pdev->dev, "event %d wait timeout\n", event_type); + + return ret; +} + +int hbg_hw_dev_specs_init(struct hbg_priv *priv) +{ + struct hbg_dev_specs *dev_specs =3D &priv->dev_specs; + u64 mac_addr; + + if (!hbg_hw_spec_is_valid(priv)) { + dev_err(&priv->pdev->dev, "dev_specs not init\n"); + return -EINVAL; + } + + dev_specs->mac_id =3D hbg_reg_read(priv, HBG_REG_MAC_ID_ADDR); + dev_specs->phy_addr =3D hbg_reg_read(priv, HBG_REG_PHY_ID_ADDR); + dev_specs->mdio_frequency =3D hbg_reg_read(priv, HBG_REG_MDIO_FREQ_ADDR); + dev_specs->max_mtu =3D hbg_reg_read(priv, HBG_REG_MAX_MTU_ADDR); + dev_specs->min_mtu =3D hbg_reg_read(priv, HBG_REG_MIN_MTU_ADDR); + dev_specs->vlan_layers =3D hbg_reg_read(priv, HBG_REG_VLAN_LAYERS_ADDR); + dev_specs->rx_fifo_num =3D hbg_reg_read(priv, HBG_REG_RX_FIFO_NUM_ADDR); + dev_specs->tx_fifo_num =3D hbg_reg_read(priv, HBG_REG_TX_FIFO_NUM_ADDR); + mac_addr =3D hbg_reg_read64(priv, HBG_REG_MAC_ADDR_ADDR); + u64_to_ether_addr(mac_addr, (u8 *)dev_specs->mac_addr.sa_data); + + if (!is_valid_ether_addr((u8 *)dev_specs->mac_addr.sa_data)) + return -EADDRNOTAVAIL; + + return 0; +} diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h b/drivers/net/= ethernet/hisilicon/hibmcge/hbg_hw.h new file mode 100644 index 000000000000..e977132915e1 --- /dev/null +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright (c) 2024 Hisilicon Limited. */ + +#ifndef __HBG_HW_H +#define __HBG_HW_H + +#include +#include + +#define hbg_reg_read(priv, reg_addr) ({ \ + u32 _value =3D U32_MAX; \ + (void)regmap_read((priv)->regmap, reg_addr, &_value); \ + _value; }) + +#define hbg_reg_write(priv, reg_addr, value) \ + regmap_write((priv)->regmap, reg_addr, value) + +#define hbg_reg_read64(priv, reg_addr) lo_hi_readq((priv)->io_base + (reg_= addr)) + +#define hbg_reg_write64(priv, reg_addr, value) \ + lo_hi_writeq(value, (priv)->io_base + (reg_addr)) + +#define hbg_reg_read_field(priv, reg_addr, mask) \ + FIELD_GET(mask, hbg_reg_read(priv, reg_addr)) + +#define hbg_reg_write_field(priv, reg_addr, mask, val) \ + regmap_write_bits((priv)->regmap, reg_addr, mask, FIELD_PREP(mask, val)) + +int hbg_hw_event_notify(struct hbg_priv *priv, enum hbg_hw_event_type even= t_type); +int hbg_hw_dev_specs_init(struct hbg_priv *priv); + +#endif diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c b/drivers/ne= t/ethernet/hisilicon/hibmcge/hbg_main.c index 9195c7fb13e3..5ab3f1df3d21 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c @@ -5,6 +5,33 @@ #include #include #include "hbg_common.h" +#include "hbg_hw.h" + +static const struct regmap_config hbg_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x20000, + .fast_io =3D true, +}; + +static int hbg_init(struct hbg_priv *priv) +{ + struct device *dev =3D &priv->pdev->dev; + struct regmap *regmap; + int ret; + + regmap =3D devm_regmap_init_mmio(dev, priv->io_base, &hbg_regmap_config); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), "failed to init regmap\n"); + + priv->regmap =3D regmap; + ret =3D hbg_hw_event_notify(priv, HBG_HW_EVENT_INIT); + if (ret) + return ret; + + return hbg_hw_dev_specs_init(priv); +} =20 static int hbg_pci_init(struct pci_dev *pdev) { @@ -56,10 +83,15 @@ static int hbg_probe(struct pci_dev *pdev, const struct= pci_device_id *ent) if (ret) return ret; =20 + ret =3D hbg_init(priv); + if (ret) + return ret; + ret =3D devm_register_netdev(dev, netdev); if (ret) return dev_err_probe(dev, ret, "failed to register netdev\n"); =20 + set_bit(HBG_NIC_STATE_INITED, &priv->state); return 0; } =20 diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h b/drivers/net= /ethernet/hisilicon/hibmcge/hbg_reg.h new file mode 100644 index 000000000000..77153f1132fd --- /dev/null +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright (c) 2024 Hisilicon Limited. */ + +#ifndef __HBG_REG_H +#define __HBG_REG_H + +/* DEV SPEC */ +#define HBG_REG_SPEC_VALID_ADDR 0x0000 +#define HBG_REG_EVENT_REQ_ADDR 0x0004 +#define HBG_REG_MAC_ID_ADDR 0x0008 +#define HBG_REG_PHY_ID_ADDR 0x000C +#define HBG_REG_MAC_ADDR_ADDR 0x0010 +#define HBG_REG_MDIO_FREQ_ADDR 0x0024 +#define HBG_REG_MAX_MTU_ADDR 0x0028 +#define HBG_REG_MIN_MTU_ADDR 0x002C +#define HBG_REG_TX_FIFO_NUM_ADDR 0x0030 +#define HBG_REG_RX_FIFO_NUM_ADDR 0x0034 +#define HBG_REG_VLAN_LAYERS_ADDR 0x0038 + +#endif --=20 2.33.0