From nobody Sun Feb 8 05:28:38 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 467C812D214; Tue, 13 Aug 2024 07:43:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723535027; cv=none; b=r0M0SBUn2t4aAEki7r/67zCm7DIHKKiLLhZ68NQ0MHCxOh7LoCmEnMOgHk4KFRws5wQ1kTGczDeVnZZk8RLgxGuSwXMoJOHPNNrx6CwSsK6X1fu0gLww6MSD4LGEC6ofSava5A94DAvOVCnSU99+l7/y+SgwKed6NBQ9VYeEJ6s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723535027; c=relaxed/simple; bh=CVBx+W6TLdjMUGMg9fR/4/zxYtvSPg0a973K0nBxzXg=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bJSI139M/UV1C2WGG7mv/N5ffONeS3YRQgy2/sn6RBuQcCxoCQiA5ETAG5jI5Z5RAQn28c9nzTEtYPHfFslljBdnnyGtT5jtc70wRYwVR+7SIfOTvD7KDex7DT+bD9MTqz6gmZMqlVhfi5UgIxFjZIutyKnN6R69n0DZrHt9luo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Tue, 13 Aug 2024 15:43:40 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Tue, 13 Aug 2024 15:43:40 +0800 From: Kevin Chen To: , , , , , , , , , , Subject: [PATCH v1 1/2] dt-bindings: interrupt-controller: Add support for ASPEED AST27XX INTC Date: Tue, 13 Aug 2024 15:43:37 +0800 Message-ID: <20240813074338.969883-2-kevin_chen@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240813074338.969883-1-kevin_chen@aspeedtech.com> References: <20240813074338.969883-1-kevin_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The ASPEED AST27XX interrupt controller(INTC) combines 32 interrupt sources into 1 interrupt into GIC from CPU die to CPU die. The INTC design contains soc0_intc and soc1_intc module doing hand shake between CPU die and IO die INTC. In soc0_intc11, each bit represent 1 GIC_SPI interrupt from soc1_intcX. In soc1_intcX, each bit represent 1 device interrupt in IO die. By soc1_intcX in IO die, AST27XX INTC combines 32 interrupt sources to 1 interrupt source in soc0_intc11 in CPU die, which achieve the interrupt passing between the different die in AST27XX. --- .../aspeed,ast2700-intc.yaml | 120 ++++++++++++++++++ 1 file changed, 120 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= aspeed,ast2700-intc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,= ast2700-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/= aspeed,ast2700-intc.yaml new file mode 100644 index 000000000000..93d7141bf9f9 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700= -intc.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-int= c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed Interrupt Controller driver + +description: + These bindings are for the Aspeed interrupt controller. The AST2700 + SoC families include a legacy register layout before a re-designed + layout, but the bindings do not prescribe the use of one or the other. + +maintainers: + - Kevin Chen + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - aspeed,ast2700-intc-ic + - aspeed,ast2700-intc-icv2 + description: | + Use "aspeed,ast2700-intc-ic" for soc1 INTC in IO die + Use "aspeed,ast2700-intc-icv2" for soc0 INTC in CPU die + + interrupt-controller: true + + interrupts-extended: + minItems: 1 + maxItems: 3 + description: + Specifies which contexts are connected to the INTC, with "-1" specif= ying + that a context is not present. Each node pointed to should be a + aspeed,ast2700-intc-ic or aspeed,ast2700-intc-icv2 nodes which are p= ointed + to gic node. + + "#address-cells": + const: 2 + "#size-cells": + const: 2 + + '#interrupt-cells': + const: 2 + description: | + The first cell cell is the interrupt source IRQ number, and the seco= nd cell + is the trigger type as defined in interrupt.txt in this directory. + + reg: + minItems: 1 + maxItems: 2 + description: | + The first cell cell is the interrupt enable register, and the second= cell + is the status register. + + ranges: true + + interrupts: + minItems: 1 + maxItems: 10 + description: | + Interrupt source of the CPU interrupts. In soc0_intc in CPU die INTC= each bit + represent soc1_intc interrupt source. soc0_intc take care 10 interru= pt source + from soc1_intc0~5 and ltpi0/1_soc1_intc0/1. + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +example: + - | + soc0_intc: interrupt-controller@12100000 { + compatible =3D "simple-mfd"; + reg =3D <0 0x12100000 0 0x4000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x0 0x0 0x0 0x12100000 0x0 0x4000>; + + soc0_intc11: interrupt-controller@1b00 { + compatible =3D "aspeed,ast2700-intc-icv2"; + interrupts =3D , + , + , + , + , + , + , + , + , + ; + #interrupt-cells =3D <2>; + interrupt-controller; + reg =3D <0x0 0x1b00 0x0 0x10>; + }; + }; + + - | + soc1_intc: interrupt-controller@14c18000 { + compatible =3D "simple-mfd"; + reg =3D <0 0x14c18000 0 0x400>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x0 0x0 0x0 0x14c18000 0x0 0x400>; + + soc1_intc0: interrupt-controller@100 { + compatible =3D "aspeed,ast2700-intc-ic"; + interrupts-extended =3D <&soc0_intc11 0 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells =3D <2>; + interrupt-controller; + reg =3D <0x0 0x100 0x0 0x10>; + }; + }; --=20 2.34.1 From nobody Sun Feb 8 05:28:38 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E33DB13A27E; Tue, 13 Aug 2024 07:43:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723535029; cv=none; b=tiymMx57WwTPXHQE1+OptT/APr9tW1Copv7XCq5dhLrIfZKTErZWNukaIs6uuWpQL+xSc0cAoUx3QOEAnUGuuFpqGNOUBc9Y+41CrCkmIg6cWbOaAJEpcgitatxbh2X5dAdsRCSBSEKU3dZgbDg+JYFBRSVXz2J95Kryf/iePls= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723535029; c=relaxed/simple; bh=OzNbWjZdzW9zPbcoqy44lUoYPblw6enzk/wdA/yLURo=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bbHw5TxD+d32utrBAFY3vFOWpm1qKzffICcT4/2IYDB/JzIEMoS43YTZEV2HKvyAeqdbt0XTHRUKQXcsrb9aRiKOSJccwakp7M91k2w4bJ6dzmnWZ9Vmuj6w1GtEpzwhHJYUBmmew435IHy5oqVEecoJBBcb3a9q9ug9ynT05EQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Tue, 13 Aug 2024 15:43:40 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Tue, 13 Aug 2024 15:43:40 +0800 From: Kevin Chen To: , , , , , , , , , , Subject: [PATCH v1 2/2] irqchip/aspeed-intc: Add support for 10 INTC interrupts on AST27XX platforms Date: Tue, 13 Aug 2024 15:43:38 +0800 Message-ID: <20240813074338.969883-3-kevin_chen@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240813074338.969883-1-kevin_chen@aspeedtech.com> References: <20240813074338.969883-1-kevin_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There are 10 interrupt source of soc0_intc in CPU die INTC. 1. 6 interrupt sources in IO die of soc1_intc0~soc1_intc5. 2. 2 interrupt sources in LTPI of ltpi0_intc0 and ltpi0_intc1. 3. 2 interrupt sources in LTPI of ltpi1_intc0 and ltpi1_intc1. Request GIC interrupt to check each bit in status register to do next level INTC handler. In next level INTC handler of IO die or LTPI INTC using soc1_intcX combining 32 interrupt sources into soc0_intc11 in CPU die. In soc1_intcX, handler would check 32 bit of status register to do the requested device handler. --- drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-aspeed-intc.c | 198 ++++++++++++++++++++++++++++++ 2 files changed, 199 insertions(+) create mode 100644 drivers/irqchip/irq-aspeed-intc.c diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 15635812b2d6..d2fe686ae018 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -84,6 +84,7 @@ obj-$(CONFIG_MVEBU_SEI) +=3D irq-mvebu-sei.o obj-$(CONFIG_LS_EXTIRQ) +=3D irq-ls-extirq.o obj-$(CONFIG_LS_SCFG_MSI) +=3D irq-ls-scfg-msi.o obj-$(CONFIG_ARCH_ASPEED) +=3D irq-aspeed-vic.o irq-aspeed-i2c-ic.o irq-a= speed-scu-ic.o +obj-$(CONFIG_MACH_ASPEED_G7) +=3D irq-aspeed-intc.o obj-$(CONFIG_STM32MP_EXTI) +=3D irq-stm32mp-exti.o obj-$(CONFIG_STM32_EXTI) +=3D irq-stm32-exti.o obj-$(CONFIG_QCOM_IRQ_COMBINER) +=3D qcom-irq-combiner.o diff --git a/drivers/irqchip/irq-aspeed-intc.c b/drivers/irqchip/irq-aspeed= -intc.c new file mode 100644 index 000000000000..71407475fb27 --- /dev/null +++ b/drivers/irqchip/irq-aspeed-intc.c @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Aspeed Interrupt Controller. + * + * Copyright (C) 2023 ASPEED Technology Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define INTC_INT_ENABLE_REG 0x00 +#define INTC_INT_STATUS_REG 0x04 + +struct aspeed_intc_ic { + void __iomem *base; + raw_spinlock_t gic_lock; + raw_spinlock_t intc_lock; + struct irq_domain *irq_domain; +}; + +static void aspeed_intc_ic_irq_handler(struct irq_desc *desc) +{ + struct aspeed_intc_ic *intc_ic =3D irq_desc_get_handler_data(desc); + struct irq_chip *chip =3D irq_desc_get_chip(desc); + unsigned long bit, status, flags; + + chained_irq_enter(chip, desc); + + raw_spin_lock_irqsave(&intc_ic->gic_lock, flags); + status =3D readl(intc_ic->base + INTC_INT_STATUS_REG); + for_each_set_bit(bit, &status, 32) { + generic_handle_domain_irq(intc_ic->irq_domain, bit); + writel(BIT(bit), intc_ic->base + INTC_INT_STATUS_REG); + } + raw_spin_unlock_irqrestore(&intc_ic->gic_lock, flags); + + chained_irq_exit(chip, desc); +} + +static void aspeed_intc_irq_mask(struct irq_data *data) +{ + struct aspeed_intc_ic *intc_ic =3D irq_data_get_irq_chip_data(data); + unsigned int mask =3D readl(intc_ic->base + INTC_INT_ENABLE_REG) & ~BIT(d= ata->hwirq); + unsigned long flags; + + raw_spin_lock_irqsave(&intc_ic->intc_lock, flags); + writel(mask, intc_ic->base + INTC_INT_ENABLE_REG); + raw_spin_unlock_irqrestore(&intc_ic->intc_lock, flags); +} + +static void aspeed_intc_irq_unmask(struct irq_data *data) +{ + struct aspeed_intc_ic *intc_ic =3D irq_data_get_irq_chip_data(data); + unsigned int unmask =3D readl(intc_ic->base + INTC_INT_ENABLE_REG) | BIT(= data->hwirq); + unsigned long flags; + + raw_spin_lock_irqsave(&intc_ic->intc_lock, flags); + writel(unmask, intc_ic->base + INTC_INT_ENABLE_REG); + raw_spin_unlock_irqrestore(&intc_ic->intc_lock, flags); +} + +static int aspeed_intc_irq_set_affinity(struct irq_data *data, const struc= t cpumask *dest, + bool force) +{ + return -EINVAL; +} + +static struct irq_chip aspeed_intc_chip =3D { + .name =3D "ASPEED INTC", + .irq_mask =3D aspeed_intc_irq_mask, + .irq_unmask =3D aspeed_intc_irq_unmask, + .irq_set_affinity =3D aspeed_intc_irq_set_affinity, +}; + +static int aspeed_intc_ic_map_irq_domain(struct irq_domain *domain, unsign= ed int irq, + irq_hw_number_t hwirq) +{ + irq_set_chip_and_handler(irq, &aspeed_intc_chip, handle_level_irq); + irq_set_chip_data(irq, domain->host_data); + + return 0; +} + +static const struct irq_domain_ops aspeed_intc_ic_irq_domain_ops =3D { + .map =3D aspeed_intc_ic_map_irq_domain, +}; + +static int __init aspeed_intc_ic_of_init(struct device_node *node, struct = device_node *parent) +{ + struct aspeed_intc_ic *intc_ic; + int ret =3D 0; + int irq; + + intc_ic =3D kzalloc(sizeof(*intc_ic), GFP_KERNEL); + if (!intc_ic) + return -ENOMEM; + + intc_ic->base =3D of_iomap(node, 0); + if (!intc_ic->base) { + pr_err("Failed to iomap intc_ic base\n"); + ret =3D -ENOMEM; + goto err_free_ic; + } + writel(0xffffffff, intc_ic->base + INTC_INT_STATUS_REG); + writel(0x0, intc_ic->base + INTC_INT_ENABLE_REG); + + irq =3D irq_of_parse_and_map(node, 0); + if (!irq) { + pr_err("Failed to get irq number\n"); + ret =3D -EINVAL; + goto err_iounmap; + } + + intc_ic->irq_domain =3D irq_domain_add_linear(node, 32, + &aspeed_intc_ic_irq_domain_ops, intc_ic); + if (!intc_ic->irq_domain) { + ret =3D -ENOMEM; + goto err_iounmap; + } + + raw_spin_lock_init(&intc_ic->gic_lock); + raw_spin_lock_init(&intc_ic->intc_lock); + + intc_ic->irq_domain->name =3D "aspeed-intc-domain"; + + irq_set_chained_handler_and_data(irq, + aspeed_intc_ic_irq_handler, intc_ic); + + return 0; + +err_iounmap: + iounmap(intc_ic->base); +err_free_ic: + kfree(intc_ic); + return ret; +} + +static int __init aspeed_intc_ic_of_init_v2(struct device_node *node, + struct device_node *parent) +{ + struct aspeed_intc_ic *intc_ic; + int ret =3D 0; + int irq, i; + + intc_ic =3D kzalloc(sizeof(*intc_ic), GFP_KERNEL); + if (!intc_ic) + return -ENOMEM; + + intc_ic->base =3D of_iomap(node, 0); + if (!intc_ic->base) { + pr_err("Failed to iomap intc_ic base\n"); + ret =3D -ENOMEM; + goto err_free_ic; + } + writel(0xffffffff, intc_ic->base + INTC_INT_STATUS_REG); + writel(0x0, intc_ic->base + INTC_INT_ENABLE_REG); + + intc_ic->irq_domain =3D irq_domain_add_linear(node, 32, + &aspeed_intc_ic_irq_domain_ops, intc_ic); + if (!intc_ic->irq_domain) { + ret =3D -ENOMEM; + goto err_iounmap; + } + + raw_spin_lock_init(&intc_ic->gic_lock); + raw_spin_lock_init(&intc_ic->intc_lock); + + intc_ic->irq_domain->name =3D "aspeed-intc-domain"; + + for (i =3D 0; i < of_irq_count(node); i++) { + irq =3D irq_of_parse_and_map(node, i); + if (!irq) { + pr_err("Failed to get irq number\n"); + ret =3D -EINVAL; + goto err_iounmap; + } else { + irq_set_chained_handler_and_data(irq, aspeed_intc_ic_irq_handler, intc_= ic); + } + } + + return 0; + +err_iounmap: + iounmap(intc_ic->base); +err_free_ic: + kfree(intc_ic); + return ret; +} + +IRQCHIP_DECLARE(ast2700_intc_ic, "aspeed,ast2700-intc-1.0", aspeed_intc_ic= _of_init); +IRQCHIP_DECLARE(ast2700_intc_icv2, "aspeed,ast2700-intc-2.0", aspeed_intc_= ic_of_init_v2); --=20 2.34.1