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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4290c738e01sm152901205e9.11.2024.08.11.08.02.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Aug 2024 08:02:31 -0700 (PDT) From: Alexandre Ghiti To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Andy Chiu , Alexandre Ghiti , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH -fixes] riscv: Fix out-of-bounds when accessing Andes per hart vendor extension array Date: Sun, 11 Aug 2024 17:02:29 +0200 Message-Id: <20240811150229.82321-1-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The out-of-bounds access is reported by UBSAN: [ 0.000000] UBSAN: array-index-out-of-bounds in ../arch/riscv/kernel/ven= dor_extensions.c:41:66 [ 0.000000] index -1 is out of range for type 'riscv_isavendorinfo [32]' [ 0.000000] CPU: 0 UID: 0 PID: 0 Comm: swapper Not tainted 6.11.0-rc2ubu= ntu-defconfig #2 [ 0.000000] Hardware name: riscv-virtio,qemu (DT) [ 0.000000] Call Trace: [ 0.000000] [] dump_backtrace+0x32/0x40 [ 0.000000] [] show_stack+0x38/0x44 [ 0.000000] [] dump_stack_lvl+0x70/0x9c [ 0.000000] [] dump_stack+0x18/0x20 [ 0.000000] [] ubsan_epilogue+0x10/0x46 [ 0.000000] [] __ubsan_handle_out_of_bounds+0x94/0x9c [ 0.000000] [] __riscv_isa_vendor_extension_available+= 0x90/0x92 [ 0.000000] [] riscv_cpufeature_patch_func+0xc4/0x148 [ 0.000000] [] _apply_alternatives+0x42/0x50 [ 0.000000] [] apply_boot_alternatives+0x3c/0x100 [ 0.000000] [] setup_arch+0x85a/0x8bc [ 0.000000] [] start_kernel+0xa4/0xfb6 This happens because we unconditionally use the cpu parameter to access this array. But if -1 is passed, that means we should not and we don't need to access this array, so simply prevent accessing the array in that ca= se. Fixes: 23c996fc2bc1 ("riscv: Extend cpufeature.c to detect vendor extension= s") Signed-off-by: Alexandre Ghiti Tested-by: Conor Dooley --- arch/riscv/kernel/vendor_extensions.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kernel/vendor_extensions.c b/arch/riscv/kernel/vend= or_extensions.c index b6c1e7b5d34b..01dc79b1d17b 100644 --- a/arch/riscv/kernel/vendor_extensions.c +++ b/arch/riscv/kernel/vendor_extensions.c @@ -27,7 +27,7 @@ const size_t riscv_isa_vendor_ext_list_size =3D ARRAY_SIZ= E(riscv_isa_vendor_ext_li * @bit: bit position of the desired extension * Return: true or false * - * NOTE: When cpu is -1, will check if extension is available on all cpus + * NOTE: When cpu is VENDOR_EXT_ALL_CPUS, will check if extension is avail= able on all cpus */ bool __riscv_isa_vendor_extension_available(int cpu, unsigned long vendor,= unsigned int bit) { @@ -38,14 +38,15 @@ bool __riscv_isa_vendor_extension_available(int cpu, un= signed long vendor, unsig #ifdef CONFIG_RISCV_ISA_VENDOR_EXT_ANDES case ANDES_VENDOR_ID: bmap =3D &riscv_isa_vendor_ext_list_andes.all_harts_isa_bitmap; - cpu_bmap =3D &riscv_isa_vendor_ext_list_andes.per_hart_isa_bitmap[cpu]; + if (cpu !=3D VENDOR_EXT_ALL_CPUS) + cpu_bmap =3D &riscv_isa_vendor_ext_list_andes.per_hart_isa_bitmap[cpu]; break; #endif default: return false; } =20 - if (cpu !=3D -1) + if (cpu !=3D VENDOR_EXT_ALL_CPUS) bmap =3D &cpu_bmap[cpu]; =20 if (bit >=3D RISCV_ISA_VENDOR_EXT_MAX) --=20 2.39.2