From nobody Wed Dec 17 20:55:54 2025 Received: from out-182.mta1.migadu.com (out-182.mta1.migadu.com [95.215.58.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9907316A94F for ; Fri, 9 Aug 2024 19:36:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723232195; cv=none; b=Tp0pyHlQCnR1r3FV/96ShF2RcbYmqADqW9JuvMJDXQnGzuwFISpu1KuGHWjizRb9uwGfOZ3lmHU2cJ+XVNRNXgUXylRImx0FjUmjYnxBbBSPc+j/sher4lrI7zHHvXIFo3bzLTyrfhbhCTtKTJ91Opmh6+0Fir0nP/GOlQk1ngU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723232195; c=relaxed/simple; bh=NmfBPCQOUiqvuYgDchKyG5guDaffzHEJRaAjXJm9klE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=A3+AURBXy7nwLXgfHKJB5m+4oQSrD6r1O9mzMOehAaZX29L6EARiXa9JoEZXnTpJfeD/jMDvPlzPioWGQMSzhdRPQddtDxLQG3Lsw62OWbP2LDExq19GqQcTZLrJRRqyM2G5AUbqWkYsrTCMGaktpRYlN+jVjFzLeGSdJsF5yjk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=f3kf7JZJ; arc=none smtp.client-ip=95.215.58.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="f3kf7JZJ" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1723232191; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=quWhlQYCIJ5ooa/bXKzdLXD7dpTxps6C7G+W1eMFLO4=; b=f3kf7JZJNh6Fj4JJy6FTYFDxCEI0GxTlAZ/XgHhmyY469GU9Fa9Kxc2vKWS9LzrO9L8cVO Gyhyk6A9CygsqE87pZiFGtuyEByOh6FlToyB90i9ztVFOofgV376THJ5qiOUN79NhAEaYV VDzJCItHhhndgHAbOEsZQPL2z1W8dsw= From: Sean Anderson To: Laurent Pinchart , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , dri-devel@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, David Airlie , Michal Simek , Daniel Vetter , Tomi Valkeinen , Sean Anderson Subject: [PATCH v6 6/8] drm: zynqmp_dp: Split off several helper functions Date: Fri, 9 Aug 2024 15:35:58 -0400 Message-Id: <20240809193600.3360015-7-sean.anderson@linux.dev> In-Reply-To: <20240809193600.3360015-1-sean.anderson@linux.dev> References: <20240809193600.3360015-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" In preparation for supporting compliance testing, split off several helper functions. No functional change intended. Signed-off-by: Sean Anderson Reviewed-by: Laurent Pinchart Reviewed-by: Tomi Valkeinen --- (no changes since v1) drivers/gpu/drm/xlnx/zynqmp_dp.c | 49 ++++++++++++++++++++++---------- 1 file changed, 34 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp= _dp.c index babfa3581014..e0ab3b3e8580 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c @@ -636,6 +636,7 @@ static void zynqmp_dp_adjust_train(struct zynqmp_dp *dp, /** * zynqmp_dp_update_vs_emph - Update the training values * @dp: DisplayPort IP core structure + * @train_set: A set of training values * * Update the training values based on the request from sink. The mapped v= alues * are predefined, and values(vs, pe, pc) are from the device manual. @@ -643,12 +644,12 @@ static void zynqmp_dp_adjust_train(struct zynqmp_dp *= dp, * Return: 0 if vs and emph are updated successfully, or the error code re= turned * by drm_dp_dpcd_write(). */ -static int zynqmp_dp_update_vs_emph(struct zynqmp_dp *dp) +static int zynqmp_dp_update_vs_emph(struct zynqmp_dp *dp, u8 *train_set) { unsigned int i; int ret; =20 - ret =3D drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, dp->train_set, + ret =3D drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, train_set, dp->mode.lane_cnt); if (ret < 0) return ret; @@ -656,7 +657,7 @@ static int zynqmp_dp_update_vs_emph(struct zynqmp_dp *d= p) for (i =3D 0; i < dp->mode.lane_cnt; i++) { u32 reg =3D ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_0 + i * 4; union phy_configure_opts opts =3D { 0 }; - u8 train =3D dp->train_set[i]; + u8 train =3D train_set[i]; =20 opts.dp.voltage[0] =3D (train & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT; @@ -700,7 +701,7 @@ static int zynqmp_dp_link_train_cr(struct zynqmp_dp *dp) * So, This loop should exit before 512 iterations */ for (max_tries =3D 0; max_tries < 512; max_tries++) { - ret =3D zynqmp_dp_update_vs_emph(dp); + ret =3D zynqmp_dp_update_vs_emph(dp, dp->train_set); if (ret) return ret; =20 @@ -765,7 +766,7 @@ static int zynqmp_dp_link_train_ce(struct zynqmp_dp *dp) return ret; =20 for (tries =3D 0; tries < DP_MAX_TRAINING_TRIES; tries++) { - ret =3D zynqmp_dp_update_vs_emph(dp); + ret =3D zynqmp_dp_update_vs_emph(dp, dp->train_set); if (ret) return ret; =20 @@ -788,28 +789,29 @@ static int zynqmp_dp_link_train_ce(struct zynqmp_dp *= dp) } =20 /** - * zynqmp_dp_train - Train the link + * zynqmp_dp_setup() - Set up major link parameters * @dp: DisplayPort IP core structure + * @bw_code: The link bandwidth as a multiple of 270 MHz + * @lane_cnt: The number of lanes to use + * @enhanced: Use enhanced framing + * @downspread: Enable spread-spectrum clocking * - * Return: 0 if all trains are done successfully, or corresponding error c= ode. + * Return: 0 on success, or -errno on failure */ -static int zynqmp_dp_train(struct zynqmp_dp *dp) +static int zynqmp_dp_setup(struct zynqmp_dp *dp, u8 bw_code, u8 lane_cnt, + bool enhanced, bool downspread) { u32 reg; - u8 bw_code =3D dp->mode.bw_code; - u8 lane_cnt =3D dp->mode.lane_cnt; u8 aux_lane_cnt =3D lane_cnt; - bool enhanced; int ret; =20 zynqmp_dp_write(dp, ZYNQMP_DP_LANE_COUNT_SET, lane_cnt); - enhanced =3D drm_dp_enhanced_frame_cap(dp->dpcd); if (enhanced) { zynqmp_dp_write(dp, ZYNQMP_DP_ENHANCED_FRAME_EN, 1); aux_lane_cnt |=3D DP_LANE_COUNT_ENHANCED_FRAME_EN; } =20 - if (dp->dpcd[3] & 0x1) { + if (downspread) { zynqmp_dp_write(dp, ZYNQMP_DP_DOWNSPREAD_CTL, 1); drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); @@ -852,8 +854,25 @@ static int zynqmp_dp_train(struct zynqmp_dp *dp) } =20 zynqmp_dp_write(dp, ZYNQMP_DP_PHY_CLOCK_SELECT, reg); - ret =3D zynqmp_dp_phy_ready(dp); - if (ret < 0) + return zynqmp_dp_phy_ready(dp); +} + + +/** + * zynqmp_dp_train - Train the link + * @dp: DisplayPort IP core structure + * + * Return: 0 if all trains are done successfully, or corresponding error c= ode. + */ +static int zynqmp_dp_train(struct zynqmp_dp *dp) +{ + int ret; + + ret =3D zynqmp_dp_setup(dp, dp->mode.bw_code, dp->mode.lane_cnt, + drm_dp_enhanced_frame_cap(dp->dpcd), + dp->dpcd[DP_MAX_DOWNSPREAD] & + DP_MAX_DOWNSPREAD_0_5); + if (ret) return ret; =20 zynqmp_dp_write(dp, ZYNQMP_DP_SCRAMBLING_DISABLE, 1); --=20 2.35.1.1320.gc452695387.dirty