From nobody Mon Feb 9 03:11:50 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3C5B194AFA; Fri, 9 Aug 2024 13:09:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723208972; cv=none; b=EF7SRv0nryYQI7jzPQkLFxGUIHuFh+QPmUmIma54YpM2NgfZVWyrQpExZAuP5ftRFgNjl251MZPG6DNztbS51XC71p7aKNza4K1+hPux/0NqVdCoxwd9FBaqbkche9mg53oU9/LifBfr2UG3ea8WQdmPtHC5wkRIy/MnTX5BZlk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723208972; c=relaxed/simple; bh=Nbsl3p9OLbL48cTueVzxumNtwMa9kobgVhE46dIs0EU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IUZyRtpj7RdIEoFlpzec1MjzWL/KRxV5rHqIznCLWcgxXOKi4UjLzyxjcq72AGX2SG6gPJ2QXX5wIjeTc56kpXnKMQ5lV3y7hQTTa/0rBzwgMjJk5Tb1B0iFFHkIhQyGRNOMKgUf3NNL8ekpeCMaBrS2qftP+AEMuuW0AfiZ0X4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.helo=mgamail.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=dtIK0hAj; arc=none smtp.client-ip=192.198.163.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.helo=mgamail.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="dtIK0hAj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1723208971; x=1754744971; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Nbsl3p9OLbL48cTueVzxumNtwMa9kobgVhE46dIs0EU=; b=dtIK0hAjrEcTh8/U9tzZVzO/nXSL2PSV1ZU0sOkA6k/Kp73J5+XhcgNm sMf+/Kjw9Cy7oHsqH9ZHYxMVHHBQvfP84F5jA/A+JeWpUz4itRQozTULw YC0d8gM/JNaa6/InyTO9laCxzDcF3YINpYkJeqRmWtVdtKJksdddVTmTQ 9/f0TaOYhdoN8mxh4LQ3X7zdRMIVwc2mkdFPClcADiVJ8bd20qwuhF9GR Gerw6g4FKKymBpmwSaJOS2QsRyqXH9mm34kKMZnmlnyShpaJdD71gHD37 dwVcxM9eVX1TQMlwop2baQNjFrKHYTVkeqi1mETdeqizWqH1Rmu64PjyD g==; X-CSE-ConnectionGUID: WDzzHNYiSUyjwFn2wmLu8Q== X-CSE-MsgGUID: 54cYRwHWRpqvC+lWSFqXBg== X-IronPort-AV: E=McAfee;i="6700,10204,11158"; a="46788175" X-IronPort-AV: E=Sophos;i="6.09,276,1716274800"; d="scan'208";a="46788175" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2024 06:09:29 -0700 X-CSE-ConnectionGUID: NrhCh9GoREKODt0sVRz5pQ== X-CSE-MsgGUID: nd+D3aeOSne7ju3Jrvg6uA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,276,1716274800"; d="scan'208";a="57651681" Received: from black.fi.intel.com ([10.237.72.28]) by fmviesa010.fm.intel.com with ESMTP; 09 Aug 2024 06:09:27 -0700 Received: by black.fi.intel.com (Postfix, from userid 1000) id 0A50C580; Fri, 09 Aug 2024 16:09:25 +0300 (EEST) From: "Kirill A. Shutemov" To: "Kirill A. Shutemov" , Dave Hansen , Thomas Gleixner , Ingo Molnar , Borislav Petkov , x86@kernel.org, "H. Peter Anvin" Cc: linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, Kai Huang , Kuppuswamy Sathyanarayanan , stable@vger.kernel.org Subject: [PATCHv5, REBASED 1/4] x86/tdx: Introduce wrappers to read and write TD metadata Date: Fri, 9 Aug 2024 16:09:20 +0300 Message-ID: <20240809130923.3893765-2-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240809130923.3893765-1-kirill.shutemov@linux.intel.com> References: <20240809130923.3893765-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The TDG_VM_WR TDCALL is used to ask the TDX module to change some TD-specific VM configuration. There is currently only one user in the kernel of this TDCALL leaf. More will be added shortly. Refactor to make way for more users of TDG_VM_WR who will need to modify other TD configuration values. Add a wrapper for the TDG_VM_RD TDCALL that requests TD-specific metadata from the TDX module. There are currently no users for TDG_VM_RD. Mark it as __maybe_unused until the first user appears. This is preparation for enumeration and enabling optional TD features. Signed-off-by: Kirill A. Shutemov Reviewed-by: Kai Huang Reviewed-by: Kuppuswamy Sathyanarayanan Cc: stable@vger.kernel.org --- arch/x86/coco/tdx/tdx.c | 32 ++++++++++++++++++++++++++----- arch/x86/include/asm/shared/tdx.h | 1 + 2 files changed, 28 insertions(+), 5 deletions(-) diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c index 078e2bac2553..64717a96a936 100644 --- a/arch/x86/coco/tdx/tdx.c +++ b/arch/x86/coco/tdx/tdx.c @@ -77,6 +77,32 @@ static inline void tdcall(u64 fn, struct tdx_module_args= *args) panic("TDCALL %lld failed (Buggy TDX module!)\n", fn); } =20 +/* Read TD-scoped metadata */ +static inline u64 __maybe_unused tdg_vm_rd(u64 field, u64 *value) +{ + struct tdx_module_args args =3D { + .rdx =3D field, + }; + u64 ret; + + ret =3D __tdcall_ret(TDG_VM_RD, &args); + *value =3D args.r8; + + return ret; +} + +/* Write TD-scoped metadata */ +static inline u64 tdg_vm_wr(u64 field, u64 value, u64 mask) +{ + struct tdx_module_args args =3D { + .rdx =3D field, + .r8 =3D value, + .r9 =3D mask, + }; + + return __tdcall(TDG_VM_WR, &args); +} + /** * tdx_mcall_get_report0() - Wrapper to get TDREPORT0 (a.k.a. TDREPORT * subtype 0) using TDG.MR.REPORT TDCALL. @@ -924,10 +950,6 @@ static void tdx_kexec_finish(void) =20 void __init tdx_early_init(void) { - struct tdx_module_args args =3D { - .rdx =3D TDCS_NOTIFY_ENABLES, - .r9 =3D -1ULL, - }; u64 cc_mask; u32 eax, sig[3]; =20 @@ -946,7 +968,7 @@ void __init tdx_early_init(void) cc_set_mask(cc_mask); =20 /* Kernel does not use NOTIFY_ENABLES and does not need random #VEs */ - tdcall(TDG_VM_WR, &args); + tdg_vm_wr(TDCS_NOTIFY_ENABLES, 0, -1ULL); =20 /* * All bits above GPA width are reserved and kernel treats shared bit diff --git a/arch/x86/include/asm/shared/tdx.h b/arch/x86/include/asm/share= d/tdx.h index fdfd41511b02..7e12cfa28bec 100644 --- a/arch/x86/include/asm/shared/tdx.h +++ b/arch/x86/include/asm/shared/tdx.h @@ -16,6 +16,7 @@ #define TDG_VP_VEINFO_GET 3 #define TDG_MR_REPORT 4 #define TDG_MEM_PAGE_ACCEPT 6 +#define TDG_VM_RD 7 #define TDG_VM_WR 8 =20 /* TDCS fields. To be used by TDG.VM.WR and TDG.VM.RD module calls */ --=20 2.43.0