From nobody Thu Dec 18 07:11:54 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C528816C869 for ; Fri, 9 Aug 2024 05:58:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723183087; cv=none; b=sjSzG/DbpsrlEKwYPsCJ3c9TlFSf1Vui/1kx0b0Y7RvTDbDCPREmqUxuXydn9opWe3a50MQ0x0WyKdI2ahM4UhGuIxW1iqo1PMpVxGDld7N+2EgDGqT7KxD90M0mUouDBBFbtSbZw2i4lmlf0ZBJBs5QUaXNsIuuclMYip5WURM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723183087; c=relaxed/simple; bh=B+6em4UthMTuByvNjr21u/tD+rVpRmRx6QqDm8rjcJU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=b+UEqL2yURiZM+3pQCGaIDJriYrSsCtj5v+wmaUzD18N2t9ffGP2AKWQoHe73fD/Y8PsRzQ4iXyixA5RhvRCWdOF51VOoGL9yRQiPVmCtebKYnY8nxvR2bSJIN61w0Nzu8QWig3RBmrORPgvU3qYbit3nQ8wr0urVAijKlLG+iE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=B+ERBb8C; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="B+ERBb8C" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1723183086; x=1754719086; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=B+6em4UthMTuByvNjr21u/tD+rVpRmRx6QqDm8rjcJU=; b=B+ERBb8CI9/RdwxncSKLzdx0wfLrS4tLcjYj6KsQZEsuxyE7afwswWDi Ngq7Lfh4WdMtSYAi41pR7bLqvWjxdG60n5kJMjWwgCIxT1PPEqJWk7JTb 13+05T+EQbPzFkw8Kmc47chYBN/G2jo2gH8e4Ktkuw3SaxPln3Iv9KQ/Y b90vZJB2xEFTCjpt96yBe2gJGEuAaRHcVg0ssCFgu5+oVaJqAOGtqd5vA QQCe1pasFwFzuspQm0qs2fMQ/YM6GAjB2DM+x8hVxNoPn1gOY92KX5SCs ysM2QJ4uDAQlEV8/dsxmApV487BhmMeBoxOU3nu7p/aFz8FXxV+UHqF4L g==; X-CSE-ConnectionGUID: rozFj1pvQmaFtp00snqagQ== X-CSE-MsgGUID: cK8GX3DaTEOgmDXGo2gdlQ== X-IronPort-AV: E=McAfee;i="6700,10204,11158"; a="21469112" X-IronPort-AV: E=Sophos;i="6.09,275,1716274800"; d="scan'208";a="21469112" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2024 22:58:05 -0700 X-CSE-ConnectionGUID: hNMVCE8xQ5mjuc2GGhrVZg== X-CSE-MsgGUID: 228R14gBSQ2lng4quV72hw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,275,1716274800"; d="scan'208";a="57540867" Received: from allen-box.sh.intel.com ([10.239.159.127]) by fmviesa010.fm.intel.com with ESMTP; 08 Aug 2024 22:58:03 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu , Jason Gunthorpe Subject: [PATCH v4 1/7] iommu/vt-d: Require DMA domain if hardware not support passthrough Date: Fri, 9 Aug 2024 13:54:25 +0800 Message-Id: <20240809055431.36513-2-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240809055431.36513-1-baolu.lu@linux.intel.com> References: <20240809055431.36513-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The iommu core defines the def_domain_type callback to query the iommu driver about hardware capability and quirks. The iommu driver should declare IOMMU_DOMAIN_DMA requirement for hardware lacking pass-through capability. Earlier VT-d hardware implementations did not support pass-through translation mode. The iommu driver relied on a paging domain with all physical system memory addresses identically mapped to the same IOVA to simulate pass-through translation before the def_domain_type was introduced and it has been kept until now. It's time to adjust it now to make the Intel iommu driver follow the def_domain_type semantics. Reviewed-by: Jason Gunthorpe Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian --- drivers/iommu/intel/iommu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 9ff8b83c19a3..90ad794a1be7 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -2149,6 +2149,16 @@ static bool device_rmrr_is_relaxable(struct device *= dev) =20 static int device_def_domain_type(struct device *dev) { + struct device_domain_info *info =3D dev_iommu_priv_get(dev); + struct intel_iommu *iommu =3D info->iommu; + + /* + * Hardware does not support the passthrough translation mode. + * Always use a dynamaic mapping domain. + */ + if (!ecap_pass_through(iommu->ecap)) + return IOMMU_DOMAIN_DMA; + if (dev_is_pci(dev)) { struct pci_dev *pdev =3D to_pci_dev(dev); =20 --=20 2.34.1 From nobody Thu Dec 18 07:11:54 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 276DB16C878 for ; Fri, 9 Aug 2024 05:58:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723183089; cv=none; b=kuCutvUbx9JmqGO54lSGrpjS69zf91rfSewR0zlLIOuDUwRhLt9SwSuPAhsaeoqThsXhnlJK7mFvv21/f/EPjJ9Jt6unObZ/L51vHDqxlGZ2c+WHQ/qa8G687NjjcyPq1RvsNXVCXk1N21qxrAm0FOvnzYRo4LF6/joT7/4Vb6E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723183089; c=relaxed/simple; bh=wbU3ZV/NJxEZIOwGOe90pQPqrLese+1fXkQ3W4IMrQI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=DGYbENRLv4VlzzthumZWbQXt8wWCDQi0jEmWZcjjYbTJfQ9hU4qI+5niMdRcoJni74JI6u2/6+jZuGRZH0DGCL5kdAMpBEXilynPZ1wtToOlHditG60mKqTjdiomRJA+tbi84kVE5SVUfsXzX9eA6JVQiJEfglFYeHHZ/Vl8btE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=W48QPsGv; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="W48QPsGv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1723183087; x=1754719087; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wbU3ZV/NJxEZIOwGOe90pQPqrLese+1fXkQ3W4IMrQI=; b=W48QPsGv8fBof1oXeENMhC99E9WXyc+eKZqUn+adYPufOgGTu1dPFYJS Ce4b8Q3IQxkEXkmq/BN4Pe+yJbQ3Dd71Veuxq8OT2CgFr4nny5tikC0sP 6BJrPvQZyKoVtXA2LGTZHDOkzM34mZHABnMDkYhzJ8gPq4CnUVU4UPEGh OU+QzPK97YuIY5y3bNvM8+JxfnAWomxJZvNpVQuaOuqAMY7h/JWgLA4U4 BxJkKTe5/w8oITY+KcvdmAsqAg4yafVyuIW7L9p17Wa1o1y1XRQ5WfJxX T0QDKgAhXW1E19si6KU47ZY1cKLKBpBruEIgKPUO/XLOo5ZNbaZawUQ9C A==; X-CSE-ConnectionGUID: kPjeefXpQcCjJ+XDb2X/0Q== X-CSE-MsgGUID: r3BwQsejRFOYhSYqlFkaJQ== X-IronPort-AV: E=McAfee;i="6700,10204,11158"; a="21469121" X-IronPort-AV: E=Sophos;i="6.09,275,1716274800"; d="scan'208";a="21469121" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2024 22:58:07 -0700 X-CSE-ConnectionGUID: 1lkTrB73Qmivd9q1L2AKAg== X-CSE-MsgGUID: HTnGqAznR16qMLikK7HsNg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,275,1716274800"; d="scan'208";a="57540880" Received: from allen-box.sh.intel.com ([10.239.159.127]) by fmviesa010.fm.intel.com with ESMTP; 08 Aug 2024 22:58:05 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu , Jason Gunthorpe Subject: [PATCH v4 2/7] iommu/vt-d: Remove identity mappings from si_domain Date: Fri, 9 Aug 2024 13:54:26 +0800 Message-Id: <20240809055431.36513-3-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240809055431.36513-1-baolu.lu@linux.intel.com> References: <20240809055431.36513-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As the driver has enforced DMA domains for devices managed by an IOMMU hardware that doesn't support passthrough translation mode, there is no need for static identity mappings in the si_domain. Remove the identity mapping code to avoid dead code. Reviewed-by: Jason Gunthorpe Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian --- drivers/iommu/intel/iommu.c | 122 ++---------------------------------- 1 file changed, 4 insertions(+), 118 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 90ad794a1be7..723ea9f3f501 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -167,14 +167,7 @@ static void device_rbtree_remove(struct device_domain_= info *info) spin_unlock_irqrestore(&iommu->device_rbtree_lock, flags); } =20 -/* - * This domain is a statically identity mapping domain. - * 1. This domain creats a static 1:1 mapping to all usable memory. - * 2. It maps to each iommu if successful. - * 3. Each iommu mapps to this domain if successful. - */ static struct dmar_domain *si_domain; -static int hw_pass_through =3D 1; =20 struct dmar_rmrr_unit { struct list_head list; /* list of rmrr units */ @@ -1647,7 +1640,7 @@ static int domain_context_mapping_one(struct dmar_dom= ain *domain, struct context_entry *context; int agaw, ret; =20 - if (hw_pass_through && domain_type_is_si(domain)) + if (domain_type_is_si(domain)) translation =3D CONTEXT_TT_PASS_THROUGH; =20 pr_debug("Set context mapping for %02x:%02x.%d\n", @@ -1998,29 +1991,10 @@ static bool dev_is_real_dma_subdevice(struct device= *dev) pci_real_dma_dev(to_pci_dev(dev)) !=3D to_pci_dev(dev); } =20 -static int iommu_domain_identity_map(struct dmar_domain *domain, - unsigned long first_vpfn, - unsigned long last_vpfn) -{ - /* - * RMRR range might have overlap with physical memory range, - * clear it first - */ - dma_pte_clear_range(domain, first_vpfn, last_vpfn); - - return __domain_mapping(domain, first_vpfn, - first_vpfn, last_vpfn - first_vpfn + 1, - DMA_PTE_READ|DMA_PTE_WRITE, GFP_KERNEL); -} - static int md_domain_init(struct dmar_domain *domain, int guest_width); =20 -static int __init si_domain_init(int hw) +static int __init si_domain_init(void) { - struct dmar_rmrr_unit *rmrr; - struct device *dev; - int i, nid, ret; - si_domain =3D alloc_domain(IOMMU_DOMAIN_IDENTITY); if (!si_domain) return -EFAULT; @@ -2031,44 +2005,6 @@ static int __init si_domain_init(int hw) return -EFAULT; } =20 - if (hw) - return 0; - - for_each_online_node(nid) { - unsigned long start_pfn, end_pfn; - int i; - - for_each_mem_pfn_range(i, nid, &start_pfn, &end_pfn, NULL) { - ret =3D iommu_domain_identity_map(si_domain, - mm_to_dma_pfn_start(start_pfn), - mm_to_dma_pfn_end(end_pfn-1)); - if (ret) - return ret; - } - } - - /* - * Identity map the RMRRs so that devices with RMRRs could also use - * the si_domain. - */ - for_each_rmrr_units(rmrr) { - for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt, - i, dev) { - unsigned long long start =3D rmrr->base_address; - unsigned long long end =3D rmrr->end_address; - - if (WARN_ON(end < start || - end >> agaw_to_width(si_domain->agaw))) - continue; - - ret =3D iommu_domain_identity_map(si_domain, - mm_to_dma_pfn_start(start >> PAGE_SHIFT), - mm_to_dma_pfn_end(end >> PAGE_SHIFT)); - if (ret) - return ret; - } - } - return 0; } =20 @@ -2094,7 +2030,7 @@ static int dmar_domain_attach_device(struct dmar_doma= in *domain, =20 if (!sm_supported(iommu)) ret =3D domain_context_mapping(domain, dev); - else if (hw_pass_through && domain_type_is_si(domain)) + else if (domain_type_is_si(domain)) ret =3D intel_pasid_setup_pass_through(iommu, dev, IOMMU_NO_PASID); else if (domain->use_first_level) ret =3D domain_setup_first_level(iommu, domain, dev, IOMMU_NO_PASID); @@ -2449,8 +2385,6 @@ static int __init init_dmars(void) } } =20 - if (!ecap_pass_through(iommu->ecap)) - hw_pass_through =3D 0; intel_svm_check(iommu); } =20 @@ -2466,7 +2400,7 @@ static int __init init_dmars(void) =20 check_tylersburg_isoch(); =20 - ret =3D si_domain_init(hw_pass_through); + ret =3D si_domain_init(); if (ret) goto free_iommu; =20 @@ -2893,12 +2827,6 @@ static int intel_iommu_add(struct dmar_drhd_unit *dm= aru) if (ret) goto out; =20 - if (hw_pass_through && !ecap_pass_through(iommu->ecap)) { - pr_warn("%s: Doesn't support hardware pass through.\n", - iommu->name); - return -ENXIO; - } - sp =3D domain_update_iommu_superpage(NULL, iommu) - 1; if (sp >=3D 0 && !(cap_super_page_val(iommu->cap) & (1 << sp))) { pr_warn("%s: Doesn't support large page.\n", @@ -3149,43 +3077,6 @@ int dmar_iommu_notify_scope_dev(struct dmar_pci_noti= fy_info *info) return 0; } =20 -static int intel_iommu_memory_notifier(struct notifier_block *nb, - unsigned long val, void *v) -{ - struct memory_notify *mhp =3D v; - unsigned long start_vpfn =3D mm_to_dma_pfn_start(mhp->start_pfn); - unsigned long last_vpfn =3D mm_to_dma_pfn_end(mhp->start_pfn + - mhp->nr_pages - 1); - - switch (val) { - case MEM_GOING_ONLINE: - if (iommu_domain_identity_map(si_domain, - start_vpfn, last_vpfn)) { - pr_warn("Failed to build identity map for [%lx-%lx]\n", - start_vpfn, last_vpfn); - return NOTIFY_BAD; - } - break; - - case MEM_OFFLINE: - case MEM_CANCEL_ONLINE: - { - LIST_HEAD(freelist); - - domain_unmap(si_domain, start_vpfn, last_vpfn, &freelist); - iommu_put_pages_list(&freelist); - } - break; - } - - return NOTIFY_OK; -} - -static struct notifier_block intel_iommu_memory_nb =3D { - .notifier_call =3D intel_iommu_memory_notifier, - .priority =3D 0 -}; - static void intel_disable_iommus(void) { struct intel_iommu *iommu =3D NULL; @@ -3482,12 +3373,7 @@ int __init intel_iommu_init(void) =20 iommu_pmu_register(iommu); } - up_read(&dmar_global_lock); =20 - if (si_domain && !hw_pass_through) - register_memory_notifier(&intel_iommu_memory_nb); - - down_read(&dmar_global_lock); if (probe_acpi_namespace_devices()) pr_warn("ACPI name space devices didn't probe correctly\n"); =20 --=20 2.34.1 From nobody Thu Dec 18 07:11:54 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51E1416D301 for ; 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X-CSE-ConnectionGUID: zEFL7/x8RjW98vxnI9YZdA== X-CSE-MsgGUID: xTvRbb9BTUWmNX7/xFer/Q== X-IronPort-AV: E=McAfee;i="6700,10204,11158"; a="21469133" X-IronPort-AV: E=Sophos;i="6.09,275,1716274800"; d="scan'208";a="21469133" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2024 22:58:09 -0700 X-CSE-ConnectionGUID: /S8jRWbMQmy0aB/OaSzn6g== X-CSE-MsgGUID: Rf5PO/EdRmm+2Mr5ridiig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,275,1716274800"; d="scan'208";a="57540890" Received: from allen-box.sh.intel.com ([10.239.159.127]) by fmviesa010.fm.intel.com with ESMTP; 08 Aug 2024 22:58:07 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu , Jason Gunthorpe Subject: [PATCH v4 3/7] iommu/vt-d: Always reserve a domain ID for identity setup Date: Fri, 9 Aug 2024 13:54:27 +0800 Message-Id: <20240809055431.36513-4-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240809055431.36513-1-baolu.lu@linux.intel.com> References: <20240809055431.36513-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" We will use a global static identity domain. Reserve a static domain ID for it. Reviewed-by: Jason Gunthorpe Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian --- drivers/iommu/intel/iommu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 723ea9f3f501..c019fb3b3e78 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -1440,10 +1440,10 @@ static int iommu_init_domains(struct intel_iommu *i= ommu) * entry for first-level or pass-through translation modes should * be programmed with a domain id different from those used for * second-level or nested translation. We reserve a domain id for - * this purpose. + * this purpose. This domain id is also used for identity domain + * in legacy mode. */ - if (sm_supported(iommu)) - set_bit(FLPT_DEFAULT_DID, iommu->domain_ids); + set_bit(FLPT_DEFAULT_DID, iommu->domain_ids); =20 return 0; } --=20 2.34.1 From nobody Thu Dec 18 07:11:54 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C86B616D338 for ; Fri, 9 Aug 2024 05:58:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723183093; cv=none; b=TJRSRrs6M85w1qwDXltNwz0nTSSHCN97bfDTl5qRLHD9Wy2tReQkapHRcQWmJ84KyfnYbb9A3CMrM7X0I8UcfHtT2oLGj3bY8j2xKsUsrP28YIFjblembfBPDCWseQhOUvMQOdaDQ04QBGOSJG/TZ6LzpmWeXDIleZnTGzmnvi0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723183093; c=relaxed/simple; bh=c7v96DK+GCPmvTOHcXM9hx7vasVuUoNQMA4x16fiRTA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=f/K77V2SvsbxbDnJN5vYXHmRIzZGpSF3vqR0d7zoG+N37eNpzwxf+OJucBaKr2GSrVggKluyBMQzzRz5r6MYjudGLWeNjm9b2CryXP3vYan+/tBLu8+3I+79u0Pc+fZLfdmnlMiGJ9RtTFe4ruu0r1PmKL8foGDSbqYEVeN3SVc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=EE/SDKM9; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EE/SDKM9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1723183092; x=1754719092; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=c7v96DK+GCPmvTOHcXM9hx7vasVuUoNQMA4x16fiRTA=; b=EE/SDKM9mrB7f7SWJmKQ5jx6bQa1Yx9JwqxXNh9QsKskFAhIB6MNdbLg ourCb57nkPsMrnKgGqoBgCbsI2gm7Z3gw8jO0UaXNpqmItm1AdLVrt3PT Fair87s3IBX9/JcedSiZwZqQQssIb8Rn218S2+0nBXKWdHE7iI3/7iGFL IKatFtGJccdlPON5SMOExk5hXfdwdBfDAoxnw/Zzo6cTxbFokKybz3+1N SmXpGb5YUqyGwBIxblxJuUbaeJwGHDiBYV81uUQnx6OZnn1MnIYxjsaIz HQx9NvKw/gLJBshly9A9jqLIbiabJPkFOq9XTy0snC8HPKFC2HVifA4rw w==; X-CSE-ConnectionGUID: QH7/OrFLQJq926HnVJgTIQ== X-CSE-MsgGUID: W7muLkdtRfy5XxXGIPBc+Q== X-IronPort-AV: E=McAfee;i="6700,10204,11158"; a="21469143" X-IronPort-AV: E=Sophos;i="6.09,275,1716274800"; d="scan'208";a="21469143" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2024 22:58:12 -0700 X-CSE-ConnectionGUID: YOdDjjWtRAi+TWiIO2bKRA== X-CSE-MsgGUID: mBmRpl6OT2e2Lj2mitnpHw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,275,1716274800"; d="scan'208";a="57540907" Received: from allen-box.sh.intel.com ([10.239.159.127]) by fmviesa010.fm.intel.com with ESMTP; 08 Aug 2024 22:58:10 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu , Jason Gunthorpe Subject: [PATCH v4 4/7] iommu/vt-d: Remove has_iotlb_device flag Date: Fri, 9 Aug 2024 13:54:28 +0800 Message-Id: <20240809055431.36513-5-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240809055431.36513-1-baolu.lu@linux.intel.com> References: <20240809055431.36513-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The has_iotlb_device flag was used to indicate if a domain had attached devices with ATS enabled. Domains without this flag didn't require device TLB invalidation during unmap operations, optimizing performance by avoiding unnecessary device iteration. With the introduction of cache tags, this flag is no longer needed. The code to iterate over attached devices was removed by commit 06792d067989 ("iommu/vt-d: Cleanup use of iommu_flush_iotlb_psi()"). Remove has_iotlb_device to avoid unnecessary code. Suggested-by: Jason Gunthorpe Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian --- drivers/iommu/intel/iommu.h | 2 -- drivers/iommu/intel/iommu.c | 34 +--------------------------------- drivers/iommu/intel/nested.c | 2 -- 3 files changed, 1 insertion(+), 37 deletions(-) diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index b67c14da1240..01002ae2a091 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -588,7 +588,6 @@ struct dmar_domain { int nid; /* node id */ struct xarray iommu_array; /* Attached IOMMU array */ =20 - u8 has_iotlb_device: 1; u8 iommu_coherency: 1; /* indicate coherency of iommu access */ u8 force_snooping : 1; /* Create IOPTEs with snoop control */ u8 set_pte_snp:1; @@ -1104,7 +1103,6 @@ int qi_submit_sync(struct intel_iommu *iommu, struct = qi_desc *desc, */ #define QI_OPT_WAIT_DRAIN BIT(0) =20 -void domain_update_iotlb(struct dmar_domain *domain); int domain_attach_iommu(struct dmar_domain *domain, struct intel_iommu *io= mmu); void domain_detach_iommu(struct dmar_domain *domain, struct intel_iommu *i= ommu); void device_block_translation(struct device *dev); diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index c019fb3b3e78..aa8e10a2ad51 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -485,7 +485,6 @@ void domain_update_iommu_cap(struct dmar_domain *domain) domain->domain.geometry.aperture_end =3D __DOMAIN_MAX_ADDR(domain->gaw); =20 domain->domain.pgsize_bitmap |=3D domain_super_pgsize_bitmap(domain); - domain_update_iotlb(domain); } =20 struct context_entry *iommu_context_addr(struct intel_iommu *iommu, u8 bus, @@ -1263,32 +1262,6 @@ domain_lookup_dev_info(struct dmar_domain *domain, return NULL; } =20 -void domain_update_iotlb(struct dmar_domain *domain) -{ - struct dev_pasid_info *dev_pasid; - struct device_domain_info *info; - bool has_iotlb_device =3D false; - unsigned long flags; - - spin_lock_irqsave(&domain->lock, flags); - list_for_each_entry(info, &domain->devices, link) { - if (info->ats_enabled) { - has_iotlb_device =3D true; - break; - } - } - - list_for_each_entry(dev_pasid, &domain->dev_pasids, link_domain) { - info =3D dev_iommu_priv_get(dev_pasid->dev); - if (info->ats_enabled) { - has_iotlb_device =3D true; - break; - } - } - domain->has_iotlb_device =3D has_iotlb_device; - spin_unlock_irqrestore(&domain->lock, flags); -} - /* * The extra devTLB flush quirk impacts those QAT devices with PCI device * IDs ranging from 0x4940 to 0x4943. It is exempted from risky_device() @@ -1325,10 +1298,8 @@ static void iommu_enable_pci_caps(struct device_doma= in_info *info) info->pasid_enabled =3D 1; =20 if (info->ats_supported && pci_ats_page_aligned(pdev) && - !pci_enable_ats(pdev, VTD_PAGE_SHIFT)) { + !pci_enable_ats(pdev, VTD_PAGE_SHIFT)) info->ats_enabled =3D 1; - domain_update_iotlb(info->domain); - } } =20 static void iommu_disable_pci_caps(struct device_domain_info *info) @@ -1343,7 +1314,6 @@ static void iommu_disable_pci_caps(struct device_doma= in_info *info) if (info->ats_enabled) { pci_disable_ats(pdev); info->ats_enabled =3D 0; - domain_update_iotlb(info->domain); } =20 if (info->pasid_enabled) { @@ -1517,7 +1487,6 @@ static struct dmar_domain *alloc_domain(unsigned int = type) domain->nid =3D NUMA_NO_NODE; if (first_level_by_default(type)) domain->use_first_level =3D true; - domain->has_iotlb_device =3D false; INIT_LIST_HEAD(&domain->devices); INIT_LIST_HEAD(&domain->dev_pasids); INIT_LIST_HEAD(&domain->cache_tags); @@ -3518,7 +3487,6 @@ static struct dmar_domain *paging_domain_alloc(struct= device *dev, bool first_st xa_init(&domain->iommu_array); =20 domain->nid =3D dev_to_node(dev); - domain->has_iotlb_device =3D info->ats_enabled; domain->use_first_level =3D first_stage; =20 /* calculate the address width */ diff --git a/drivers/iommu/intel/nested.c b/drivers/iommu/intel/nested.c index 16a2bcf5cfeb..36a91b1b52be 100644 --- a/drivers/iommu/intel/nested.c +++ b/drivers/iommu/intel/nested.c @@ -66,8 +66,6 @@ static int intel_nested_attach_dev(struct iommu_domain *d= omain, list_add(&info->link, &dmar_domain->devices); spin_unlock_irqrestore(&dmar_domain->lock, flags); =20 - domain_update_iotlb(dmar_domain); - return 0; unassign_tag: cache_tag_unassign_domain(dmar_domain, dev, IOMMU_NO_PASID); --=20 2.34.1 From nobody Thu Dec 18 07:11:54 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E8A816D4D2 for ; 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X-CSE-ConnectionGUID: bUIVlhd1SWiBENGoaUZ6ww== X-CSE-MsgGUID: IUpXLCZwS2KCz22rpKHipg== X-IronPort-AV: E=McAfee;i="6700,10204,11158"; a="21469154" X-IronPort-AV: E=Sophos;i="6.09,275,1716274800"; d="scan'208";a="21469154" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2024 22:58:14 -0700 X-CSE-ConnectionGUID: ERqxv9LVSy2+gPg6Vpt1+w== X-CSE-MsgGUID: /VyJAjy5Twa3qL+NKN8bNg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,275,1716274800"; d="scan'208";a="57540924" Received: from allen-box.sh.intel.com ([10.239.159.127]) by fmviesa010.fm.intel.com with ESMTP; 08 Aug 2024 22:58:12 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu , Jason Gunthorpe Subject: [PATCH v4 5/7] iommu/vt-d: Factor out helpers from domain_context_mapping_one() Date: Fri, 9 Aug 2024 13:54:29 +0800 Message-Id: <20240809055431.36513-6-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240809055431.36513-1-baolu.lu@linux.intel.com> References: <20240809055431.36513-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extract common code from domain_context_mapping_one() into new helpers, making it reusable by other functions such as the upcoming identity domain implementation. No intentional functional changes. Reviewed-by: Jason Gunthorpe Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian --- drivers/iommu/intel/iommu.c | 99 ++++++++++++++++++++++--------------- 1 file changed, 58 insertions(+), 41 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index aa8e10a2ad51..7950152bb4e6 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -1597,6 +1597,61 @@ static void domain_exit(struct dmar_domain *domain) kfree(domain); } =20 +/* + * For kdump cases, old valid entries may be cached due to the + * in-flight DMA and copied pgtable, but there is no unmapping + * behaviour for them, thus we need an explicit cache flush for + * the newly-mapped device. For kdump, at this point, the device + * is supposed to finish reset at its driver probe stage, so no + * in-flight DMA will exist, and we don't need to worry anymore + * hereafter. + */ +static void copied_context_tear_down(struct intel_iommu *iommu, + struct context_entry *context, + u8 bus, u8 devfn) +{ + u16 did_old; + + if (!context_copied(iommu, bus, devfn)) + return; + + assert_spin_locked(&iommu->lock); + + did_old =3D context_domain_id(context); + context_clear_entry(context); + + if (did_old < cap_ndoms(iommu->cap)) { + iommu->flush.flush_context(iommu, did_old, + (((u16)bus) << 8) | devfn, + DMA_CCMD_MASK_NOBIT, + DMA_CCMD_DEVICE_INVL); + iommu->flush.flush_iotlb(iommu, did_old, 0, 0, + DMA_TLB_DSI_FLUSH); + } + + clear_context_copied(iommu, bus, devfn); +} + +/* + * It's a non-present to present mapping. If hardware doesn't cache + * non-present entry we only need to flush the write-buffer. If the + * _does_ cache non-present entries, then it does so in the special + * domain #0, which we have to flush: + */ +static void context_present_cache_flush(struct intel_iommu *iommu, u16 did, + u8 bus, u8 devfn) +{ + if (cap_caching_mode(iommu->cap)) { + iommu->flush.flush_context(iommu, 0, + (((u16)bus) << 8) | devfn, + DMA_CCMD_MASK_NOBIT, + DMA_CCMD_DEVICE_INVL); + iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH); + } else { + iommu_flush_write_buffer(iommu); + } +} + static int domain_context_mapping_one(struct dmar_domain *domain, struct intel_iommu *iommu, u8 bus, u8 devfn) @@ -1625,31 +1680,9 @@ static int domain_context_mapping_one(struct dmar_do= main *domain, if (context_present(context) && !context_copied(iommu, bus, devfn)) goto out_unlock; =20 - /* - * For kdump cases, old valid entries may be cached due to the - * in-flight DMA and copied pgtable, but there is no unmapping - * behaviour for them, thus we need an explicit cache flush for - * the newly-mapped device. For kdump, at this point, the device - * is supposed to finish reset at its driver probe stage, so no - * in-flight DMA will exist, and we don't need to worry anymore - * hereafter. - */ - if (context_copied(iommu, bus, devfn)) { - u16 did_old =3D context_domain_id(context); - - if (did_old < cap_ndoms(iommu->cap)) { - iommu->flush.flush_context(iommu, did_old, - (((u16)bus) << 8) | devfn, - DMA_CCMD_MASK_NOBIT, - DMA_CCMD_DEVICE_INVL); - iommu->flush.flush_iotlb(iommu, did_old, 0, 0, - DMA_TLB_DSI_FLUSH); - } - - clear_context_copied(iommu, bus, devfn); - } - + copied_context_tear_down(iommu, context, bus, devfn); context_clear_entry(context); + context_set_domain_id(context, did); =20 if (translation !=3D CONTEXT_TT_PASS_THROUGH) { @@ -1685,23 +1718,7 @@ static int domain_context_mapping_one(struct dmar_do= main *domain, context_set_present(context); if (!ecap_coherent(iommu->ecap)) clflush_cache_range(context, sizeof(*context)); - - /* - * It's a non-present to present mapping. If hardware doesn't cache - * non-present entry we only need to flush the write-buffer. If the - * _does_ cache non-present entries, then it does so in the special - * domain #0, which we have to flush: - */ - if (cap_caching_mode(iommu->cap)) { - iommu->flush.flush_context(iommu, 0, - (((u16)bus) << 8) | devfn, - DMA_CCMD_MASK_NOBIT, - DMA_CCMD_DEVICE_INVL); - iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH); - } else { - iommu_flush_write_buffer(iommu); - } - + context_present_cache_flush(iommu, did, bus, devfn); ret =3D 0; =20 out_unlock: --=20 2.34.1 From nobody Thu Dec 18 07:11:54 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78E7116D9AB for ; Fri, 9 Aug 2024 05:58:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723183098; cv=none; b=AZs4miQWx362zgx36+AbIDD1+qESBD3ClJ6JL6BjPYNkXhxXanMu7TvD1N3RxV0YFIxCCEvvQDTZZCh+wDL7tW8e5JxXhiHQGmtX6EPftM5qtKonD/aI4i7NMz557VbvgwWQzJ8tUEYM5skD8Lbk1giWjg1d8i8TtET0LS4Q4vk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723183098; c=relaxed/simple; bh=dGJ807P2NgMXfp/nKRwxut/4ZkS9X3sgQHFPed4vft0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hdmlGkFFGD0pelh0VIAvXt3OMYB0Uv9H5IwlC9g8dExsN8NoPGhGDPw6QBrCgpdbtln1iy05jqIH4EepbnEquohhU8+01YgfrytrvTuO4llIrm8fv1O+9vfRvBVIg0cNVTSAKggw711dwbploKQkNfE2jlDCXX7K2yEvcdCGHKo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=XgLdeQdk; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XgLdeQdk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1723183097; x=1754719097; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dGJ807P2NgMXfp/nKRwxut/4ZkS9X3sgQHFPed4vft0=; b=XgLdeQdkW6/04pZoAnw63fQovPn0iHEr+Qj0ec6l+jippQY/dnBUIde2 SD8Mj3wZ5hEGDXyEfTBItPcPn5Sr7bI06+KOPoamW9/RQJnE7fgAerrzj 0zk0SG0mK6a0CNm/j4rG02QXgvJvWNEJWk1OO5DLzZHJirGdb6kV14YLx c5dgaInfLJWgSCjnyTqXPofvUPk3+MPdf+u3OQ7/fFgqmGxPH2Olxlm0+ NHw57c1uGOmihsGqyHIqfmxE8nKT5ogGi3ewZEV9YcDBUqE7LhYpRu/gc 7SYrQeWz9ghPYlvR8aTsLgjsYJINTdNF52g9YA97nLXnMENz9FEzUDlaa A==; X-CSE-ConnectionGUID: JTr/0tplSSq8/GzRrVidSQ== X-CSE-MsgGUID: /3WYJqybQPa2C5Nxo2L0Ag== X-IronPort-AV: E=McAfee;i="6700,10204,11158"; a="21469168" X-IronPort-AV: E=Sophos;i="6.09,275,1716274800"; d="scan'208";a="21469168" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2024 22:58:17 -0700 X-CSE-ConnectionGUID: eTYEuUu9SUq7TnnbWPZGzQ== X-CSE-MsgGUID: fzBSnxkwTYmuVRNuiEp82w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,275,1716274800"; d="scan'208";a="57540936" Received: from allen-box.sh.intel.com ([10.239.159.127]) by fmviesa010.fm.intel.com with ESMTP; 08 Aug 2024 22:58:14 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu , Jason Gunthorpe Subject: [PATCH v4 6/7] iommu/vt-d: Add support for static identity domain Date: Fri, 9 Aug 2024 13:54:30 +0800 Message-Id: <20240809055431.36513-7-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240809055431.36513-1-baolu.lu@linux.intel.com> References: <20240809055431.36513-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Software determines VT-d hardware support for passthrough translation by inspecting the capability register. If passthrough translation is not supported, the device is instructed to use DMA domain for its default domain. Add a global static identity domain with guaranteed attach semantics for IOMMUs that support passthrough translation mode. The global static identity domain is a dummy domain without corresponding dmar_domain structure. Consequently, the device's info->domain will be NULL with the identity domain is attached. Refactor the code accordingly. Reviewed-by: Jason Gunthorpe Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian --- drivers/iommu/intel/iommu.c | 114 ++++++++++++++++++++++++++++++++++-- 1 file changed, 110 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 7950152bb4e6..14f1fcf17152 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -3691,11 +3691,9 @@ int prepare_domain_attach_device(struct iommu_domain= *domain, static int intel_iommu_attach_device(struct iommu_domain *domain, struct device *dev) { - struct device_domain_info *info =3D dev_iommu_priv_get(dev); int ret; =20 - if (info->domain) - device_block_translation(dev); + device_block_translation(dev); =20 ret =3D prepare_domain_attach_device(domain, dev); if (ret) @@ -4301,11 +4299,17 @@ static void intel_iommu_remove_dev_pasid(struct dev= ice *dev, ioasid_t pasid, struct iommu_domain *domain) { struct device_domain_info *info =3D dev_iommu_priv_get(dev); - struct dmar_domain *dmar_domain =3D to_dmar_domain(domain); struct dev_pasid_info *curr, *dev_pasid =3D NULL; struct intel_iommu *iommu =3D info->iommu; + struct dmar_domain *dmar_domain; unsigned long flags; =20 + if (domain->type =3D=3D IOMMU_DOMAIN_IDENTITY) { + intel_pasid_tear_down_entry(iommu, dev, pasid, false); + return; + } + + dmar_domain =3D to_dmar_domain(domain); spin_lock_irqsave(&dmar_domain->lock, flags); list_for_each_entry(curr, &dmar_domain->dev_pasids, link_domain) { if (curr->dev =3D=3D dev && curr->pasid =3D=3D pasid) { @@ -4532,9 +4536,111 @@ static const struct iommu_dirty_ops intel_dirty_ops= =3D { .read_and_clear_dirty =3D intel_iommu_read_and_clear_dirty, }; =20 +static int context_setup_pass_through(struct device *dev, u8 bus, u8 devfn) +{ + struct device_domain_info *info =3D dev_iommu_priv_get(dev); + struct intel_iommu *iommu =3D info->iommu; + struct context_entry *context; + + spin_lock(&iommu->lock); + context =3D iommu_context_addr(iommu, bus, devfn, 1); + if (!context) { + spin_unlock(&iommu->lock); + return -ENOMEM; + } + + if (context_present(context) && !context_copied(iommu, bus, devfn)) { + spin_unlock(&iommu->lock); + return 0; + } + + copied_context_tear_down(iommu, context, bus, devfn); + context_clear_entry(context); + context_set_domain_id(context, FLPT_DEFAULT_DID); + + /* + * In pass through mode, AW must be programmed to indicate the largest + * AGAW value supported by hardware. And ASR is ignored by hardware. + */ + context_set_address_width(context, iommu->msagaw); + context_set_translation_type(context, CONTEXT_TT_PASS_THROUGH); + context_set_fault_enable(context); + context_set_present(context); + if (!ecap_coherent(iommu->ecap)) + clflush_cache_range(context, sizeof(*context)); + context_present_cache_flush(iommu, FLPT_DEFAULT_DID, bus, devfn); + spin_unlock(&iommu->lock); + + return 0; +} + +static int context_setup_pass_through_cb(struct pci_dev *pdev, u16 alias, = void *data) +{ + struct device *dev =3D data; + + if (dev !=3D &pdev->dev) + return 0; + + return context_setup_pass_through(dev, PCI_BUS_NUM(alias), alias & 0xff); +} + +static int device_setup_pass_through(struct device *dev) +{ + struct device_domain_info *info =3D dev_iommu_priv_get(dev); + + if (!dev_is_pci(dev)) + return context_setup_pass_through(dev, info->bus, info->devfn); + + return pci_for_each_dma_alias(to_pci_dev(dev), + context_setup_pass_through_cb, dev); +} + +static int identity_domain_attach_dev(struct iommu_domain *domain, struct = device *dev) +{ + struct device_domain_info *info =3D dev_iommu_priv_get(dev); + struct intel_iommu *iommu =3D info->iommu; + int ret; + + device_block_translation(dev); + + if (dev_is_real_dma_subdevice(dev)) + return 0; + + if (sm_supported(iommu)) { + ret =3D intel_pasid_setup_pass_through(iommu, dev, IOMMU_NO_PASID); + if (!ret) + iommu_enable_pci_caps(info); + } else { + ret =3D device_setup_pass_through(dev); + } + + return ret; +} + +static int identity_domain_set_dev_pasid(struct iommu_domain *domain, + struct device *dev, ioasid_t pasid) +{ + struct device_domain_info *info =3D dev_iommu_priv_get(dev); + struct intel_iommu *iommu =3D info->iommu; + + if (!pasid_supported(iommu) || dev_is_real_dma_subdevice(dev)) + return -EOPNOTSUPP; + + return intel_pasid_setup_pass_through(iommu, dev, pasid); +} + +static struct iommu_domain identity_domain =3D { + .type =3D IOMMU_DOMAIN_IDENTITY, + .ops =3D &(const struct iommu_domain_ops) { + .attach_dev =3D identity_domain_attach_dev, + .set_dev_pasid =3D identity_domain_set_dev_pasid, + }, +}; + const struct iommu_ops intel_iommu_ops =3D { .blocked_domain =3D &blocking_domain, .release_domain =3D &blocking_domain, + .identity_domain =3D &identity_domain, .capable =3D intel_iommu_capable, .hw_info =3D intel_iommu_hw_info, .domain_alloc =3D intel_iommu_domain_alloc, --=20 2.34.1 From nobody Thu Dec 18 07:11:54 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8F7A16D9D4 for ; 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X-CSE-ConnectionGUID: FMKmt1XbQzmJr2ECOVsZLw== X-CSE-MsgGUID: yoJirrydR9qOQXFGUlcg+Q== X-IronPort-AV: E=McAfee;i="6700,10204,11158"; a="21469178" X-IronPort-AV: E=Sophos;i="6.09,275,1716274800"; d="scan'208";a="21469178" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2024 22:58:19 -0700 X-CSE-ConnectionGUID: ABrRPWwtTy+x1i0mwY/L+w== X-CSE-MsgGUID: v3x3qcDXQOisvGdbhg23SQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,275,1716274800"; d="scan'208";a="57540949" Received: from allen-box.sh.intel.com ([10.239.159.127]) by fmviesa010.fm.intel.com with ESMTP; 08 Aug 2024 22:58:17 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu , Jason Gunthorpe Subject: [PATCH v4 7/7] iommu/vt-d: Cleanup si_domain Date: Fri, 9 Aug 2024 13:54:31 +0800 Message-Id: <20240809055431.36513-8-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240809055431.36513-1-baolu.lu@linux.intel.com> References: <20240809055431.36513-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The static identity domain has been introduced, rendering the si_domain obsolete. Remove si_domain and cleanup the code accordingly. Reviewed-by: Jason Gunthorpe Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian --- drivers/iommu/intel/iommu.c | 91 ++++++++----------------------------- 1 file changed, 19 insertions(+), 72 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 14f1fcf17152..159da629349c 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -167,8 +167,6 @@ static void device_rbtree_remove(struct device_domain_i= nfo *info) spin_unlock_irqrestore(&iommu->device_rbtree_lock, flags); } =20 -static struct dmar_domain *si_domain; - struct dmar_rmrr_unit { struct list_head list; /* list of rmrr units */ struct acpi_dmar_header *hdr; /* ACPI header */ @@ -286,11 +284,6 @@ static int __init intel_iommu_setup(char *str) } __setup("intel_iommu=3D", intel_iommu_setup); =20 -static int domain_type_is_si(struct dmar_domain *domain) -{ - return domain->domain.type =3D=3D IOMMU_DOMAIN_IDENTITY; -} - static int domain_pfn_supported(struct dmar_domain *domain, unsigned long = pfn) { int addr_width =3D agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; @@ -1664,9 +1657,6 @@ static int domain_context_mapping_one(struct dmar_dom= ain *domain, struct context_entry *context; int agaw, ret; =20 - if (domain_type_is_si(domain)) - translation =3D CONTEXT_TT_PASS_THROUGH; - pr_debug("Set context mapping for %02x:%02x.%d\n", bus, PCI_SLOT(devfn), PCI_FUNC(devfn)); =20 @@ -1685,34 +1675,24 @@ static int domain_context_mapping_one(struct dmar_d= omain *domain, =20 context_set_domain_id(context, did); =20 - if (translation !=3D CONTEXT_TT_PASS_THROUGH) { - /* - * Skip top levels of page tables for iommu which has - * less agaw than default. Unnecessary for PT mode. - */ - for (agaw =3D domain->agaw; agaw > iommu->agaw; agaw--) { - ret =3D -ENOMEM; - pgd =3D phys_to_virt(dma_pte_addr(pgd)); - if (!dma_pte_present(pgd)) - goto out_unlock; - } - - if (info && info->ats_supported) - translation =3D CONTEXT_TT_DEV_IOTLB; - else - translation =3D CONTEXT_TT_MULTI_LEVEL; - - context_set_address_root(context, virt_to_phys(pgd)); - context_set_address_width(context, agaw); - } else { - /* - * In pass through mode, AW must be programmed to - * indicate the largest AGAW value supported by - * hardware. And ASR is ignored by hardware. - */ - context_set_address_width(context, iommu->msagaw); + /* + * Skip top levels of page tables for iommu which has + * less agaw than default. Unnecessary for PT mode. + */ + for (agaw =3D domain->agaw; agaw > iommu->agaw; agaw--) { + ret =3D -ENOMEM; + pgd =3D phys_to_virt(dma_pte_addr(pgd)); + if (!dma_pte_present(pgd)) + goto out_unlock; } =20 + if (info && info->ats_supported) + translation =3D CONTEXT_TT_DEV_IOTLB; + else + translation =3D CONTEXT_TT_MULTI_LEVEL; + + context_set_address_root(context, virt_to_phys(pgd)); + context_set_address_width(context, agaw); context_set_translation_type(context, translation); context_set_fault_enable(context); context_set_present(context); @@ -1977,23 +1957,6 @@ static bool dev_is_real_dma_subdevice(struct device = *dev) pci_real_dma_dev(to_pci_dev(dev)) !=3D to_pci_dev(dev); } =20 -static int md_domain_init(struct dmar_domain *domain, int guest_width); - -static int __init si_domain_init(void) -{ - si_domain =3D alloc_domain(IOMMU_DOMAIN_IDENTITY); - if (!si_domain) - return -EFAULT; - - if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) { - domain_exit(si_domain); - si_domain =3D NULL; - return -EFAULT; - } - - return 0; -} - static int dmar_domain_attach_device(struct dmar_domain *domain, struct device *dev) { @@ -2016,8 +1979,6 @@ static int dmar_domain_attach_device(struct dmar_doma= in *domain, =20 if (!sm_supported(iommu)) ret =3D domain_context_mapping(domain, dev); - else if (domain_type_is_si(domain)) - ret =3D intel_pasid_setup_pass_through(iommu, dev, IOMMU_NO_PASID); else if (domain->use_first_level) ret =3D domain_setup_first_level(iommu, domain, dev, IOMMU_NO_PASID); else @@ -2026,8 +1987,7 @@ static int dmar_domain_attach_device(struct dmar_doma= in *domain, if (ret) goto out_block_translation; =20 - if (sm_supported(info->iommu) || !domain_type_is_si(info->domain)) - iommu_enable_pci_caps(info); + iommu_enable_pci_caps(info); =20 ret =3D cache_tag_assign_domain(domain, dev, IOMMU_NO_PASID); if (ret) @@ -2386,10 +2346,6 @@ static int __init init_dmars(void) =20 check_tylersburg_isoch(); =20 - ret =3D si_domain_init(); - if (ret) - goto free_iommu; - /* * for each drhd * enable fault log @@ -2435,10 +2391,6 @@ static int __init init_dmars(void) disable_dmar_iommu(iommu); free_dmar_iommu(iommu); } - if (si_domain) { - domain_exit(si_domain); - si_domain =3D NULL; - } =20 return ret; } @@ -3572,8 +3524,6 @@ static struct iommu_domain *intel_iommu_domain_alloc(= unsigned type) domain->geometry.force_aperture =3D true; =20 return domain; - case IOMMU_DOMAIN_IDENTITY: - return &si_domain->domain; default: return NULL; } @@ -3640,8 +3590,7 @@ static void intel_iommu_domain_free(struct iommu_doma= in *domain) =20 WARN_ON(dmar_domain->nested_parent && !list_empty(&dmar_domain->s1_domains)); - if (domain !=3D &si_domain->domain) - domain_exit(dmar_domain); + domain_exit(dmar_domain); } =20 int prepare_domain_attach_device(struct iommu_domain *domain, @@ -4364,9 +4313,7 @@ static int intel_iommu_set_dev_pasid(struct iommu_dom= ain *domain, if (ret) goto out_detach_iommu; =20 - if (domain_type_is_si(dmar_domain)) - ret =3D intel_pasid_setup_pass_through(iommu, dev, pasid); - else if (dmar_domain->use_first_level) + if (dmar_domain->use_first_level) ret =3D domain_setup_first_level(iommu, dmar_domain, dev, pasid); else --=20 2.34.1