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Fri, 9 Aug 2024 17:01:18 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 9 Aug 2024 17:01:18 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 9 Aug 2024 17:01:18 -0500 Received: from localhost (bb.dhcp.ti.com [128.247.81.12]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 479M1IJk110316; Fri, 9 Aug 2024 17:01:18 -0500 From: Bryan Brattlof Date: Fri, 9 Aug 2024 17:01:14 -0500 Subject: [PATCH 2/2] arm64: dts: ti: k3-am62p: add opp frequencies Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240809-opp-v1-2-fea8efeaf963@ti.com> References: <20240809-opp-v1-0-fea8efeaf963@ti.com> In-Reply-To: <20240809-opp-v1-0-fea8efeaf963@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Bryan Brattlof X-Mailer: b4 0.13.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Add OPP table for the am62px-sk allowing us to slow down CPUs when idle Signed-off-by: Bryan Brattlof --- .../boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi | 5 +++ arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 9 +++++ arch/arm64/boot/dts/ti/k3-am62p5.dtsi | 47 ++++++++++++++++++= ++++ 3 files changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi b/arc= h/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi index 315d0092e7366..6f32135f00a55 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi @@ -20,6 +20,11 @@ chipid: chipid@14 { bootph-all; }; =20 + opp_efuse_table: syscon@18 { + compatible =3D "ti,am62-opp-efuse-table", "syscon"; + reg =3D <0x18 0x4>; + }; + cpsw_mac_syscon: ethernet-mac-syscon@200 { compatible =3D "ti,am62p-cpsw-mac-efuse", "syscon"; reg =3D <0x200 0x8>; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62p5-sk.dts index ff65955551a32..ab5d7a5fc6118 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -128,6 +128,15 @@ led-0 { }; }; =20 + opp-table { + /* Requires VDD_CORE at 0v85 */ + opp-1400000000 { + opp-hz =3D /bits/ 64 <1400000000>; + opp-supported-hw =3D <0x01 0x0004>; + clock-latency-ns =3D <6000000>; + }; + }; + tlv320_mclk: clk-0 { #clock-cells =3D <0>; compatible =3D "fixed-clock"; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi b/arch/arm64/boot/dts/ti= /k3-am62p5.dtsi index 41f479dca4555..140587d02e88e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi @@ -47,6 +47,7 @@ cpu0: cpu@0 { d-cache-line-size =3D <64>; d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; + operating-points-v2 =3D <&a53_opp_table>; clocks =3D <&k3_clks 135 0>; }; =20 @@ -62,6 +63,7 @@ cpu1: cpu@1 { d-cache-line-size =3D <64>; d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; + operating-points-v2 =3D <&a53_opp_table>; clocks =3D <&k3_clks 136 0>; }; =20 @@ -77,6 +79,7 @@ cpu2: cpu@2 { d-cache-line-size =3D <64>; d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; + operating-points-v2 =3D <&a53_opp_table>; clocks =3D <&k3_clks 137 0>; }; =20 @@ -92,10 +95,54 @@ cpu3: cpu@3 { d-cache-line-size =3D <64>; d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; + operating-points-v2 =3D <&a53_opp_table>; clocks =3D <&k3_clks 138 0>; }; }; =20 + a53_opp_table: opp-table { + compatible =3D "operating-points-v2-ti-cpu"; + opp-shared; + syscon =3D <&opp_efuse_table>; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + opp-supported-hw =3D <0x01 0x0007>; + clock-latency-ns =3D <6000000>; + }; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + opp-supported-hw =3D <0x01 0x0007>; + clock-latency-ns =3D <6000000>; + }; + + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + opp-supported-hw =3D <0x01 0x0007>; + clock-latency-ns =3D <6000000>; + }; + + opp-800000000 { + opp-hz =3D /bits/ 64 <800000000>; + opp-supported-hw =3D <0x01 0x0007>; + clock-latency-ns =3D <6000000>; + }; + + opp-1000000000 { + opp-hz =3D /bits/ 64 <1000000000>; + opp-supported-hw =3D <0x01 0x0006>; + clock-latency-ns =3D <6000000>; + }; + + opp-1250000000 { + opp-hz =3D /bits/ 64 <1250000000>; + opp-supported-hw =3D <0x01 0x0004>; + clock-latency-ns =3D <6000000>; + opp-suspend; + }; + }; + l2_0: l2-cache0 { compatible =3D "cache"; cache-unified; --=20 2.45.2