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[24.150.219.207]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4531c1d723asm370381cf.44.2024.08.09.11.41.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Aug 2024 11:41:19 -0700 (PDT) From: Trevor Gamblin Date: Fri, 09 Aug 2024 14:41:10 -0400 Subject: [PATCH v2 3/3] docs: iio: new docs for ad7625 driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240809-ad7625_r1-v2-3-f85e7ac83150@baylibre.com> References: <20240809-ad7625_r1-v2-0-f85e7ac83150@baylibre.com> In-Reply-To: <20240809-ad7625_r1-v2-0-f85e7ac83150@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , David Lechner , Uwe Kleine-Konig Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Trevor Gamblin X-Mailer: b4 0.14.1 Add documentation for the AD7625/AD7626/AD7960/AD7961 ADCs. Signed-off-by: Trevor Gamblin --- Documentation/iio/ad7625.rst | 91 ++++++++++++++++++++++++++++++++++++++++= ++++ MAINTAINERS | 1 + 2 files changed, 92 insertions(+) diff --git a/Documentation/iio/ad7625.rst b/Documentation/iio/ad7625.rst new file mode 100644 index 000000000000..61761e3b75c3 --- /dev/null +++ b/Documentation/iio/ad7625.rst @@ -0,0 +1,91 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +AD7625 driver +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +ADC driver for Analog Devices Inc. AD7625, AD7626, AD7960, and AD7961 +devices. The module name is ``ad7625``. + +Supported devices +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The following chips are supported by this driver: + +* `AD7625 `_ +* `AD7626 `_ +* `AD7960 `_ +* `AD7961 `_ + +The driver requires use of the Pulsar LVDS HDL project: + +* `Pulsar LVDS HDL `_ + +To trigger conversions and enable subsequent data transfer, the devices +require coupled PWM signals with a phase offset. + +Supported features +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Conversion control modes +------------------------ + +The driver currently supports one of two possible LVDS conversion control = methods. + +Echoed-Clock interface mode +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. code-block:: + + +----------------+ + +xxxxxxxxxxxxxxxxxxxxxxxxxx| CNV | + X | | + v | HOST | + +----------------------------+ | | + | CNV+/CNV- DCO+/DCO- |xxxxxxx>| CLK_IN | + | | | | + | | | | + | AD7625 D+/D- |xxxxxxx>| DATA_IN | + | | | | + | | | | + | CLK+/CLK- |