From nobody Sat Feb 7 15:22:14 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E238188CA7 for ; Thu, 8 Aug 2024 07:47:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723103277; cv=none; b=YYcg3gWsxAl5huaF159v59I17TKq8y/xtiRzcw4xhig+xLlGnvoorpLpZYWaNX71Ifj4Amj1YoLnaYFQiq9lP9kfr1N3Zb6WS6Cqdyn3z2sLoFUW5OzFuHDX2WZJhR5IqUdMfOrLfh5Ay0v1rFW2jX1ksuuXLWJ8mWxK84z2m9Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723103277; c=relaxed/simple; bh=kRefNyGkY58doqRLS+Q3D+2QDtqbzSeMiWn5qKzcAFA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Cgcz9OLDX72jBI5qQB32Wyqxgysn54pdlSzhTZ2wKBwt1bseB3I3jmq1SAFH1pKeJgYPZBGCtNbUtc9HR4bK6NFJbwEr7LgFrAetD9AYbVtCRBjLEn049XDAMceZjCSlhGqz0yyngy2Qx3+/RUpNSoimldJcBOJuwJIJ8eWMg7s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YVZbyA0L; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YVZbyA0L" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1723103275; x=1754639275; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kRefNyGkY58doqRLS+Q3D+2QDtqbzSeMiWn5qKzcAFA=; b=YVZbyA0LAWVVKKESfB0Lmtyxx5C+5ckAV4PlDxs7XZQunuTAZfOWOxuG ZAbV062q4uj7D/Ku8PCDocGxomHyykKPY/1djKOXcoITbZpmxWhhcpH6y 5RDap9smn13TaR/yMlthEv5KnF9DS1gygwb/lOAqafaLghknuztp1PLhI 0uID1eit9wO9xhPjaI1bUzJhD+mWYgOe1AbnVk6A4L+76jyPSFVIiyD2O iJ+VB/qsVbP6CS94610hVpq1YEWsJPM/kLXzwYraIZvZKEMUGd5xUf/cH qp5jZnYJQp1sZbKKPiLU6HBmY2SPT+SeR9s5h73O3RJ0Gn6VoOD0N2FTE g==; X-CSE-ConnectionGUID: fUFfFmb6RxqzJfp4j/RuRw== X-CSE-MsgGUID: Xy61wjYeTdiskhIgCAY7lg== X-IronPort-AV: E=McAfee;i="6700,10204,11157"; a="38720978" X-IronPort-AV: E=Sophos;i="6.09,272,1716274800"; d="scan'208";a="38720978" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2024 00:47:55 -0700 X-CSE-ConnectionGUID: Sh2Szmc/R2K0jeZyEtVSjw== X-CSE-MsgGUID: 7RKhpyrNQlyYysawyexD4w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,272,1716274800"; d="scan'208";a="57090931" Received: from emr.sh.intel.com ([10.112.229.56]) by fmviesa009.fm.intel.com with ESMTP; 08 Aug 2024 00:47:52 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Kan Liang Cc: linux-kernel@vger.kernel.org, Andi Kleen , Zhenyu Wang , Yongwei Ma , Pawan Gupta , Dapeng Mi , Dapeng Mi Subject: [PATCH 1/4] perf/x86: Refine hybrid_pmu_type defination Date: Thu, 8 Aug 2024 14:02:07 +0000 Message-Id: <20240808140210.1666783-2-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240808140210.1666783-1-dapeng1.mi@linux.intel.com> References: <20240808140210.1666783-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use macros instead of magic number to define hybrid_pmu_type and remove X86_HYBRID_NUM_PMUS since it's never used. Signed-off-by: Dapeng Mi Tested-by: Yongwei Ma Reviewed-by: Kan Liang --- arch/x86/events/perf_event.h | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index ac1182141bf6..5d1677844e04 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -674,19 +674,16 @@ enum hybrid_cpu_type { HYBRID_INTEL_CORE =3D 0x40, }; =20 +#define X86_HYBRID_PMU_ATOM_IDX 0 +#define X86_HYBRID_PMU_CORE_IDX 1 enum hybrid_pmu_type { not_hybrid, - hybrid_small =3D BIT(0), - hybrid_big =3D BIT(1), + hybrid_small =3D BIT(X86_HYBRID_PMU_ATOM_IDX), + hybrid_big =3D BIT(X86_HYBRID_PMU_CORE_IDX), =20 hybrid_big_small =3D hybrid_big | hybrid_small, /* only used for matching= */ }; =20 -#define X86_HYBRID_PMU_ATOM_IDX 0 -#define X86_HYBRID_PMU_CORE_IDX 1 - -#define X86_HYBRID_NUM_PMUS 2 - struct x86_hybrid_pmu { struct pmu pmu; const char *name; --=20 2.40.1 From nobody Sat Feb 7 15:22:14 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4DBF1891A3 for ; Thu, 8 Aug 2024 07:47:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723103280; cv=none; b=BfBCFPtuwEQCZgjG1k9sgy9yUxrkUgsDzZyHG3BPYI8a+mu3iduf8g541zKzUDoRdVLf810CHhNmupYWMdBE3VSkoAHDLOWIkIPAMb/pfunNIIzgSpXbViz/JEDMQQXORXoxW/CqvhOYKpEQXiJkRVmHxAgSIX3DX38UM2FmHcc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723103280; c=relaxed/simple; bh=pqZfyJTJ1/8PqnS8FcutnA0VtCKDLURR0MjAxPAGrxw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=JIsODF15fVj5CpQ2Aqi+Q7dNoNzDR4jtnxN2qae8YqUFsvGhbZnpa/FdgBXF4RiFYE3KvA+sh+AN96gpeAn2W0t28+0OHXqtTwUvEcfmExrOYPAb69uNKVHHtxKWFOj6iGNyHYYkNFsI0fMH3/pv/L+5L65ZOKkeRXVZes2W+EY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Z7AzptOk; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Z7AzptOk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1723103279; x=1754639279; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pqZfyJTJ1/8PqnS8FcutnA0VtCKDLURR0MjAxPAGrxw=; b=Z7AzptOkj/E9n8gOsDKi6UJUpo3VJ7c2Jc71a9fyutJRXTQW9h3eUHGc IS127Dfq9qHvbmgU710fTS33GFeeO7+fymHteAZlFJc/BGSrJ0N+omhv5 riourjep6z8pam3DpxM+6ZaBtEUzXpwM1WNLw2tTUqW8P1oS6RDjT0IBh 1hqHujNwiQBYd6HL9TXS84zDYFfWkXW36j6/qkpgp5LTe37hpejR+KTdE w1YBkNBL7pg0SBHryOOZ2woNRLjc0zu+HuzTbdWwb5KBlGSMGG7EyN8eJ voXA7SNZoOukK7zhLNW24yPIsFomhl6VKnzBgCMHyWkrooFgAdZnGPhIB A==; X-CSE-ConnectionGUID: EgOqTOLlQ4agufuqFFO8mQ== X-CSE-MsgGUID: 58oYlVJ/RmmgNal/NznrHA== X-IronPort-AV: E=McAfee;i="6700,10204,11157"; a="38720986" X-IronPort-AV: E=Sophos;i="6.09,272,1716274800"; d="scan'208";a="38720986" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2024 00:47:58 -0700 X-CSE-ConnectionGUID: n2RKBaqoQ7ikYA9eOH6l/A== X-CSE-MsgGUID: EEEmD7DnQZ2Q5wQRIVUUeQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,272,1716274800"; d="scan'208";a="57090937" Received: from emr.sh.intel.com ([10.112.229.56]) by fmviesa009.fm.intel.com with ESMTP; 08 Aug 2024 00:47:56 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Kan Liang Cc: linux-kernel@vger.kernel.org, Andi Kleen , Zhenyu Wang , Yongwei Ma , Pawan Gupta , Dapeng Mi , Dapeng Mi Subject: [PATCH 2/4] x86/cpu/intel: Define helper to get CPU core native ID Date: Thu, 8 Aug 2024 14:02:08 +0000 Message-Id: <20240808140210.1666783-3-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240808140210.1666783-1-dapeng1.mi@linux.intel.com> References: <20240808140210.1666783-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define helper get_this_hybrid_cpu_native_id() to return the CPU core native ID. This core native ID combining with core type can be used to figure out the CPU core uarch uniquely. Signed-off-by: Dapeng Mi Tested-by: Yongwei Ma Reviewed-by: Kan Liang --- arch/x86/include/asm/cpu.h | 6 ++++++ arch/x86/kernel/cpu/intel.c | 15 +++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index aa30fd8cad7f..5af69b5be2fb 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -32,6 +32,7 @@ extern bool handle_user_split_lock(struct pt_regs *regs, = long error_code); extern bool handle_guest_split_lock(unsigned long ip); extern void handle_bus_lock(struct pt_regs *regs); u8 get_this_hybrid_cpu_type(void); +u32 get_this_hybrid_cpu_native_id(void); #else static inline void __init sld_setup(struct cpuinfo_x86 *c) {} static inline bool handle_user_split_lock(struct pt_regs *regs, long error= _code) @@ -50,6 +51,11 @@ static inline u8 get_this_hybrid_cpu_type(void) { return 0; } + +static inline u32 get_this_hybrid_cpu_native_id(void) +{ + return 0; +} #endif #ifdef CONFIG_IA32_FEAT_CTL void init_ia32_feat_ctl(struct cpuinfo_x86 *c); diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 08b95a35b5cb..dbc457626207 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -1297,3 +1297,18 @@ u8 get_this_hybrid_cpu_type(void) =20 return cpuid_eax(0x0000001a) >> X86_HYBRID_CPU_TYPE_ID_SHIFT; } + +/** + * get_this_hybrid_cpu_native_id() - Get the native id of this hybrid CPU + * + * Returns the uarch native ID [23:0] of a CPU in a hybrid processor. + * If the processor is not hybrid, returns 0. + */ +u32 get_this_hybrid_cpu_native_id(void) +{ + if (!cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) + return 0; + + return cpuid_eax(0x0000001a) & + (BIT_ULL(X86_HYBRID_CPU_TYPE_ID_SHIFT) - 1); +} --=20 2.40.1 From nobody Sat Feb 7 15:22:14 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 556D51891CF for ; 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charset="utf-8" The upcoming ARL-H hybrid processor contains 2 different atom uarchs which have different PMU capabilities. To distinguish these atom uarchs, CPUID.1AH.EAX[23:0] defines a native model ID which can be used to uniquely identify the uarch of the core by combining with core type. Thus a 3rd hybrid pmu type "hybrid_small2" is defined to mark the 2nd atom uarch. The helper find_hybrid_pmu_for_cpu() would compare the hybrid pmu type and dynamically read core native id from cpu to identify the corresponding hybrid pmu structure. Signed-off-by: Dapeng Mi Tested-by: Yongwei Ma Reviewed-by: Kan Liang --- arch/x86/events/intel/core.c | 24 +++++++++++++++++------- arch/x86/events/perf_event.h | 18 +++++++++++++++++- 2 files changed, 34 insertions(+), 8 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 0c9c2706d4ec..b6429bc009c0 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4902,17 +4902,26 @@ static struct x86_hybrid_pmu *find_hybrid_pmu_for_c= pu(void) =20 /* * This essentially just maps between the 'hybrid_cpu_type' - * and 'hybrid_pmu_type' enums: + * and 'hybrid_pmu_type' enums except for ARL-H processor + * which needs to compare atom uarch native id since ARL-H + * contains two different atom uarchs. */ for (i =3D 0; i < x86_pmu.num_hybrid_pmus; i++) { enum hybrid_pmu_type pmu_type =3D x86_pmu.hybrid_pmu[i].pmu_type; + u32 native_id; =20 - if (cpu_type =3D=3D HYBRID_INTEL_CORE && - pmu_type =3D=3D hybrid_big) - return &x86_pmu.hybrid_pmu[i]; - if (cpu_type =3D=3D HYBRID_INTEL_ATOM && - pmu_type =3D=3D hybrid_small) + if (cpu_type =3D=3D HYBRID_INTEL_CORE && pmu_type =3D=3D hybrid_big) return &x86_pmu.hybrid_pmu[i]; + if (cpu_type =3D=3D HYBRID_INTEL_ATOM) { + if (x86_pmu.num_hybrid_pmus =3D=3D 2 && pmu_type =3D=3D hybrid_small) + return &x86_pmu.hybrid_pmu[i]; + + native_id =3D get_this_hybrid_cpu_native_id(); + if (native_id =3D=3D skt_native_id && pmu_type =3D=3D hybrid_small) + return &x86_pmu.hybrid_pmu[i]; + if (native_id =3D=3D cmt_native_id && pmu_type =3D=3D hybrid_small2) + return &x86_pmu.hybrid_pmu[i]; + } } =20 return NULL; @@ -6218,6 +6227,7 @@ static inline int intel_pmu_v6_addr_offset(int index,= bool eventsel) static const struct { enum hybrid_pmu_type id; char *name; } intel_hybrid_= pmu_type_map[] __initconst =3D { { hybrid_small, "cpu_atom" }, { hybrid_big, "cpu_core" }, + { hybrid_small2, "cpu_atom2" }, }; =20 static __always_inline int intel_pmu_init_hybrid(enum hybrid_pmu_type pmus) @@ -6250,7 +6260,7 @@ static __always_inline int intel_pmu_init_hybrid(enum= hybrid_pmu_type pmus) 0, x86_pmu_num_counters(&pmu->pmu), 0, 0); =20 pmu->intel_cap.capabilities =3D x86_pmu.intel_cap.capabilities; - if (pmu->pmu_type & hybrid_small) { + if (pmu->pmu_type & hybrid_small_all) { pmu->intel_cap.perf_metrics =3D 0; pmu->intel_cap.pebs_output_pt_available =3D 1; pmu->mid_ack =3D true; diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 5d1677844e04..f7b55c909eff 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -668,6 +668,13 @@ enum { #define PERF_PEBS_DATA_SOURCE_GRT_MAX 0x10 #define PERF_PEBS_DATA_SOURCE_GRT_MASK (PERF_PEBS_DATA_SOURCE_GRT_MAX - 1) =20 + +/* + * CPUID.1AH.EAX[31:0] uniquely identifies the microarchitecture + * of the core. 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It is different with previous hybrid processors which only contains two kinds of uarchs. This patch adds PMU support for ArrowLake-H processor, adds ARL-H specific events which supports the 3 kinds of uarchs, such as td_retiring_arl_h, and extends some existed format attributes like offcore_rsp to make them be available to support ARL-H as well. Althrough these format attributes like offcore_rsp have been extended to support ARL-H, they can still support the regular hybrid platforms with 2 kinds of uarchs since the helper hybrid_format_is_visible() would filter PMU types and only show the format attribute for available PMUs. Signed-off-by: Dapeng Mi Tested-by: Yongwei Ma Reviewed-by: Kan Liang --- arch/x86/events/intel/core.c | 105 ++++++++++++++++++++++++++++++++++- arch/x86/events/intel/ds.c | 21 +++++++ arch/x86/events/perf_event.h | 4 ++ 3 files changed, 127 insertions(+), 3 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index b6429bc009c0..72836bb05387 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4589,6 +4589,28 @@ static enum hybrid_cpu_type adl_get_hybrid_cpu_type(= void) return HYBRID_INTEL_CORE; } =20 +static struct event_constraint * +arl_h_get_event_constraints(struct cpu_hw_events *cpuc, int idx, + struct perf_event *event) +{ + struct x86_hybrid_pmu *pmu =3D hybrid_pmu(event->pmu); + + if (pmu->pmu_type =3D=3D hybrid_small2) + return cmt_get_event_constraints(cpuc, idx, event); + + return mtl_get_event_constraints(cpuc, idx, event); +} + +static int arl_h_hw_config(struct perf_event *event) +{ + struct x86_hybrid_pmu *pmu =3D hybrid_pmu(event->pmu); + + if (pmu->pmu_type =3D=3D hybrid_small2) + return intel_pmu_hw_config(event); + + return adl_hw_config(event); +} + /* * Broadwell: * @@ -5952,6 +5974,37 @@ static struct attribute *lnl_hybrid_events_attrs[] = =3D { NULL }; =20 +/* The event string must be in PMU IDX order. */ +EVENT_ATTR_STR_HYBRID(topdown-retiring, + td_retiring_arl_h, + "event=3D0xc2,umask=3D0x02;event=3D0x00,umask=3D0x80;event=3D0xc2,= umask=3D0x0", + hybrid_big_small_arl_h); +EVENT_ATTR_STR_HYBRID(topdown-bad-spec, + td_bad_spec_arl_h, + "event=3D0x73,umask=3D0x0;event=3D0x00,umask=3D0x81;event=3D0x73,u= mask=3D0x0", + hybrid_big_small_arl_h); +EVENT_ATTR_STR_HYBRID(topdown-fe-bound, + td_fe_bound_arl_h, + "event=3D0x9c,umask=3D0x01;event=3D0x00,umask=3D0x82;event=3D0x71,= umask=3D0x0", + hybrid_big_small_arl_h); +EVENT_ATTR_STR_HYBRID(topdown-be-bound, + td_be_bound_arl_h, + "event=3D0xa4,umask=3D0x02;event=3D0x00,umask=3D0x83;event=3D0x74,= umask=3D0x0", + hybrid_big_small_arl_h); + +static struct attribute *arl_h_hybrid_events_attrs[] =3D { + EVENT_PTR(slots_adl), + EVENT_PTR(td_retiring_arl_h), + EVENT_PTR(td_bad_spec_arl_h), + EVENT_PTR(td_fe_bound_arl_h), + EVENT_PTR(td_be_bound_arl_h), + EVENT_PTR(td_heavy_ops_adl), + EVENT_PTR(td_br_mis_adl), + EVENT_PTR(td_fetch_lat_adl), + EVENT_PTR(td_mem_bound_adl), + NULL, +}; + /* Must be in IDX order */ EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=3D0xd0,umask= =3D0x5,ldlat=3D3;event=3D0xcd,umask=3D0x1,ldlat=3D3", hybrid_big_small); EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=3D0xd0,umask= =3D0x6;event=3D0xcd,umask=3D0x2", hybrid_big_small); @@ -5970,6 +6023,21 @@ static struct attribute *mtl_hybrid_mem_attrs[] =3D { NULL }; =20 +EVENT_ATTR_STR_HYBRID(mem-loads, + mem_ld_arl_h, + "event=3D0xd0,umask=3D0x5,ldlat=3D3;event=3D0xcd,umask=3D0x1,ldlat= =3D3;event=3D0xd0,umask=3D0x5,ldlat=3D3", + hybrid_big_small_arl_h); +EVENT_ATTR_STR_HYBRID(mem-stores, + mem_st_arl_h, + "event=3D0xd0,umask=3D0x6;event=3D0xcd,umask=3D0x2;event=3D0xd0,um= ask=3D0x6", + hybrid_big_small_arl_h); + +static struct attribute *arl_h_hybrid_mem_attrs[] =3D { + EVENT_PTR(mem_ld_arl_h), + EVENT_PTR(mem_st_arl_h), + NULL, +}; + EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=3D0= xc9,umask=3D0x1", hybrid_big); EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=3D0= xc9,umask=3D0x2", hybrid_big); EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=3D0= xc9,umask=3D0x4", hybrid_big); @@ -5993,8 +6061,8 @@ static struct attribute *adl_hybrid_tsx_attrs[] =3D { =20 FORMAT_ATTR_HYBRID(in_tx, hybrid_big); FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big); -FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small); -FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small); +FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small_arl_h); +FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small_arl_h); FORMAT_ATTR_HYBRID(frontend, hybrid_big); =20 #define ADL_HYBRID_RTM_FORMAT_ATTR \ @@ -6017,7 +6085,7 @@ static struct attribute *adl_hybrid_extra_attr[] =3D { NULL }; =20 -FORMAT_ATTR_HYBRID(snoop_rsp, hybrid_small); +FORMAT_ATTR_HYBRID(snoop_rsp, hybrid_small_all); =20 static struct attribute *mtl_hybrid_extra_attr_rtm[] =3D { ADL_HYBRID_RTM_FORMAT_ATTR, @@ -7098,6 +7166,37 @@ __init int intel_pmu_init(void) name =3D "lunarlake_hybrid"; break; =20 + case INTEL_ARROWLAKE_H: + intel_pmu_init_hybrid(hybrid_big_small_arl_h); + + x86_pmu.pebs_latency_data =3D arl_h_latency_data; + x86_pmu.get_event_constraints =3D arl_h_get_event_constraints; + x86_pmu.hw_config =3D arl_h_hw_config; + + td_attr =3D arl_h_hybrid_events_attrs; + mem_attr =3D arl_h_hybrid_mem_attrs; + tsx_attr =3D adl_hybrid_tsx_attrs; + extra_attr =3D boot_cpu_has(X86_FEATURE_RTM) ? + mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; + + /* Initialize big core specific PerfMon capabilities.*/ + pmu =3D &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; + intel_pmu_init_lnc(&pmu->pmu); + + /* Initialize Atom core specific PerfMon capabilities.*/ + pmu =3D &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; + intel_pmu_init_skt(&pmu->pmu); + + /* Initialize Atom2 core specific PerfMon capabilities.*/ + pmu =3D &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM2_IDX]; + intel_pmu_init_grt(&pmu->pmu); + pmu->extra_regs =3D intel_cmt_extra_regs; + + intel_pmu_pebs_data_source_arl_h(); + pr_cont("ArrowLake-H Hybrid events, "); + name =3D "arrowlake_h_hybrid"; + break; + default: switch (x86_pmu.version) { case 1: diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index fa5ea65de0d0..64242a8ffaf1 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -177,6 +177,17 @@ void __init intel_pmu_pebs_data_source_mtl(void) __intel_pmu_pebs_data_source_cmt(data_source); } =20 +void __init intel_pmu_pebs_data_source_arl_h(void) +{ + u64 *data_source; + + intel_pmu_pebs_data_source_lnl(); + + data_source =3D x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM2_IDX].pebs_data_so= urce; + memcpy(data_source, pebs_data_source, sizeof(pebs_data_source)); + __intel_pmu_pebs_data_source_cmt(data_source); +} + void __init intel_pmu_pebs_data_source_cmt(void) { __intel_pmu_pebs_data_source_cmt(pebs_data_source); @@ -388,6 +399,16 @@ u64 lnl_latency_data(struct perf_event *event, u64 sta= tus) return lnc_latency_data(event, status); } =20 +u64 arl_h_latency_data(struct perf_event *event, u64 status) +{ + struct x86_hybrid_pmu *pmu =3D hybrid_pmu(event->pmu); + + if (pmu->pmu_type =3D=3D hybrid_small2) + return cmt_latency_data(event, status); + + return lnl_latency_data(event, status); +} + static u64 load_latency_data(struct perf_event *event, u64 status) { union intel_x86_pebs_dse dse; diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index f7b55c909eff..32fcbdb464e2 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -1591,6 +1591,8 @@ u64 cmt_latency_data(struct perf_event *event, u64 st= atus); =20 u64 lnl_latency_data(struct perf_event *event, u64 status); =20 +u64 arl_h_latency_data(struct perf_event *event, u64 status); + extern struct event_constraint intel_core2_pebs_event_constraints[]; =20 extern struct event_constraint intel_atom_pebs_event_constraints[]; @@ -1710,6 +1712,8 @@ void intel_pmu_pebs_data_source_grt(void); =20 void intel_pmu_pebs_data_source_mtl(void); =20 +void intel_pmu_pebs_data_source_arl_h(void); + void intel_pmu_pebs_data_source_cmt(void); =20 void intel_pmu_pebs_data_source_lnl(void); --=20 2.40.1