From nobody Fri Dec 19 20:34:17 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4031E3BB50 for ; Tue, 6 Aug 2024 02:43:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722912209; cv=none; b=bnWpStnaVHfVbBzaFsiGoXjh4ooxUNJSDR7OQ0P4gceGgNcRYYZ1+VjP+8G7QxKzPHufuMvb0vpJ1iBKnV8CpJIrLA3L7W+L0qQwmVLwnxXqq0ELvvbAd7WG/XHbodyrSEYdUvii0SuAszdMHTNduWo59MSoCVbZ2DF41+wRIn0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722912209; c=relaxed/simple; bh=AkE4086whaLRTFuL6aoncvEZZjAKqwpJvgyU/lowk4M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=R2lfOB6W7y2Syb3a4wbzjBSwwqc53w6+lzgirGTYFnihNjd7VMVBYqznDvxc6jFo6zJFEQcOet0WN1l9TIHTGFW/v7O2UoW1+uKcogb7L0lJrcAoe+X8k9pJ6P7PFX1h0+ujVN+RJx903o1Ls8kFoYIveqH5FsuUnwALLs32lTM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=dUDvx0vs; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="dUDvx0vs" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1722912208; x=1754448208; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AkE4086whaLRTFuL6aoncvEZZjAKqwpJvgyU/lowk4M=; b=dUDvx0vs2XbM14BKY0wxH9XW2APUF1/mWFIwVY5KRA0V8+BX3VcqOkgt xuSvK0QJGAHLJIj4x+wEQ0VM9cI6a2qxomrtNyMhfD+W41rj+2NLzf6cy RRyZYbNX9ECXQkaTG7Hd1Qjuc0JdyDMsVxHZlRLMPCJBcl5GMQ7XgEdh6 gexDcTzKaWe5URdyJ8c8jcE4FWiSRqSCrKqeMMfIyLPWG8Z7dX/JzB/Vb Wl5/btb4UIxR/zYQJvaxHBWAyWxlPyMCCgmL6HZKcnn9+W/ZofbJshlxj 3my6RY/rTFelloHWj0Lp/zWSaPOYZiqUqCw5TnjMuu/KrzJyzsHK6zyaP Q==; X-CSE-ConnectionGUID: YMBY9SPMTrm60pZizftrpg== X-CSE-MsgGUID: AYKK4SiWSDu/CDaOYVD3Vw== X-IronPort-AV: E=McAfee;i="6700,10204,11155"; a="20756303" X-IronPort-AV: E=Sophos;i="6.09,266,1716274800"; d="scan'208";a="20756303" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2024 19:43:28 -0700 X-CSE-ConnectionGUID: QsNztapJRJa+zIBa+MtJqg== X-CSE-MsgGUID: gAeYOZrjRpOeRIKrONoyBA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,266,1716274800"; d="scan'208";a="56572543" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orviesa006.jf.intel.com with ESMTP; 05 Aug 2024 19:43:26 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v3 7/7] iommu/vt-d: Cleanup si_domain Date: Tue, 6 Aug 2024 10:39:41 +0800 Message-Id: <20240806023941.93454-8-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240806023941.93454-1-baolu.lu@linux.intel.com> References: <20240806023941.93454-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The static identity domain has been introduced, rendering the si_domain obsolete. Remove si_domain and cleanup the code accordingly. Signed-off-by: Lu Baolu Reviewed-by: Jason Gunthorpe --- drivers/iommu/intel/iommu.c | 91 ++++++++----------------------------- 1 file changed, 19 insertions(+), 72 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 9e7b4159e53f..8f8dce602c86 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -167,8 +167,6 @@ static void device_rbtree_remove(struct device_domain_i= nfo *info) spin_unlock_irqrestore(&iommu->device_rbtree_lock, flags); } =20 -static struct dmar_domain *si_domain; - struct dmar_rmrr_unit { struct list_head list; /* list of rmrr units */ struct acpi_dmar_header *hdr; /* ACPI header */ @@ -286,11 +284,6 @@ static int __init intel_iommu_setup(char *str) } __setup("intel_iommu=3D", intel_iommu_setup); =20 -static int domain_type_is_si(struct dmar_domain *domain) -{ - return domain->domain.type =3D=3D IOMMU_DOMAIN_IDENTITY; -} - static int domain_pfn_supported(struct dmar_domain *domain, unsigned long = pfn) { int addr_width =3D agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; @@ -1698,9 +1691,6 @@ static int domain_context_mapping_one(struct dmar_dom= ain *domain, struct context_entry *context; int agaw, ret; =20 - if (domain_type_is_si(domain)) - translation =3D CONTEXT_TT_PASS_THROUGH; - pr_debug("Set context mapping for %02x:%02x.%d\n", bus, PCI_SLOT(devfn), PCI_FUNC(devfn)); =20 @@ -1719,34 +1709,24 @@ static int domain_context_mapping_one(struct dmar_d= omain *domain, =20 context_set_domain_id(context, did); =20 - if (translation !=3D CONTEXT_TT_PASS_THROUGH) { - /* - * Skip top levels of page tables for iommu which has - * less agaw than default. Unnecessary for PT mode. - */ - for (agaw =3D domain->agaw; agaw > iommu->agaw; agaw--) { - ret =3D -ENOMEM; - pgd =3D phys_to_virt(dma_pte_addr(pgd)); - if (!dma_pte_present(pgd)) - goto out_unlock; - } - - if (info && info->ats_supported) - translation =3D CONTEXT_TT_DEV_IOTLB; - else - translation =3D CONTEXT_TT_MULTI_LEVEL; - - context_set_address_root(context, virt_to_phys(pgd)); - context_set_address_width(context, agaw); - } else { - /* - * In pass through mode, AW must be programmed to - * indicate the largest AGAW value supported by - * hardware. And ASR is ignored by hardware. - */ - context_set_address_width(context, iommu->msagaw); + /* + * Skip top levels of page tables for iommu which has + * less agaw than default. Unnecessary for PT mode. + */ + for (agaw =3D domain->agaw; agaw > iommu->agaw; agaw--) { + ret =3D -ENOMEM; + pgd =3D phys_to_virt(dma_pte_addr(pgd)); + if (!dma_pte_present(pgd)) + goto out_unlock; } =20 + if (info && info->ats_supported) + translation =3D CONTEXT_TT_DEV_IOTLB; + else + translation =3D CONTEXT_TT_MULTI_LEVEL; + + context_set_address_root(context, virt_to_phys(pgd)); + context_set_address_width(context, agaw); context_set_translation_type(context, translation); context_set_fault_enable(context); context_set_present(context); @@ -2011,23 +1991,6 @@ static bool dev_is_real_dma_subdevice(struct device = *dev) pci_real_dma_dev(to_pci_dev(dev)) !=3D to_pci_dev(dev); } =20 -static int md_domain_init(struct dmar_domain *domain, int guest_width); - -static int __init si_domain_init(void) -{ - si_domain =3D alloc_domain(IOMMU_DOMAIN_IDENTITY); - if (!si_domain) - return -EFAULT; - - if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) { - domain_exit(si_domain); - si_domain =3D NULL; - return -EFAULT; - } - - return 0; -} - static int dmar_domain_attach_device(struct dmar_domain *domain, struct device *dev) { @@ -2050,8 +2013,6 @@ static int dmar_domain_attach_device(struct dmar_doma= in *domain, =20 if (!sm_supported(iommu)) ret =3D domain_context_mapping(domain, dev); - else if (domain_type_is_si(domain)) - ret =3D intel_pasid_setup_pass_through(iommu, dev, IOMMU_NO_PASID); else if (domain->use_first_level) ret =3D domain_setup_first_level(iommu, domain, dev, IOMMU_NO_PASID); else @@ -2060,8 +2021,7 @@ static int dmar_domain_attach_device(struct dmar_doma= in *domain, if (ret) goto out_block_translation; =20 - if (sm_supported(info->iommu) || !domain_type_is_si(info->domain)) - iommu_enable_pci_caps(info); + iommu_enable_pci_caps(info); =20 ret =3D cache_tag_assign_domain(domain, dev, IOMMU_NO_PASID); if (ret) @@ -2420,10 +2380,6 @@ static int __init init_dmars(void) =20 check_tylersburg_isoch(); =20 - ret =3D si_domain_init(); - if (ret) - goto free_iommu; - /* * for each drhd * enable fault log @@ -2469,10 +2425,6 @@ static int __init init_dmars(void) disable_dmar_iommu(iommu); free_dmar_iommu(iommu); } - if (si_domain) { - domain_exit(si_domain); - si_domain =3D NULL; - } =20 return ret; } @@ -3607,8 +3559,6 @@ static struct iommu_domain *intel_iommu_domain_alloc(= unsigned type) domain->geometry.force_aperture =3D true; =20 return domain; - case IOMMU_DOMAIN_IDENTITY: - return &si_domain->domain; default: return NULL; } @@ -3675,8 +3625,7 @@ static void intel_iommu_domain_free(struct iommu_doma= in *domain) =20 WARN_ON(dmar_domain->nested_parent && !list_empty(&dmar_domain->s1_domains)); - if (domain !=3D &si_domain->domain) - domain_exit(dmar_domain); + domain_exit(dmar_domain); } =20 int prepare_domain_attach_device(struct iommu_domain *domain, @@ -4398,9 +4347,7 @@ static int intel_iommu_set_dev_pasid(struct iommu_dom= ain *domain, if (ret) goto out_detach_iommu; =20 - if (domain_type_is_si(dmar_domain)) - ret =3D intel_pasid_setup_pass_through(iommu, dev, pasid); - else if (dmar_domain->use_first_level) + if (dmar_domain->use_first_level) ret =3D domain_setup_first_level(iommu, dmar_domain, dev, pasid); else --=20 2.34.1