From nobody Fri Dec 19 17:34:21 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59ACDBA34 for ; Tue, 6 Aug 2024 02:43:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722912196; cv=none; b=QeH19kcQMViYSSRbEZ9as5emc5UH7ao61na6sMyh2NHN2KDVxREaGhON69CHO0mxHHEiRhfLnPLbffM93IknBs2xWe0hCmHlr/i9pPiqBfbYz8fb+oS5qwwLezfL28LfOBzoK2B4Qo0mlGAV63GpsItTFiVYwk0ur/6GdM69tR0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722912196; c=relaxed/simple; bh=wv58EET3WPiGTK9JJMk/b9Ols/RUHJCB3khJbO8AXvY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=qhs58P7M+Tsua+dXzzJ9D9sFMj+xw1gClnNWdd/A+Vm9bfOctLzAfg3JbjGT+4m/mIWdQoe7HlQqqp/p1lyoA1GicHT8FOkxCqM+ma4Rpo4RQYf6h2ows95Qkp03Nn/PJPof3s0m1BzKZolp7D5+J7KffKz0bhLc5SnLRkldiaU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=jTj+KJPu; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="jTj+KJPu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1722912194; x=1754448194; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wv58EET3WPiGTK9JJMk/b9Ols/RUHJCB3khJbO8AXvY=; b=jTj+KJPuy4iI4ZqSaK8ekIaIG/ARPeS33azBqezWIkEl6Y+2P/HZAwRW hOhWDWx+Fr40EhuG9X/Hemf8QmydqhtWh7J3jZzzql3pk3yXiDRijGS6Q /CHQxF64SS0oNMPndXLBIep81qVjuB8ex/f+RZO/PBScpq12Qdiw0iM5p GPw/jOp8VzPG4weOBjFmbM/d3+ejhFiCt5xJNz3sKr2GM/YdJzbPpt/2P hyrqNayLc7pe5fz/4YZra4NIXuqQ5cCgWmGWXZuj7SLQB5lWf0yP4MNho iFSOnHZgZ+b0oNTgNr9rFyLM7wRG7cnuGUkDFJYHpZldkP0upfmv2YZgI Q==; X-CSE-ConnectionGUID: t8lI1GszRHWVfwwJxC9z3A== X-CSE-MsgGUID: Z5gnWrZlQkavgwdjhBQDhQ== X-IronPort-AV: E=McAfee;i="6700,10204,11155"; a="20756257" X-IronPort-AV: E=Sophos;i="6.09,266,1716274800"; d="scan'208";a="20756257" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2024 19:43:14 -0700 X-CSE-ConnectionGUID: vuyOKkI0RXKNe1+yQmcZRw== X-CSE-MsgGUID: 87et/yEaTLy55uX7/OMovw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,266,1716274800"; d="scan'208";a="56572515" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orviesa006.jf.intel.com with ESMTP; 05 Aug 2024 19:43:12 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v3 1/7] iommu/vt-d: Require DMA domain if hardware not support passthrough Date: Tue, 6 Aug 2024 10:39:35 +0800 Message-Id: <20240806023941.93454-2-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240806023941.93454-1-baolu.lu@linux.intel.com> References: <20240806023941.93454-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The iommu core defines the def_domain_type callback to query the iommu driver about hardware capability and quirks. The iommu driver should declare IOMMU_DOMAIN_DMA requirement for hardware lacking pass-through capability. Earlier VT-d hardware implementations did not support pass-through translation mode. The iommu driver relied on a paging domain with all physical system memory addresses identically mapped to the same IOVA to simulate pass-through translation before the def_domain_type was introduced and it has been kept until now. It's time to adjust it now to make the Intel iommu driver follow the def_domain_type semantics. Signed-off-by: Lu Baolu Reviewed-by: Jason Gunthorpe Reviewed-by: Jerry Snitselaar --- drivers/iommu/intel/iommu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 9ff8b83c19a3..90ad794a1be7 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -2149,6 +2149,16 @@ static bool device_rmrr_is_relaxable(struct device *= dev) =20 static int device_def_domain_type(struct device *dev) { + struct device_domain_info *info =3D dev_iommu_priv_get(dev); + struct intel_iommu *iommu =3D info->iommu; + + /* + * Hardware does not support the passthrough translation mode. + * Always use a dynamaic mapping domain. + */ + if (!ecap_pass_through(iommu->ecap)) + return IOMMU_DOMAIN_DMA; + if (dev_is_pci(dev)) { struct pci_dev *pdev =3D to_pci_dev(dev); =20 --=20 2.34.1 From nobody Fri Dec 19 17:34:21 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 344B0182C5 for ; Tue, 6 Aug 2024 02:43:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722912199; cv=none; b=ZVVYmo5qMFlNMLyNtvkMSAE+sx2K3nqiomJdSGOHNPwijAGfS0Y4/f8E8SaDuzJrD1I9eh4BX/VYCUEGW6ooKl2/9b5jboP7zNNC2hOl/NghLTrWn81Rlx+pdZlaAX+BxbQw41QiIbBIffFJrwqShwLHwd9jrPBOwcIx4mQAzsk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722912199; c=relaxed/simple; bh=3mh7J7DTz8B/XffYBmV3qV48c2ReihOlXTNT4y/rT1c=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=f7Gj2Dsefu9Nx/UKAryJcgXoyuF+qYRT0TwzdyHK+qloNVaSPCsIJN9fxgQ6tWrx4+ZE9a29MUlde5z1nY11iQuYAAy0gTa3EKgKPuJOmnNfNiqx5IYaaRhNwZAX98IZ6nXr8xBY3f6FiJlc9oSqhKxVEUL2bQVJhiE2FAUAS6Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=mb/lED23; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="mb/lED23" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1722912197; x=1754448197; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3mh7J7DTz8B/XffYBmV3qV48c2ReihOlXTNT4y/rT1c=; b=mb/lED23WkOWOW6NurF5MFpJZFm12el33lClgD/RrRL9By72lv00Lkmh T9NPC2yqH8+RYaxYyE8Ne6eRkB8m/FELzodeagX4u/T6eOdhtP5AZ6PQu dyng8ca0D5bBCHOcJz80gJst+kLT0ZHuhqQGpHuxFDnV9MGI+FqbmJNV4 EjmgGMA7CPcorzmyle3j7fdz+P9rdETRB0e5uoNUqS0GPBykfo+PsyNkw zaPQWcLt4XhRobGDtvsETPr9LXryuD6xWDF3AAhzYd6nKIU+X9Ajw3DLs zVSntS0EkxMFqseAZlUpsM+SYIZUA2GonxWVkS2kYoLDxr9u/7IKS89bg Q==; X-CSE-ConnectionGUID: f8X2d7l9SgyX3ZwU+dr8MQ== X-CSE-MsgGUID: NlJb8EkdQC+yB6LVGsDj0w== X-IronPort-AV: E=McAfee;i="6700,10204,11155"; a="20756267" X-IronPort-AV: E=Sophos;i="6.09,266,1716274800"; d="scan'208";a="20756267" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2024 19:43:17 -0700 X-CSE-ConnectionGUID: 3bLjj5LtRmSVmvtfZ9z+9g== X-CSE-MsgGUID: blbS6y3hR2WJq1BR83iVRw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,266,1716274800"; d="scan'208";a="56572522" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orviesa006.jf.intel.com with ESMTP; 05 Aug 2024 19:43:14 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v3 2/7] iommu/vt-d: Remove identity mappings from si_domain Date: Tue, 6 Aug 2024 10:39:36 +0800 Message-Id: <20240806023941.93454-3-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240806023941.93454-1-baolu.lu@linux.intel.com> References: <20240806023941.93454-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As the driver has enforced DMA domains for devices managed by an IOMMU hardware that doesn't support passthrough translation mode, there is no need for static identity mappings in the si_domain. Remove the identity mapping code to avoid dead code. Signed-off-by: Lu Baolu Reviewed-by: Jason Gunthorpe --- drivers/iommu/intel/iommu.c | 122 ++---------------------------------- 1 file changed, 4 insertions(+), 118 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 90ad794a1be7..723ea9f3f501 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -167,14 +167,7 @@ static void device_rbtree_remove(struct device_domain_= info *info) spin_unlock_irqrestore(&iommu->device_rbtree_lock, flags); } =20 -/* - * This domain is a statically identity mapping domain. - * 1. This domain creats a static 1:1 mapping to all usable memory. - * 2. It maps to each iommu if successful. - * 3. Each iommu mapps to this domain if successful. - */ static struct dmar_domain *si_domain; -static int hw_pass_through =3D 1; =20 struct dmar_rmrr_unit { struct list_head list; /* list of rmrr units */ @@ -1647,7 +1640,7 @@ static int domain_context_mapping_one(struct dmar_dom= ain *domain, struct context_entry *context; int agaw, ret; =20 - if (hw_pass_through && domain_type_is_si(domain)) + if (domain_type_is_si(domain)) translation =3D CONTEXT_TT_PASS_THROUGH; =20 pr_debug("Set context mapping for %02x:%02x.%d\n", @@ -1998,29 +1991,10 @@ static bool dev_is_real_dma_subdevice(struct device= *dev) pci_real_dma_dev(to_pci_dev(dev)) !=3D to_pci_dev(dev); } =20 -static int iommu_domain_identity_map(struct dmar_domain *domain, - unsigned long first_vpfn, - unsigned long last_vpfn) -{ - /* - * RMRR range might have overlap with physical memory range, - * clear it first - */ - dma_pte_clear_range(domain, first_vpfn, last_vpfn); - - return __domain_mapping(domain, first_vpfn, - first_vpfn, last_vpfn - first_vpfn + 1, - DMA_PTE_READ|DMA_PTE_WRITE, GFP_KERNEL); -} - static int md_domain_init(struct dmar_domain *domain, int guest_width); =20 -static int __init si_domain_init(int hw) +static int __init si_domain_init(void) { - struct dmar_rmrr_unit *rmrr; - struct device *dev; - int i, nid, ret; - si_domain =3D alloc_domain(IOMMU_DOMAIN_IDENTITY); if (!si_domain) return -EFAULT; @@ -2031,44 +2005,6 @@ static int __init si_domain_init(int hw) return -EFAULT; } =20 - if (hw) - return 0; - - for_each_online_node(nid) { - unsigned long start_pfn, end_pfn; - int i; - - for_each_mem_pfn_range(i, nid, &start_pfn, &end_pfn, NULL) { - ret =3D iommu_domain_identity_map(si_domain, - mm_to_dma_pfn_start(start_pfn), - mm_to_dma_pfn_end(end_pfn-1)); - if (ret) - return ret; - } - } - - /* - * Identity map the RMRRs so that devices with RMRRs could also use - * the si_domain. - */ - for_each_rmrr_units(rmrr) { - for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt, - i, dev) { - unsigned long long start =3D rmrr->base_address; - unsigned long long end =3D rmrr->end_address; - - if (WARN_ON(end < start || - end >> agaw_to_width(si_domain->agaw))) - continue; - - ret =3D iommu_domain_identity_map(si_domain, - mm_to_dma_pfn_start(start >> PAGE_SHIFT), - mm_to_dma_pfn_end(end >> PAGE_SHIFT)); - if (ret) - return ret; - } - } - return 0; } =20 @@ -2094,7 +2030,7 @@ static int dmar_domain_attach_device(struct dmar_doma= in *domain, =20 if (!sm_supported(iommu)) ret =3D domain_context_mapping(domain, dev); - else if (hw_pass_through && domain_type_is_si(domain)) + else if (domain_type_is_si(domain)) ret =3D intel_pasid_setup_pass_through(iommu, dev, IOMMU_NO_PASID); else if (domain->use_first_level) ret =3D domain_setup_first_level(iommu, domain, dev, IOMMU_NO_PASID); @@ -2449,8 +2385,6 @@ static int __init init_dmars(void) } } =20 - if (!ecap_pass_through(iommu->ecap)) - hw_pass_through =3D 0; intel_svm_check(iommu); } =20 @@ -2466,7 +2400,7 @@ static int __init init_dmars(void) =20 check_tylersburg_isoch(); =20 - ret =3D si_domain_init(hw_pass_through); + ret =3D si_domain_init(); if (ret) goto free_iommu; =20 @@ -2893,12 +2827,6 @@ static int intel_iommu_add(struct dmar_drhd_unit *dm= aru) if (ret) goto out; =20 - if (hw_pass_through && !ecap_pass_through(iommu->ecap)) { - pr_warn("%s: Doesn't support hardware pass through.\n", - iommu->name); - return -ENXIO; - } - sp =3D domain_update_iommu_superpage(NULL, iommu) - 1; if (sp >=3D 0 && !(cap_super_page_val(iommu->cap) & (1 << sp))) { pr_warn("%s: Doesn't support large page.\n", @@ -3149,43 +3077,6 @@ int dmar_iommu_notify_scope_dev(struct dmar_pci_noti= fy_info *info) return 0; } =20 -static int intel_iommu_memory_notifier(struct notifier_block *nb, - unsigned long val, void *v) -{ - struct memory_notify *mhp =3D v; - unsigned long start_vpfn =3D mm_to_dma_pfn_start(mhp->start_pfn); - unsigned long last_vpfn =3D mm_to_dma_pfn_end(mhp->start_pfn + - mhp->nr_pages - 1); - - switch (val) { - case MEM_GOING_ONLINE: - if (iommu_domain_identity_map(si_domain, - start_vpfn, last_vpfn)) { - pr_warn("Failed to build identity map for [%lx-%lx]\n", - start_vpfn, last_vpfn); - return NOTIFY_BAD; - } - break; - - case MEM_OFFLINE: - case MEM_CANCEL_ONLINE: - { - LIST_HEAD(freelist); - - domain_unmap(si_domain, start_vpfn, last_vpfn, &freelist); - iommu_put_pages_list(&freelist); - } - break; - } - - return NOTIFY_OK; -} - -static struct notifier_block intel_iommu_memory_nb =3D { - .notifier_call =3D intel_iommu_memory_notifier, - .priority =3D 0 -}; - static void intel_disable_iommus(void) { struct intel_iommu *iommu =3D NULL; @@ -3482,12 +3373,7 @@ int __init intel_iommu_init(void) =20 iommu_pmu_register(iommu); } - up_read(&dmar_global_lock); =20 - if (si_domain && !hw_pass_through) - register_memory_notifier(&intel_iommu_memory_nb); - - down_read(&dmar_global_lock); if (probe_acpi_namespace_devices()) pr_warn("ACPI name space devices didn't probe correctly\n"); =20 --=20 2.34.1 From nobody Fri Dec 19 17:34:21 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 280C722EE5 for ; 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X-CSE-ConnectionGUID: CFF4xXCgR4ORpuHmKDPezQ== X-CSE-MsgGUID: IteokO10TIqyUhc5nc3cqA== X-IronPort-AV: E=McAfee;i="6700,10204,11155"; a="20756275" X-IronPort-AV: E=Sophos;i="6.09,266,1716274800"; d="scan'208";a="20756275" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2024 19:43:19 -0700 X-CSE-ConnectionGUID: /1agKx6MQLiGItPn6qZLkQ== X-CSE-MsgGUID: Sq7BaKgIRnSmAZwxKyiZQg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,266,1716274800"; d="scan'208";a="56572526" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orviesa006.jf.intel.com with ESMTP; 05 Aug 2024 19:43:17 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v3 3/7] iommu/vt-d: Always reserve a domain ID for identity setup Date: Tue, 6 Aug 2024 10:39:37 +0800 Message-Id: <20240806023941.93454-4-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240806023941.93454-1-baolu.lu@linux.intel.com> References: <20240806023941.93454-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" We will use a global static identity domain. Reserve a static domain ID for it. Signed-off-by: Lu Baolu Reviewed-by: Jason Gunthorpe Reviewed-by: Jerry Snitselaar --- drivers/iommu/intel/iommu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 723ea9f3f501..c019fb3b3e78 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -1440,10 +1440,10 @@ static int iommu_init_domains(struct intel_iommu *i= ommu) * entry for first-level or pass-through translation modes should * be programmed with a domain id different from those used for * second-level or nested translation. We reserve a domain id for - * this purpose. + * this purpose. This domain id is also used for identity domain + * in legacy mode. */ - if (sm_supported(iommu)) - set_bit(FLPT_DEFAULT_DID, iommu->domain_ids); + set_bit(FLPT_DEFAULT_DID, iommu->domain_ids); =20 return 0; } --=20 2.34.1 From nobody Fri Dec 19 17:34:21 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29F6A2AE99 for ; Tue, 6 Aug 2024 02:43:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722912202; cv=none; b=ppaAvR+XuJ1eDbj3vhx84pLGysNGgavemYfF08QcAWkzEChnWKalrfDED+bHV+3fj85461ZXxUowYWLgspoKEXqnsWiW+3t5TO/uO3oEJ+o91udc7fhJRw5nS2MD/PhxBVPOKIWrQqyN84biARNfzNTv6AaFoPU7yo/GFf6ZTN4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722912202; c=relaxed/simple; bh=VvUjxvijcivH0pOPCUJicXjduLFqJW9qUOw2HGLvGnE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QFyYquKALCWJsgOSovwcYRjMqyC26Gt57x5tdhtCEKqyD0bfspaExrnIf8eS/1ARzy/OseaAucy9eiZxzzcy2NgSqx/vWvjB+MGT/yuJBsUr7RYlbEeaRb6Kvz6NbWmB4l64ldg/yznbxCsEMMJ8PNn5iRcALl2SkMmKeP5IT30= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=FHATSVgJ; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="FHATSVgJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1722912201; x=1754448201; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VvUjxvijcivH0pOPCUJicXjduLFqJW9qUOw2HGLvGnE=; b=FHATSVgJG6dDFnaQDCfuAN9rmfFy4erpMnvLKox3HhkBGaYV08iQsjc/ 55Bhmb7BlPvjIwBnVNVIzmvJzyaNaOm1qqA+3nbL818m15ICDw56wLazH Ewk1pRVFRft8RdgmF7P5i7lxMs+gBu2MgJLZwdLsZfN52xW3lmOk70FPp Bin5eoXqK91Zm0j5/DohQSNDMKHDFRlJBoazdvbZDVAgemevYCr6yzIUA HM0C6kSR+ozs7Y0vy2TE1MwUn6tKL3UYzDj5ijYhwKlkQmpug33Cifjtu CdCq8RXmWob+EdUjgFITo/oMoR3goVqhnqzx9cN/k1GoRLfU4oLDEEfq8 Q==; X-CSE-ConnectionGUID: Ak0VzgHVQHGWam/FUDY7sA== X-CSE-MsgGUID: YwHI8lmgTcuknLRzQsINbw== X-IronPort-AV: E=McAfee;i="6700,10204,11155"; a="20756281" X-IronPort-AV: E=Sophos;i="6.09,266,1716274800"; d="scan'208";a="20756281" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2024 19:43:21 -0700 X-CSE-ConnectionGUID: 37kGIGI3STG+A/xThK0ADw== X-CSE-MsgGUID: Q0oysaFfQQKIS3bonZEuvA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,266,1716274800"; d="scan'208";a="56572529" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orviesa006.jf.intel.com with ESMTP; 05 Aug 2024 19:43:19 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v3 4/7] iommu/vt-d: Prepare for global static identity domain Date: Tue, 6 Aug 2024 10:39:38 +0800 Message-Id: <20240806023941.93454-5-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240806023941.93454-1-baolu.lu@linux.intel.com> References: <20240806023941.93454-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With the static identity domain in place, the domain field of per-device iommu driver data can be either a pointer to a DMA translation domain, or NULL, indicating that the static identity domain is attached. Refactor the code to prepare for this change. Signed-off-by: Lu Baolu --- drivers/iommu/intel/iommu.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index c019fb3b3e78..f37c8c3cba3c 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -1270,6 +1270,9 @@ void domain_update_iotlb(struct dmar_domain *domain) bool has_iotlb_device =3D false; unsigned long flags; =20 + if (!domain) + return; + spin_lock_irqsave(&domain->lock, flags); list_for_each_entry(info, &domain->devices, link) { if (info->ats_enabled) { @@ -3706,11 +3709,9 @@ int prepare_domain_attach_device(struct iommu_domain= *domain, static int intel_iommu_attach_device(struct iommu_domain *domain, struct device *dev) { - struct device_domain_info *info =3D dev_iommu_priv_get(dev); int ret; =20 - if (info->domain) - device_block_translation(dev); + device_block_translation(dev); =20 ret =3D prepare_domain_attach_device(domain, dev); if (ret) @@ -4321,6 +4322,11 @@ static void intel_iommu_remove_dev_pasid(struct devi= ce *dev, ioasid_t pasid, struct intel_iommu *iommu =3D info->iommu; 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d="scan'208";a="56572535" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orviesa006.jf.intel.com with ESMTP; 05 Aug 2024 19:43:21 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v3 5/7] iommu/vt-d: Factor out helpers from domain_context_mapping_one() Date: Tue, 6 Aug 2024 10:39:39 +0800 Message-Id: <20240806023941.93454-6-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240806023941.93454-1-baolu.lu@linux.intel.com> References: <20240806023941.93454-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extract common code from domain_context_mapping_one() into new helpers, making it reusable by other functions such as the upcoming identity domain implementation. No intentional functional changes. Signed-off-by: Lu Baolu Reviewed-by: Jason Gunthorpe Reviewed-by: Jerry Snitselaar --- drivers/iommu/intel/iommu.c | 99 ++++++++++++++++++++++--------------- 1 file changed, 58 insertions(+), 41 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index f37c8c3cba3c..2ac56e2355e1 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -1631,6 +1631,61 @@ static void domain_exit(struct dmar_domain *domain) kfree(domain); } =20 +/* + * For kdump cases, old valid entries may be cached due to the + * in-flight DMA and copied pgtable, but there is no unmapping + * behaviour for them, thus we need an explicit cache flush for + * the newly-mapped device. For kdump, at this point, the device + * is supposed to finish reset at its driver probe stage, so no + * in-flight DMA will exist, and we don't need to worry anymore + * hereafter. + */ +static void copied_context_tear_down(struct intel_iommu *iommu, + struct context_entry *context, + u8 bus, u8 devfn) +{ + u16 did_old; + + if (!context_copied(iommu, bus, devfn)) + return; + + assert_spin_locked(&iommu->lock); + + did_old =3D context_domain_id(context); + context_clear_entry(context); + + if (did_old < cap_ndoms(iommu->cap)) { + iommu->flush.flush_context(iommu, did_old, + (((u16)bus) << 8) | devfn, + DMA_CCMD_MASK_NOBIT, + DMA_CCMD_DEVICE_INVL); + iommu->flush.flush_iotlb(iommu, did_old, 0, 0, + DMA_TLB_DSI_FLUSH); + } + + clear_context_copied(iommu, bus, devfn); +} + +/* + * It's a non-present to present mapping. If hardware doesn't cache + * non-present entry we only need to flush the write-buffer. If the + * _does_ cache non-present entries, then it does so in the special + * domain #0, which we have to flush: + */ +static void context_present_cache_flush(struct intel_iommu *iommu, u16 did, + u8 bus, u8 devfn) +{ + if (cap_caching_mode(iommu->cap)) { + iommu->flush.flush_context(iommu, 0, + (((u16)bus) << 8) | devfn, + DMA_CCMD_MASK_NOBIT, + DMA_CCMD_DEVICE_INVL); + iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH); + } else { + iommu_flush_write_buffer(iommu); + } +} + static int domain_context_mapping_one(struct dmar_domain *domain, struct intel_iommu *iommu, u8 bus, u8 devfn) @@ -1659,31 +1714,9 @@ static int domain_context_mapping_one(struct dmar_do= main *domain, if (context_present(context) && !context_copied(iommu, bus, devfn)) goto out_unlock; =20 - /* - * For kdump cases, old valid entries may be cached due to the - * in-flight DMA and copied pgtable, but there is no unmapping - * behaviour for them, thus we need an explicit cache flush for - * the newly-mapped device. For kdump, at this point, the device - * is supposed to finish reset at its driver probe stage, so no - * in-flight DMA will exist, and we don't need to worry anymore - * hereafter. - */ - if (context_copied(iommu, bus, devfn)) { - u16 did_old =3D context_domain_id(context); - - if (did_old < cap_ndoms(iommu->cap)) { - iommu->flush.flush_context(iommu, did_old, - (((u16)bus) << 8) | devfn, - DMA_CCMD_MASK_NOBIT, - DMA_CCMD_DEVICE_INVL); - iommu->flush.flush_iotlb(iommu, did_old, 0, 0, - DMA_TLB_DSI_FLUSH); - } - - clear_context_copied(iommu, bus, devfn); - } - + copied_context_tear_down(iommu, context, bus, devfn); context_clear_entry(context); + context_set_domain_id(context, did); =20 if (translation !=3D CONTEXT_TT_PASS_THROUGH) { @@ -1719,23 +1752,7 @@ static int domain_context_mapping_one(struct dmar_do= main *domain, context_set_present(context); if (!ecap_coherent(iommu->ecap)) clflush_cache_range(context, sizeof(*context)); - - /* - * It's a non-present to present mapping. If hardware doesn't cache - * non-present entry we only need to flush the write-buffer. If the - * _does_ cache non-present entries, then it does so in the special - * domain #0, which we have to flush: - */ - if (cap_caching_mode(iommu->cap)) { - iommu->flush.flush_context(iommu, 0, - (((u16)bus) << 8) | devfn, - DMA_CCMD_MASK_NOBIT, - DMA_CCMD_DEVICE_INVL); - iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH); - } else { - iommu_flush_write_buffer(iommu); - } - + context_present_cache_flush(iommu, did, bus, devfn); ret =3D 0; =20 out_unlock: --=20 2.34.1 From nobody Fri Dec 19 17:34:21 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF1ED175A5 for ; Tue, 6 Aug 2024 02:43:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722912207; cv=none; b=bw3RyRXZHvqYxhwt97IpXphwM7osI14nf2O9u1Gyhhq6Hc/m0t3rJnczuK+zAEmjOaKkkXGYHqP/MvQObw6CGEagfgOh0bBFhQQ86162qgJPWnKPTQMKVcEwnLgftXviXWsGuOspgbfnjm0i9LUqB8zELADoRSrCYl4FWW0ywBI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722912207; c=relaxed/simple; bh=BKDP/l/ykYrd+su1McxY6adYnlMLl4k2S1MoqpKDU7E=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=OdEAI6yrTGoTSEO1Xpz17E9Tli0AlLTImRY35zWdhEyZoxzn7kqFEtB1UnaMLq8FiO3T+vZFFd3iK2OYpahD/HQvsULtcS9zgH0V6M2MBjt6gbGXe+pGRCdkYkhZuL+xiHjQ360Zm4t+iAproVX81icXf1pUF+k7Hv++2o72wGs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=dPJX37v6; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="dPJX37v6" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1722912206; x=1754448206; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BKDP/l/ykYrd+su1McxY6adYnlMLl4k2S1MoqpKDU7E=; b=dPJX37v6igVl5hja4X5d2PBatEeIPXCy2o/8pDws8a8s1Vdpon82ual2 xrTR+1ryBAq5kjXgmp8PnzCbN9a0GqrBMCSu2gqvRhhNHdObL7MbsNn6j ih37ZcY6wuk2Mu9t8ME24Jn6+0m07JCmDWCNsd/TrsMbJEOuCtJCSNc+U +Vn6SOqeiO5kI3f40JyFDCXjD5zNaXNP2zWmCK60kxBhNQwHdjzK0piK1 nglV5f/vSFBqBxkF57S43SQQvjwUf7uLKhcvHeq5G4SZ/dlgKt2prHXZQ sYcDyxBZ/O+JCQoSxyZU0CvTHkwZBQEeUaDRM+YwNJvi91cI//Jc7Epmn A==; X-CSE-ConnectionGUID: nz7xq0GIT72KA7LKLV7IVg== X-CSE-MsgGUID: M4AObrrnROCF0JLPXZRq6A== X-IronPort-AV: E=McAfee;i="6700,10204,11155"; a="20756296" X-IronPort-AV: E=Sophos;i="6.09,266,1716274800"; d="scan'208";a="20756296" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2024 19:43:26 -0700 X-CSE-ConnectionGUID: 9V5IqpnMTdyShbtqBoWYIA== X-CSE-MsgGUID: BCfQxyQBSY+zMxk5ZLKzKQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,266,1716274800"; d="scan'208";a="56572538" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orviesa006.jf.intel.com with ESMTP; 05 Aug 2024 19:43:24 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v3 6/7] iommu/vt-d: Add support for static identity domain Date: Tue, 6 Aug 2024 10:39:40 +0800 Message-Id: <20240806023941.93454-7-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240806023941.93454-1-baolu.lu@linux.intel.com> References: <20240806023941.93454-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Software determines VT-d hardware support for passthrough translation by inspecting the capability register. If passthrough translation is not supported, the device is instructed to use DMA domain for its default domain. Add a global static identity domain with guaranteed attach semantics for IOMMUs that support passthrough translation mode. Signed-off-by: Lu Baolu Reviewed-by: Jason Gunthorpe --- drivers/iommu/intel/iommu.c | 102 ++++++++++++++++++++++++++++++++++++ 1 file changed, 102 insertions(+) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 2ac56e2355e1..9e7b4159e53f 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -4570,9 +4570,111 @@ static const struct iommu_dirty_ops intel_dirty_ops= =3D { .read_and_clear_dirty =3D intel_iommu_read_and_clear_dirty, }; =20 +static int context_setup_pass_through(struct device *dev, u8 bus, u8 devfn) +{ + struct device_domain_info *info =3D dev_iommu_priv_get(dev); + struct intel_iommu *iommu =3D info->iommu; + struct context_entry *context; + + spin_lock(&iommu->lock); + context =3D iommu_context_addr(iommu, bus, devfn, 1); + if (!context) { + spin_unlock(&iommu->lock); + return -ENOMEM; + } + + if (context_present(context) && !context_copied(iommu, bus, devfn)) { + spin_unlock(&iommu->lock); + return 0; + } + + copied_context_tear_down(iommu, context, bus, devfn); + context_clear_entry(context); + context_set_domain_id(context, FLPT_DEFAULT_DID); + + /* + * In pass through mode, AW must be programmed to indicate the largest + * AGAW value supported by hardware. And ASR is ignored by hardware. + */ + context_set_address_width(context, iommu->msagaw); + context_set_translation_type(context, CONTEXT_TT_PASS_THROUGH); + context_set_fault_enable(context); + context_set_present(context); + if (!ecap_coherent(iommu->ecap)) + clflush_cache_range(context, sizeof(*context)); + context_present_cache_flush(iommu, FLPT_DEFAULT_DID, bus, devfn); + spin_unlock(&iommu->lock); + + return 0; +} + +static int context_setup_pass_through_cb(struct pci_dev *pdev, u16 alias, = void *data) +{ + struct device *dev =3D data; + + if (dev !=3D &pdev->dev) + return 0; + + return context_setup_pass_through(dev, PCI_BUS_NUM(alias), alias & 0xff); +} + +static int device_setup_pass_through(struct device *dev) +{ + struct device_domain_info *info =3D dev_iommu_priv_get(dev); + + if (!dev_is_pci(dev)) + return context_setup_pass_through(dev, info->bus, info->devfn); + + return pci_for_each_dma_alias(to_pci_dev(dev), + context_setup_pass_through_cb, dev); +} + +static int identity_domain_attach_dev(struct iommu_domain *domain, struct = device *dev) +{ + struct device_domain_info *info =3D dev_iommu_priv_get(dev); + struct intel_iommu *iommu =3D info->iommu; + int ret; + + device_block_translation(dev); + + if (dev_is_real_dma_subdevice(dev)) + return 0; + + if (sm_supported(iommu)) { + ret =3D intel_pasid_setup_pass_through(iommu, dev, IOMMU_NO_PASID); + if (!ret) + iommu_enable_pci_caps(info); + } else { + ret =3D device_setup_pass_through(dev); + } + + return ret; +} + +static int identity_domain_set_dev_pasid(struct iommu_domain *domain, + struct device *dev, ioasid_t pasid) +{ + struct device_domain_info *info =3D dev_iommu_priv_get(dev); + struct intel_iommu *iommu =3D info->iommu; + + if (!pasid_supported(iommu) || dev_is_real_dma_subdevice(dev)) + return -EOPNOTSUPP; + + return intel_pasid_setup_pass_through(iommu, dev, pasid); +} + +static struct iommu_domain identity_domain =3D { + .type =3D IOMMU_DOMAIN_IDENTITY, + .ops =3D &(const struct iommu_domain_ops) { + .attach_dev =3D identity_domain_attach_dev, + .set_dev_pasid =3D identity_domain_set_dev_pasid, + }, +}; + const struct iommu_ops intel_iommu_ops =3D { .blocked_domain =3D &blocking_domain, .release_domain =3D &blocking_domain, + .identity_domain =3D &identity_domain, .capable =3D intel_iommu_capable, .hw_info =3D intel_iommu_hw_info, .domain_alloc =3D intel_iommu_domain_alloc, --=20 2.34.1 From nobody Fri Dec 19 17:34:21 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4031E3BB50 for ; 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X-CSE-ConnectionGUID: YMBY9SPMTrm60pZizftrpg== X-CSE-MsgGUID: AYKK4SiWSDu/CDaOYVD3Vw== X-IronPort-AV: E=McAfee;i="6700,10204,11155"; a="20756303" X-IronPort-AV: E=Sophos;i="6.09,266,1716274800"; d="scan'208";a="20756303" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2024 19:43:28 -0700 X-CSE-ConnectionGUID: QsNztapJRJa+zIBa+MtJqg== X-CSE-MsgGUID: gAeYOZrjRpOeRIKrONoyBA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,266,1716274800"; d="scan'208";a="56572543" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orviesa006.jf.intel.com with ESMTP; 05 Aug 2024 19:43:26 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v3 7/7] iommu/vt-d: Cleanup si_domain Date: Tue, 6 Aug 2024 10:39:41 +0800 Message-Id: <20240806023941.93454-8-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240806023941.93454-1-baolu.lu@linux.intel.com> References: <20240806023941.93454-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The static identity domain has been introduced, rendering the si_domain obsolete. Remove si_domain and cleanup the code accordingly. Signed-off-by: Lu Baolu Reviewed-by: Jason Gunthorpe --- drivers/iommu/intel/iommu.c | 91 ++++++++----------------------------- 1 file changed, 19 insertions(+), 72 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 9e7b4159e53f..8f8dce602c86 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -167,8 +167,6 @@ static void device_rbtree_remove(struct device_domain_i= nfo *info) spin_unlock_irqrestore(&iommu->device_rbtree_lock, flags); } =20 -static struct dmar_domain *si_domain; - struct dmar_rmrr_unit { struct list_head list; /* list of rmrr units */ struct acpi_dmar_header *hdr; /* ACPI header */ @@ -286,11 +284,6 @@ static int __init intel_iommu_setup(char *str) } __setup("intel_iommu=3D", intel_iommu_setup); =20 -static int domain_type_is_si(struct dmar_domain *domain) -{ - return domain->domain.type =3D=3D IOMMU_DOMAIN_IDENTITY; -} - static int domain_pfn_supported(struct dmar_domain *domain, unsigned long = pfn) { int addr_width =3D agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; @@ -1698,9 +1691,6 @@ static int domain_context_mapping_one(struct dmar_dom= ain *domain, struct context_entry *context; int agaw, ret; =20 - if (domain_type_is_si(domain)) - translation =3D CONTEXT_TT_PASS_THROUGH; - pr_debug("Set context mapping for %02x:%02x.%d\n", bus, PCI_SLOT(devfn), PCI_FUNC(devfn)); =20 @@ -1719,34 +1709,24 @@ static int domain_context_mapping_one(struct dmar_d= omain *domain, =20 context_set_domain_id(context, did); =20 - if (translation !=3D CONTEXT_TT_PASS_THROUGH) { - /* - * Skip top levels of page tables for iommu which has - * less agaw than default. Unnecessary for PT mode. - */ - for (agaw =3D domain->agaw; agaw > iommu->agaw; agaw--) { - ret =3D -ENOMEM; - pgd =3D phys_to_virt(dma_pte_addr(pgd)); - if (!dma_pte_present(pgd)) - goto out_unlock; - } - - if (info && info->ats_supported) - translation =3D CONTEXT_TT_DEV_IOTLB; - else - translation =3D CONTEXT_TT_MULTI_LEVEL; - - context_set_address_root(context, virt_to_phys(pgd)); - context_set_address_width(context, agaw); - } else { - /* - * In pass through mode, AW must be programmed to - * indicate the largest AGAW value supported by - * hardware. And ASR is ignored by hardware. - */ - context_set_address_width(context, iommu->msagaw); + /* + * Skip top levels of page tables for iommu which has + * less agaw than default. Unnecessary for PT mode. + */ + for (agaw =3D domain->agaw; agaw > iommu->agaw; agaw--) { + ret =3D -ENOMEM; + pgd =3D phys_to_virt(dma_pte_addr(pgd)); + if (!dma_pte_present(pgd)) + goto out_unlock; } =20 + if (info && info->ats_supported) + translation =3D CONTEXT_TT_DEV_IOTLB; + else + translation =3D CONTEXT_TT_MULTI_LEVEL; + + context_set_address_root(context, virt_to_phys(pgd)); + context_set_address_width(context, agaw); context_set_translation_type(context, translation); context_set_fault_enable(context); context_set_present(context); @@ -2011,23 +1991,6 @@ static bool dev_is_real_dma_subdevice(struct device = *dev) pci_real_dma_dev(to_pci_dev(dev)) !=3D to_pci_dev(dev); } =20 -static int md_domain_init(struct dmar_domain *domain, int guest_width); - -static int __init si_domain_init(void) -{ - si_domain =3D alloc_domain(IOMMU_DOMAIN_IDENTITY); - if (!si_domain) - return -EFAULT; - - if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) { - domain_exit(si_domain); - si_domain =3D NULL; - return -EFAULT; - } - - return 0; -} - static int dmar_domain_attach_device(struct dmar_domain *domain, struct device *dev) { @@ -2050,8 +2013,6 @@ static int dmar_domain_attach_device(struct dmar_doma= in *domain, =20 if (!sm_supported(iommu)) ret =3D domain_context_mapping(domain, dev); - else if (domain_type_is_si(domain)) - ret =3D intel_pasid_setup_pass_through(iommu, dev, IOMMU_NO_PASID); else if (domain->use_first_level) ret =3D domain_setup_first_level(iommu, domain, dev, IOMMU_NO_PASID); else @@ -2060,8 +2021,7 @@ static int dmar_domain_attach_device(struct dmar_doma= in *domain, if (ret) goto out_block_translation; =20 - if (sm_supported(info->iommu) || !domain_type_is_si(info->domain)) - iommu_enable_pci_caps(info); + iommu_enable_pci_caps(info); =20 ret =3D cache_tag_assign_domain(domain, dev, IOMMU_NO_PASID); if (ret) @@ -2420,10 +2380,6 @@ static int __init init_dmars(void) =20 check_tylersburg_isoch(); =20 - ret =3D si_domain_init(); - if (ret) - goto free_iommu; - /* * for each drhd * enable fault log @@ -2469,10 +2425,6 @@ static int __init init_dmars(void) disable_dmar_iommu(iommu); free_dmar_iommu(iommu); } - if (si_domain) { - domain_exit(si_domain); - si_domain =3D NULL; - } =20 return ret; } @@ -3607,8 +3559,6 @@ static struct iommu_domain *intel_iommu_domain_alloc(= unsigned type) domain->geometry.force_aperture =3D true; =20 return domain; - case IOMMU_DOMAIN_IDENTITY: - return &si_domain->domain; default: return NULL; } @@ -3675,8 +3625,7 @@ static void intel_iommu_domain_free(struct iommu_doma= in *domain) =20 WARN_ON(dmar_domain->nested_parent && !list_empty(&dmar_domain->s1_domains)); - if (domain !=3D &si_domain->domain) - domain_exit(dmar_domain); + domain_exit(dmar_domain); } =20 int prepare_domain_attach_device(struct iommu_domain *domain, @@ -4398,9 +4347,7 @@ static int intel_iommu_set_dev_pasid(struct iommu_dom= ain *domain, if (ret) goto out_detach_iommu; =20 - if (domain_type_is_si(dmar_domain)) - ret =3D intel_pasid_setup_pass_through(iommu, dev, pasid); - else if (dmar_domain->use_first_level) + if (dmar_domain->use_first_level) ret =3D domain_setup_first_level(iommu, dmar_domain, dev, pasid); else --=20 2.34.1