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[24.38.217.1]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6bb9c78ad54sm40028016d6.31.2024.08.05.15.59.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Aug 2024 15:59:11 -0700 (PDT) From: Alex Lanzano To: christophe.jaillet@wanadoo.fr, Alex Lanzano , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mehdi Djait Cc: Krzysztof Kozlowski , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/2] dt-bindings: display: Add Sharp Memory LCD bindings Date: Mon, 5 Aug 2024 18:57:50 -0400 Message-ID: <20240805225820.13798-3-lanzano.alex@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240805225820.13798-2-lanzano.alex@gmail.com> References: <20240805225820.13798-2-lanzano.alex@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree bindings for the monochrome Sharp Memory LCD Co-developed-by: Mehdi Djait Signed-off-by: Mehdi Djait Signed-off-by: Alex Lanzano Reviewed-by: Krzysztof Kozlowski --- .../bindings/display/sharp,ls010b7dh04.yaml | 92 +++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/sharp,ls010b7= dh04.yaml diff --git a/Documentation/devicetree/bindings/display/sharp,ls010b7dh04.ya= ml b/Documentation/devicetree/bindings/display/sharp,ls010b7dh04.yaml new file mode 100644 index 000000000000..8097f091c2a5 --- /dev/null +++ b/Documentation/devicetree/bindings/display/sharp,ls010b7dh04.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/sharp,ls010b7dh04.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sharp Memory LCD panels + +maintainers: + - Alex Lanzano + +description: + Sharp Memory LCDs are a series of monochrome displays that operate over + a SPI bus. The displays require a signal (VCOM) to be generated to preve= nt + DC bias build up resulting in pixels being unable to change. Three modes + can be used to provide the VCOM signal ("software", "external", "pwm"). + +properties: + compatible: + enum: + - sharp,ls010b7dh04 + - sharp,ls011b7dh03 + - sharp,ls012b7dd01 + - sharp,ls013b7dh03 + - sharp,ls013b7dh05 + - sharp,ls018b7dh02 + - sharp,ls027b7dh01 + - sharp,ls027b7dh01a + - sharp,ls032b7dd02 + - sharp,ls044q7dh01 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 2000000 + + sharp,vcom-mode: + $ref: /schemas/types.yaml#/definitions/string + description: | + software - This mode relies on a software operation to send a + "maintain display" message to the display, toggling the vcom + bit on and off with each message + + external - This mode relies on an external clock to generate + the signal on the EXTCOMM pin + + pwm - This mode relies on a pwm device to generate the signal + on the EXTCOMM pin + + enum: [software, external, pwm] + + enable-gpios: true + + pwms: + maxItems: 1 + description: External VCOM signal + +required: + - compatible + - reg + - sharp,vcom-mode + +allOf: + - $ref: panel/panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + + - if: + properties: + sharp,vcom-mode: + const: pwm + then: + required: + - pwms + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + display@0 { + compatible =3D "sharp,ls013b7dh03"; + reg =3D <0>; + spi-cs-high; + spi-max-frequency =3D <1000000>; + sharp,vcom-mode =3D "software"; + }; + }; +... --=20 2.45.2 From nobody Sat Feb 7 08:09:31 2026 Received: from mail-qv1-f46.google.com (mail-qv1-f46.google.com [209.85.219.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4606A16C696; Mon, 5 Aug 2024 22:59:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722898769; cv=none; b=qQZNXQlSVaDDtlICGXeuckBF8KOw7hTq3Uj4+Uh4rDNEQfd6WBrVrviEHp2TxgawCYywMctgJEACI4MdbCO2d80KC4da9jl5zM+agjpxHBQOO7Vg+M2eS3CJ9Zo7mozdYiMwhc+3mMLydl4jk6knCUe1yvGh+yHXVYgIhqzRKSE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722898769; c=relaxed/simple; bh=OX5iiAxL6xS2PcIxvxZ0bfuxGHSl2ldKoPhVbj5bVU4=; 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[24.38.217.1]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6bb9c78ad54sm40028016d6.31.2024.08.05.15.59.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Aug 2024 15:59:25 -0700 (PDT) From: Alex Lanzano To: christophe.jaillet@wanadoo.fr, Alex Lanzano , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mehdi Djait Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/2] drm/tiny: Add driver for Sharp Memory LCD Date: Mon, 5 Aug 2024 18:57:51 -0400 Message-ID: <20240805225820.13798-4-lanzano.alex@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240805225820.13798-2-lanzano.alex@gmail.com> References: <20240805225820.13798-2-lanzano.alex@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the monochrome Sharp Memory LCDs. Co-developed-by: Mehdi Djait Signed-off-by: Mehdi Djait Signed-off-by: Alex Lanzano --- MAINTAINERS | 6 + drivers/gpu/drm/tiny/Kconfig | 20 + drivers/gpu/drm/tiny/Makefile | 1 + drivers/gpu/drm/tiny/sharp-memory.c | 682 ++++++++++++++++++++++++++++ 4 files changed, 709 insertions(+) create mode 100644 drivers/gpu/drm/tiny/sharp-memory.c diff --git a/MAINTAINERS b/MAINTAINERS index 1a802219e096..6d2a56c333bc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7124,6 +7124,12 @@ S: Maintained F: Documentation/devicetree/bindings/display/panel/samsung,s6d7aa0.yaml F: drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c =20 +DRM DRIVER FOR SHARP MEMORY LCD +M: Alex Lanzano +S: Maintained +F: Documentation/devicetree/bindings/display/sharp,ls010b7dh04.yaml +F: drivers/gpu/drm/tiny/sharp-memory.c + DRM DRIVER FOR SITRONIX ST7586 PANELS M: David Lechner S: Maintained diff --git a/drivers/gpu/drm/tiny/Kconfig b/drivers/gpu/drm/tiny/Kconfig index f6889f649bc1..bc386954faa2 100644 --- a/drivers/gpu/drm/tiny/Kconfig +++ b/drivers/gpu/drm/tiny/Kconfig @@ -186,6 +186,26 @@ config TINYDRM_REPAPER =20 If M is selected the module will be called repaper. =20 +config TINYDRM_SHARP_MEMORY + tristate "DRM support for Sharp Memory LCD panels" + depends on DRM && SPI + select DRM_GEM_DMA_HELPER + select DRM_KMS_HELPER + help + DRM Driver for the following Sharp Memory Panels: + * 1.00" Sharp Memory LCD (LS010B7DH04) + * 1.10" Sharp Memory LCD (LS011B7DH03) + * 1.20" Sharp Memory LCD (LS012B7DD01) + * 1.28" Sharp Memory LCD (LS013B7DH03) + * 1.26" Sharp Memory LCD (LS013B7DH05) + * 1.80" Sharp Memory LCD (LS018B7DH02) + * 2.70" Sharp Memory LCD (LS027B7DH01) + * 2.70" Sharp Memory LCD (LS027B7DH01A) + * 3.20" Sharp Memory LCD (LS032B7DD02) + * 4.40" Sharp Memory LCD (LS044Q7DH01) + + If M is selected the module will be called sharp_memory. + config TINYDRM_ST7586 tristate "DRM support for Sitronix ST7586 display panels" depends on DRM && SPI diff --git a/drivers/gpu/drm/tiny/Makefile b/drivers/gpu/drm/tiny/Makefile index 76dde89a044b..4aaf56f8707d 100644 --- a/drivers/gpu/drm/tiny/Makefile +++ b/drivers/gpu/drm/tiny/Makefile @@ -14,5 +14,6 @@ obj-$(CONFIG_TINYDRM_ILI9341) +=3D ili9341.o obj-$(CONFIG_TINYDRM_ILI9486) +=3D ili9486.o obj-$(CONFIG_TINYDRM_MI0283QT) +=3D mi0283qt.o obj-$(CONFIG_TINYDRM_REPAPER) +=3D repaper.o +obj-$(CONFIG_TINYDRM_SHARP_MEMORY) +=3D sharp-memory.o obj-$(CONFIG_TINYDRM_ST7586) +=3D st7586.o obj-$(CONFIG_TINYDRM_ST7735R) +=3D st7735r.o diff --git a/drivers/gpu/drm/tiny/sharp-memory.c b/drivers/gpu/drm/tiny/sha= rp-memory.c new file mode 100644 index 000000000000..70236d3588a3 --- /dev/null +++ b/drivers/gpu/drm/tiny/sharp-memory.c @@ -0,0 +1,682 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SHARP_MODE_PERIOD 8 +#define SHARP_ADDR_PERIOD 8 +#define SHARP_DUMMY_PERIOD 8 + +#define SHARP_MEMORY_DISPLAY_MAINTAIN_MODE 0 +#define SHARP_MEMORY_DISPLAY_UPDATE_MODE 1 +#define SHARP_MEMORY_DISPLAY_CLEAR_MODE 4 + +enum sharp_memory_model { + LS010B7DH04, + LS011B7DH03, + LS012B7DD01, + LS013B7DH03, + LS013B7DH05, + LS018B7DH02, + LS027B7DH01, + LS027B7DH01A, + LS032B7DD02, + LS044Q7DH01, +}; + +enum sharp_memory_vcom_mode { + SHARP_MEMORY_SOFTWARE_VCOM, + SHARP_MEMORY_EXTERNAL_VCOM, + SHARP_MEMORY_PWM_VCOM +}; + +struct sharp_memory_device { + struct drm_device drm; + struct spi_device *spi; + + const struct drm_display_mode *mode; + + struct drm_crtc crtc; + struct drm_plane plane; + struct drm_encoder encoder; + struct drm_connector connector; + + struct gpio_desc *enable_gpio; + + struct task_struct *sw_vcom_signal; + struct pwm_device *pwm_vcom_signal; + + enum sharp_memory_vcom_mode vcom_mode; + u8 vcom; + + u32 pitch; + u32 tx_buffer_size; + u8 *tx_buffer; + + /* When vcom_mode =3D=3D "software" a kthread is used to + * periodically send a 'maintain display' message over + * spi. This mutex ensures tx_buffer access and spi bus + * usage is synchronized in this case + */ + struct mutex tx_mutex; +}; + +static inline int sharp_memory_spi_write(struct spi_device *spi, void *buf= , size_t len) +{ + /* Reverse the bit order */ + for (u8 *b =3D buf; b < ((u8 *)buf) + len; ++b) + *b =3D bitrev8(*b); + + return spi_write(spi, buf, len); +} + +static inline struct sharp_memory_device *drm_to_sharp_memory_device(struc= t drm_device *drm) +{ + return container_of(drm, struct sharp_memory_device, drm); +} + +DEFINE_DRM_GEM_DMA_FOPS(sharp_memory_fops); + +static const struct drm_driver sharp_memory_drm_driver =3D { + .driver_features =3D DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, + .fops =3D &sharp_memory_fops, + DRM_GEM_DMA_DRIVER_OPS_VMAP, + .name =3D "sharp_memory_display", + .desc =3D "Sharp Display Memory LCD", + .date =3D "20231129", + .major =3D 1, + .minor =3D 0, +}; + +static inline void sharp_memory_set_tx_buffer_mode(u8 *buffer, u8 mode, u8= vcom) +{ + *buffer =3D mode | (vcom << 1); +} + +static inline void sharp_memory_set_tx_buffer_addresses(u8 *buffer, + struct drm_rect clip, + u32 pitch) +{ + for (u32 line =3D 0; line < clip.y2; ++line) + buffer[line * pitch] =3D line + 1; +} + +static void sharp_memory_set_tx_buffer_data(u8 *buffer, + struct drm_framebuffer *fb, + struct drm_rect clip, + u32 pitch, + struct drm_format_conv_state *fmtcnv_state) +{ + int ret; + struct iosys_map dst, vmap; + struct drm_gem_dma_object *dma_obj =3D drm_fb_dma_get_gem_obj(fb, 0); + + ret =3D drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE); + if (ret) + return; + + iosys_map_set_vaddr(&dst, buffer); + iosys_map_set_vaddr(&vmap, dma_obj->vaddr); + + drm_fb_xrgb8888_to_mono(&dst, &pitch, &vmap, fb, &clip, fmtcnv_state); + + drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE); +} + +static int sharp_memory_update_display(struct sharp_memory_device *smd, + struct drm_framebuffer *fb, + struct drm_rect clip, + struct drm_format_conv_state *fmtcnv_state) +{ + int ret; + u32 pitch =3D smd->pitch; + u8 vcom =3D smd->vcom; + u8 *tx_buffer =3D smd->tx_buffer; + u32 tx_buffer_size =3D smd->tx_buffer_size; + + mutex_lock(&smd->tx_mutex); + + /* Populate the transmit buffer with frame data */ + sharp_memory_set_tx_buffer_mode(&tx_buffer[0], + SHARP_MEMORY_DISPLAY_UPDATE_MODE, vcom); + sharp_memory_set_tx_buffer_addresses(&tx_buffer[1], clip, pitch); + sharp_memory_set_tx_buffer_data(&tx_buffer[2], fb, clip, pitch, fmtcnv_st= ate); + + ret =3D sharp_memory_spi_write(smd->spi, tx_buffer, tx_buffer_size); + + mutex_unlock(&smd->tx_mutex); + + return ret; +} + +static int sharp_memory_maintain_display(struct sharp_memory_device *smd) +{ + int ret; + u8 vcom =3D smd->vcom; + u8 *tx_buffer =3D smd->tx_buffer; + + mutex_lock(&smd->tx_mutex); + + sharp_memory_set_tx_buffer_mode(&tx_buffer[0], SHARP_MEMORY_DISPLAY_MAINT= AIN_MODE, vcom); + tx_buffer[1] =3D 0; // Write dummy data + ret =3D sharp_memory_spi_write(smd->spi, tx_buffer, 2); + + mutex_unlock(&smd->tx_mutex); + + return ret; +} + +static int sharp_memory_clear_display(struct sharp_memory_device *smd) +{ + int ret; + u8 vcom =3D smd->vcom; + u8 *tx_buffer =3D smd->tx_buffer; + + mutex_lock(&smd->tx_mutex); + + sharp_memory_set_tx_buffer_mode(&tx_buffer[0], SHARP_MEMORY_DISPLAY_CLEAR= _MODE, vcom); + tx_buffer[1] =3D 0; // write dummy data + ret =3D sharp_memory_spi_write(smd->spi, tx_buffer, 2); + + mutex_unlock(&smd->tx_mutex); + + return ret; +} + +static void sharp_memory_fb_dirty(struct drm_framebuffer *fb, struct drm_r= ect *rect, + struct drm_format_conv_state *fmtconv_state) +{ + struct drm_rect clip; + struct sharp_memory_device *smd =3D drm_to_sharp_memory_device(fb->dev); + + /* Always update a full line regardless of what is dirty */ + clip.x1 =3D 0; + clip.x2 =3D fb->width; + clip.y1 =3D rect->y1; + clip.y2 =3D rect->y2; + + sharp_memory_update_display(smd, fb, clip, fmtconv_state); +} + +static int sharp_memory_plane_atomic_check(struct drm_plane *plane, + struct drm_atomic_state *state) +{ + struct drm_plane_state *plane_state =3D drm_atomic_get_new_plane_state(st= ate, plane); + struct sharp_memory_device *smd; + struct drm_crtc_state *crtc_state; + + smd =3D container_of(plane, struct sharp_memory_device, plane); + crtc_state =3D drm_atomic_get_new_crtc_state(state, &smd->crtc); + + return drm_atomic_helper_check_plane_state(plane_state, crtc_state, + DRM_PLANE_NO_SCALING, + DRM_PLANE_NO_SCALING, + false, false); +} + +static void sharp_memory_plane_atomic_update(struct drm_plane *plane, + struct drm_atomic_state *state) +{ + struct drm_plane_state *old_state =3D drm_atomic_get_old_plane_state(stat= e, plane); + struct drm_plane_state *plane_state =3D plane->state; + struct drm_format_conv_state fmtcnv_state =3D DRM_FORMAT_CONV_STATE_INIT; + struct sharp_memory_device *smd; + struct drm_rect rect; + + smd =3D container_of(plane, struct sharp_memory_device, plane); + if (!smd->crtc.state->active) + return; + + if (drm_atomic_helper_damage_merged(old_state, plane_state, &rect)) + sharp_memory_fb_dirty(plane_state->fb, &rect, &fmtcnv_state); + + drm_format_conv_state_release(&fmtcnv_state); +} + +static const struct drm_plane_helper_funcs sharp_memory_plane_helper_funcs= =3D { + .prepare_fb =3D drm_gem_plane_helper_prepare_fb, + .atomic_check =3D sharp_memory_plane_atomic_check, + .atomic_update =3D sharp_memory_plane_atomic_update, +}; + +static bool sharp_memory_format_mod_supported(struct drm_plane *plane, + u32 format, + u64 modifier) +{ + return modifier =3D=3D DRM_FORMAT_MOD_LINEAR; +} + +static const struct drm_plane_funcs sharp_memory_plane_funcs =3D { + .update_plane =3D drm_atomic_helper_update_plane, + .disable_plane =3D drm_atomic_helper_disable_plane, + .destroy =3D drm_plane_cleanup, + .reset =3D drm_atomic_helper_plane_reset, + .atomic_duplicate_state =3D drm_atomic_helper_plane_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_plane_destroy_state, + .format_mod_supported =3D sharp_memory_format_mod_supported, +}; + +static enum drm_mode_status sharp_memory_crtc_mode_valid(struct drm_crtc *= crtc, + const struct drm_display_mode *mode) +{ + struct sharp_memory_device *smd =3D drm_to_sharp_memory_device(crtc->dev); + + return drm_crtc_helper_mode_valid_fixed(crtc, mode, smd->mode); +} + +static int sharp_memory_crtc_check(struct drm_crtc *crtc, + struct drm_atomic_state *state) +{ + struct drm_crtc_state *crtc_state =3D drm_atomic_get_new_crtc_state(state= , crtc); + int ret; + + if (!crtc_state->enable) + goto out; + + ret =3D drm_atomic_helper_check_crtc_primary_plane(crtc_state); + if (ret) + return ret; + +out: + return drm_atomic_add_affected_planes(state, crtc); +} + +static int sharp_memory_sw_vcom_signal_thread(void *data) +{ + struct sharp_memory_device *smd =3D data; + + while (!kthread_should_stop()) { + smd->vcom ^=3D 1; // Toggle vcom + sharp_memory_maintain_display(smd); + msleep(1000); + } + + return 0; +} + +static void sharp_memory_crtc_enable(struct drm_crtc *crtc, + struct drm_atomic_state *state) +{ + struct pwm_state pwm_state; + struct sharp_memory_device *smd =3D drm_to_sharp_memory_device(crtc->dev); + + sharp_memory_clear_display(smd); + + if (smd->enable_gpio) + gpiod_set_value(smd->enable_gpio, 1); + + switch (smd->vcom_mode) { + case SHARP_MEMORY_SOFTWARE_VCOM: + smd->sw_vcom_signal =3D kthread_run(sharp_memory_sw_vcom_signal_thread, + smd, "sw_vcom_signal"); + break; + + case SHARP_MEMORY_EXTERNAL_VCOM: + break; + + case SHARP_MEMORY_PWM_VCOM: + pwm_get_state(smd->pwm_vcom_signal, &pwm_state); + pwm_state.period =3D 1000000000; + pwm_state.duty_cycle =3D 100000000; + pwm_state.enabled =3D true; + pwm_apply_state(smd->pwm_vcom_signal, &pwm_state); + break; + } +} + +static void sharp_memory_crtc_disable(struct drm_crtc *crtc, + struct drm_atomic_state *state) +{ + struct sharp_memory_device *smd =3D drm_to_sharp_memory_device(crtc->dev); + + sharp_memory_clear_display(smd); + + if (smd->enable_gpio) + gpiod_set_value(smd->enable_gpio, 0); + + switch (smd->vcom_mode) { + case SHARP_MEMORY_SOFTWARE_VCOM: + kthread_stop(smd->sw_vcom_signal); + break; + + case SHARP_MEMORY_EXTERNAL_VCOM: + break; + + case SHARP_MEMORY_PWM_VCOM: + pwm_disable(smd->pwm_vcom_signal); + break; + } +} + +static const struct drm_crtc_helper_funcs sharp_memory_crtc_helper_funcs = =3D { + .mode_valid =3D sharp_memory_crtc_mode_valid, + .atomic_check =3D sharp_memory_crtc_check, + .atomic_enable =3D sharp_memory_crtc_enable, + .atomic_disable =3D sharp_memory_crtc_disable, +}; + +static const struct drm_crtc_funcs sharp_memory_crtc_funcs =3D { + .reset =3D drm_atomic_helper_crtc_reset, + .destroy =3D drm_crtc_cleanup, + .set_config =3D drm_atomic_helper_set_config, + .page_flip =3D drm_atomic_helper_page_flip, + .atomic_duplicate_state =3D drm_atomic_helper_crtc_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_crtc_destroy_state, +}; + +static const struct drm_encoder_funcs sharp_memory_encoder_funcs =3D { + .destroy =3D drm_encoder_cleanup, +}; + +static int sharp_memory_connector_get_modes(struct drm_connector *connecto= r) +{ + struct sharp_memory_device *smd =3D drm_to_sharp_memory_device(connector-= >dev); + + return drm_connector_helper_get_modes_fixed(connector, smd->mode); +} + +static const struct drm_connector_helper_funcs sharp_memory_connector_hfun= cs =3D { + .get_modes =3D sharp_memory_connector_get_modes, +}; + +static const struct drm_connector_funcs sharp_memory_connector_funcs =3D { + .reset =3D drm_atomic_helper_connector_reset, + .fill_modes =3D drm_helper_probe_single_connector_modes, + .destroy =3D drm_connector_cleanup, + .atomic_duplicate_state =3D drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_connector_destroy_state, + +}; + +static const struct drm_mode_config_funcs sharp_memory_mode_config_funcs = =3D { + .fb_create =3D drm_gem_fb_create_with_dirty, + .atomic_check =3D drm_atomic_helper_check, + .atomic_commit =3D drm_atomic_helper_commit, +}; + +static const struct drm_display_mode sharp_memory_ls010b7dh04_mode =3D { + DRM_SIMPLE_MODE(128, 128, 18, 18), +}; + +static const struct drm_display_mode sharp_memory_ls011b7dh03_mode =3D { + DRM_SIMPLE_MODE(160, 68, 25, 10), +}; + +static const struct drm_display_mode sharp_memory_ls012b7dd01_mode =3D { + DRM_SIMPLE_MODE(184, 38, 29, 6), +}; + +static const struct drm_display_mode sharp_memory_ls013b7dh03_mode =3D { + DRM_SIMPLE_MODE(128, 128, 23, 23), +}; + +static const struct drm_display_mode sharp_memory_ls013b7dh05_mode =3D { + DRM_SIMPLE_MODE(144, 168, 20, 24), +}; + +static const struct drm_display_mode sharp_memory_ls018b7dh02_mode =3D { + DRM_SIMPLE_MODE(230, 303, 27, 36), +}; + +static const struct drm_display_mode sharp_memory_ls027b7dh01_mode =3D { + DRM_SIMPLE_MODE(400, 240, 58, 35), +}; + +static const struct drm_display_mode sharp_memory_ls032b7dd02_mode =3D { + DRM_SIMPLE_MODE(336, 536, 42, 68), +}; + +static const struct drm_display_mode sharp_memory_ls044q7dh01_mode =3D { + DRM_SIMPLE_MODE(320, 240, 89, 67), +}; + +static const struct spi_device_id sharp_memory_ids[] =3D { + {"ls010b7dh04", (kernel_ulong_t)&sharp_memory_ls010b7dh04_mode}, + {"ls011b7dh03", (kernel_ulong_t)&sharp_memory_ls011b7dh03_mode}, + {"ls012b7dd01", (kernel_ulong_t)&sharp_memory_ls012b7dd01_mode}, + {"ls013b7dh03", (kernel_ulong_t)&sharp_memory_ls013b7dh03_mode}, + {"ls013b7dh05", (kernel_ulong_t)&sharp_memory_ls013b7dh05_mode}, + {"ls018b7dh02", (kernel_ulong_t)&sharp_memory_ls018b7dh02_mode}, + {"ls027b7dh01", (kernel_ulong_t)&sharp_memory_ls027b7dh01_mode}, + {"ls027b7dh01a", (kernel_ulong_t)&sharp_memory_ls027b7dh01_mode}, + {"ls032b7dd02", (kernel_ulong_t)&sharp_memory_ls032b7dd02_mode}, + {"ls044q7dh01", (kernel_ulong_t)&sharp_memory_ls044q7dh01_mode}, + {}, +}; +MODULE_DEVICE_TABLE(spi, sharp_memory_ids); + +static const struct of_device_id sharp_memory_of_match[] =3D { + {.compatible =3D "sharp,ls010b7dh04", &sharp_memory_ls010b7dh04_mode}, + {.compatible =3D "sharp,ls011b7dh03", &sharp_memory_ls011b7dh03_mode}, + {.compatible =3D "sharp,ls012b7dd01", &sharp_memory_ls012b7dd01_mode}, + {.compatible =3D "sharp,ls013b7dh03", &sharp_memory_ls013b7dh03_mode}, + {.compatible =3D "sharp,ls013b7dh05", &sharp_memory_ls013b7dh05_mode}, + {.compatible =3D "sharp,ls018b7dh02", &sharp_memory_ls018b7dh02_mode}, + {.compatible =3D "sharp,ls027b7dh01", &sharp_memory_ls027b7dh01_mode}, + {.compatible =3D "sharp,ls027b7dh01a", &sharp_memory_ls027b7dh01_mode}, + {.compatible =3D "sharp,ls032b7dd02", &sharp_memory_ls032b7dd02_mode}, + {.compatible =3D "sharp,ls044q7dh01", &sharp_memory_ls044q7dh01_mode}, + {}, +}; +MODULE_DEVICE_TABLE(of, sharp_memory_of_match); + +static const u32 sharp_memory_formats[] =3D { + DRM_FORMAT_XRGB8888, +}; + +static int sharp_memory_pipe_init(struct drm_device *dev, + struct sharp_memory_device *smd, + const u32 *formats, unsigned int format_count, + const u64 *format_modifiers) +{ + int ret; + struct drm_encoder *encoder =3D &smd->encoder; + struct drm_plane *plane =3D &smd->plane; + struct drm_crtc *crtc =3D &smd->crtc; + struct drm_connector *connector =3D &smd->connector; + + drm_plane_helper_add(plane, &sharp_memory_plane_helper_funcs); + ret =3D drm_universal_plane_init(dev, plane, 0, + &sharp_memory_plane_funcs, + formats, format_count, + format_modifiers, + DRM_PLANE_TYPE_PRIMARY, NULL); + if (ret) + return ret; + + drm_crtc_helper_add(crtc, &sharp_memory_crtc_helper_funcs); + ret =3D drm_crtc_init_with_planes(dev, crtc, plane, NULL, + &sharp_memory_crtc_funcs, NULL); + if (ret) + return ret; + + encoder->possible_crtcs =3D drm_crtc_mask(crtc); + ret =3D drm_encoder_init(dev, encoder, &sharp_memory_encoder_funcs, + DRM_MODE_ENCODER_NONE, NULL); + if (ret) + return ret; + + ret =3D drm_connector_init(&smd->drm, &smd->connector, + &sharp_memory_connector_funcs, + DRM_MODE_CONNECTOR_SPI); + if (ret) + return ret; + + drm_connector_helper_add(&smd->connector, + &sharp_memory_connector_hfuncs); + + return drm_connector_attach_encoder(connector, encoder); +} + +static int sharp_memory_init_pwm_vcom_signal(struct sharp_memory_device *s= md) +{ + struct pwm_state state; + struct device *dev =3D &smd->spi->dev; + + smd->pwm_vcom_signal =3D devm_pwm_get(dev, NULL); + if (IS_ERR(smd->pwm_vcom_signal)) + return dev_err_probe(dev, -EINVAL, "Could not get pwm device\n"); + + pwm_init_state(smd->pwm_vcom_signal, &state); + state.enabled =3D false; + pwm_apply_state(smd->pwm_vcom_signal, &state); + + return 0; +} + +static int sharp_memory_probe(struct spi_device *spi) +{ + int ret; + struct device *dev; + struct sharp_memory_device *smd; + struct drm_device *drm; + const char *vcom_mode_str; + + ret =3D spi_setup(spi); + if (ret < 0) + return dev_err_probe(&spi->dev, ret, "Failed to setup spi device\n"); + + dev =3D &spi->dev; + if (!dev->coherent_dma_mask) { + ret =3D dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32)); + if (ret) + return dev_err_probe(dev, ret, "Failed to set dma mask\n"); + } + + smd =3D devm_drm_dev_alloc(dev, &sharp_memory_drm_driver, + struct sharp_memory_device, drm); + if (!smd) + return -ENOMEM; + + spi_set_drvdata(spi, smd); + + smd->spi =3D spi; + drm =3D &smd->drm; + ret =3D drmm_mode_config_init(drm); + if (ret) + return dev_err_probe(dev, ret, "Failed to initialize drm config\n"); + + smd->enable_gpio =3D devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_HIG= H); + if (!smd->enable_gpio) + dev_warn(dev, "Enable gpio not defined\n"); + + /* + * VCOM is a signal that prevents DC bias from being built up in + * the panel resulting in pixels being forever stuck in one state. + * + * This driver supports three different methods to generate this + * signal depending on EXTMODE pin: + * + * software (EXTMODE =3D L) - This mode uses a kthread to + * periodically send a "maintain display" message to the display, + * toggling the vcom bit on and off with each message + * + * external (EXTMODE =3D H) - This mode relies on an external + * clock to generate the signal on the EXTCOMM pin + * + * pwm (EXTMODE =3D H) - This mode uses a pwm device to generate + * the signal on the EXTCOMM pin + * + */ + if (device_property_read_string(&spi->dev, "sharp,vcom-mode", &vcom_mode_= str)) + return dev_err_probe(dev, -EINVAL, + "Unable to find sharp,vcom-mode node in device tree\n"); + + if (!strcmp("software", vcom_mode_str)) { + smd->vcom_mode =3D SHARP_MEMORY_SOFTWARE_VCOM; + + } else if (!strcmp("external", vcom_mode_str)) { + smd->vcom_mode =3D SHARP_MEMORY_EXTERNAL_VCOM; + + } else if (!strcmp("pwm", vcom_mode_str)) { + smd->vcom_mode =3D SHARP_MEMORY_PWM_VCOM; + ret =3D sharp_memory_init_pwm_vcom_signal(smd); + if (ret) + return dev_err_probe(dev, ret, + "Failed to initialize external COM signal\n"); + } else { + return dev_err_probe(dev, -EINVAL, "Invalid value set for vcom-mode\n"); + } + + drm->mode_config.funcs =3D &sharp_memory_mode_config_funcs; + smd->mode =3D spi_get_device_match_data(spi); + + smd->pitch =3D (SHARP_ADDR_PERIOD + smd->mode->hdisplay + SHARP_DUMMY_PER= IOD) / 8; + smd->tx_buffer_size =3D (SHARP_MODE_PERIOD + + (SHARP_ADDR_PERIOD + (smd->mode->hdisplay) + SHARP_DUMMY_PERIOD)= * + smd->mode->vdisplay) / 8; + + smd->tx_buffer =3D devm_kzalloc(&spi->dev, smd->tx_buffer_size, GFP_KERNE= L); + if (!smd->tx_buffer) + return -ENOMEM; + + mutex_init(&smd->tx_mutex); + + drm->mode_config.min_width =3D smd->mode->hdisplay; + drm->mode_config.max_width =3D smd->mode->hdisplay; + drm->mode_config.min_height =3D smd->mode->vdisplay; + drm->mode_config.max_height =3D smd->mode->vdisplay; + + ret =3D sharp_memory_pipe_init(drm, smd, sharp_memory_formats, + ARRAY_SIZE(sharp_memory_formats), + NULL); + if (ret) + return dev_err_probe(dev, ret, "Failed to initialize display pipeline.\n= "); + + drm_plane_enable_fb_damage_clips(&smd->plane); + drm_mode_config_reset(drm); + + ret =3D drm_dev_register(drm, 0); + if (ret) + return dev_err_probe(dev, ret, "Failed to register drm device.\n"); + + drm_fbdev_dma_setup(drm, 0); + + return 0; +} + +static void sharp_memory_remove(struct spi_device *spi) +{ + struct sharp_memory_device *smd =3D spi_get_drvdata(spi); + + drm_dev_unplug(&smd->drm); + drm_atomic_helper_shutdown(&smd->drm); +} + +static struct spi_driver sharp_memory_spi_driver =3D { + .driver =3D { + .name =3D "sharp_memory", + .of_match_table =3D sharp_memory_of_match, + }, + .probe =3D sharp_memory_probe, + .remove =3D sharp_memory_remove, + .id_table =3D sharp_memory_ids, +}; +module_spi_driver(sharp_memory_spi_driver); + +MODULE_AUTHOR("Alex Lanzano "); +MODULE_DESCRIPTION("SPI Protocol driver for the sharp_memory display"); +MODULE_LICENSE("GPL"); --=20 2.45.2